arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/sysdev.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/hpet.h>
   8 #include <linux/init.h>
   9 #include <linux/cpu.h>
  10 #include <linux/pm.h>
  11 #include <linux/io.h>
  12
  13 #include <asm/fixmap.h>
  14 #include <asm/i8253.h>
  15 #include <asm/hpet.h>
  16
  17 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  18 #define HPET_SHIFT                      22
  19
  20 /* FSEC = 10^-15
  21    NSEC = 10^-9 */
  22 #define FSEC_PER_NSEC                   1000000L
  23
  24 #define HPET_DEV_USED_BIT               2
  25 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  26 #define HPET_DEV_VALID                  0x8
  27 #define HPET_DEV_FSB_CAP                0x1000
  28 #define HPET_DEV_PERI_CAP               0x2000
  29
  30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
  31
  32 /*
  33  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  34  */
  35 unsigned long                           hpet_address;
  36 #ifdef CONFIG_PCI_MSI
  37 static unsigned long                    hpet_num_timers;
  38 #endif
  39 static void __iomem                     *hpet_virt_address;
  40
  41 struct hpet_dev {
  42         struct clock_event_device       evt;
  43         unsigned int                    num;
  44         int                             cpu;
  45         unsigned int                    irq;
  46         unsigned int                    flags;
  47         char                            name[10];
  48 };
  49
  50 unsigned long hpet_readl(unsigned long a)
  51 {
  52         return readl(hpet_virt_address + a);
  53 }
  54
  55 static inline void hpet_writel(unsigned long d, unsigned long a)
  56 {
  57         writel(d, hpet_virt_address + a);
  58 }
  59
  60 #ifdef CONFIG_X86_64
  61 #include <asm/pgtable.h>
  62 #endif
  63
  64 static inline void hpet_set_mapping(void)
  65 {
  66         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  67 #ifdef CONFIG_X86_64
  68         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
  69 #endif
  70 }
  71
  72 static inline void hpet_clear_mapping(void)
  73 {
  74         iounmap(hpet_virt_address);
  75         hpet_virt_address = NULL;
  76 }
  77
  78 /*
  79  * HPET command line enable / disable
  80  */
  81 static int boot_hpet_disable;
  82 int hpet_force_user;
  83
  84 static int __init hpet_setup(char *str)
  85 {
  86         if (str) {
  87                 if (!strncmp("disable", str, 7))
  88                         boot_hpet_disable = 1;
  89                 if (!strncmp("force", str, 5))
  90                         hpet_force_user = 1;
  91         }
  92         return 1;
  93 }
  94 __setup("hpet=", hpet_setup);
  95
  96 static int __init disable_hpet(char *str)
  97 {
  98         boot_hpet_disable = 1;
  99         return 1;
 100 }
 101 __setup("nohpet", disable_hpet);
 102
 103 static inline int is_hpet_capable(void)
 104 {
 105         return !boot_hpet_disable && hpet_address;
 106 }
 107
 108 /*
 109  * HPET timer interrupt enable / disable
 110  */
 111 static int hpet_legacy_int_enabled;
 112
 113 /**
 114  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 115  */
 116 int is_hpet_enabled(void)
 117 {
 118         return is_hpet_capable() && hpet_legacy_int_enabled;
 119 }
 120 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 121
 122 /*
 123  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 124  * timer 0 and timer 1 in case of RTC emulation.
 125  */
 126 #ifdef CONFIG_HPET
 127
 128 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 129
 130 static void hpet_reserve_platform_timers(unsigned long id)
 131 {
 132         struct hpet __iomem *hpet = hpet_virt_address;
 133         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 134         unsigned int nrtimers, i;
 135         struct hpet_data hd;
 136
 137         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 138
 139         memset(&hd, 0, sizeof(hd));
 140         hd.hd_phys_address      = hpet_address;
 141         hd.hd_address           = hpet;
 142         hd.hd_nirqs             = nrtimers;
 143         hpet_reserve_timer(&hd, 0);
 144
 145 #ifdef CONFIG_HPET_EMULATE_RTC
 146         hpet_reserve_timer(&hd, 1);
 147 #endif
 148
 149         /*
 150          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 151          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 152          * don't bother configuring *any* comparator interrupts.
 153          */
 154         hd.hd_irq[0] = HPET_LEGACY_8254;
 155         hd.hd_irq[1] = HPET_LEGACY_RTC;
 156
 157         for (i = 2; i < nrtimers; timer++, i++) {
 158                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 159                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 160         }
 161
 162         hpet_reserve_msi_timers(&hd);
 163
 164         hpet_alloc(&hd);
 165
 166 }
 167 #else
 168 static void hpet_reserve_platform_timers(unsigned long id) { }
 169 #endif
 170
 171 /*
 172  * Common hpet info
 173  */
 174 static unsigned long hpet_period;
 175
 176 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 177                           struct clock_event_device *evt);
 178 static int hpet_legacy_next_event(unsigned long delta,
 179                            struct clock_event_device *evt);
 180
 181 /*
 182  * The hpet clock event device
 183  */
 184 static struct clock_event_device hpet_clockevent = {
 185         .name           = "hpet",
 186         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 187         .set_mode       = hpet_legacy_set_mode,
 188         .set_next_event = hpet_legacy_next_event,
 189         .shift          = 32,
 190         .irq            = 0,
 191         .rating         = 50,
 192 };
 193
 194 static void hpet_start_counter(void)
 195 {
 196         unsigned long cfg = hpet_readl(HPET_CFG);
 197
 198         cfg &= ~HPET_CFG_ENABLE;
 199         hpet_writel(cfg, HPET_CFG);
 200         hpet_writel(0, HPET_COUNTER);
 201         hpet_writel(0, HPET_COUNTER + 4);
 202         cfg |= HPET_CFG_ENABLE;
 203         hpet_writel(cfg, HPET_CFG);
 204 }
 205
 206 static void hpet_resume_device(void)
 207 {
 208         force_hpet_resume();
 209 }
 210
 211 static void hpet_restart_counter(void)
 212 {
 213         hpet_resume_device();
 214         hpet_start_counter();
 215 }
 216
 217 static void hpet_enable_legacy_int(void)
 218 {
 219         unsigned long cfg = hpet_readl(HPET_CFG);
 220
 221         cfg |= HPET_CFG_LEGACY;
 222         hpet_writel(cfg, HPET_CFG);
 223         hpet_legacy_int_enabled = 1;
 224 }
 225
 226 static void hpet_legacy_clockevent_register(void)
 227 {
 228         /* Start HPET legacy interrupts */
 229         hpet_enable_legacy_int();
 230
 231         /*
 232          * The mult factor is defined as (include/linux/clockchips.h)
 233          *  mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
 234          * hpet_period is in units of femtoseconds (per cycle), so
 235          *  mult/2^shift = cyc/ns = 10^6/hpet_period
 236          *  mult = (10^6 * 2^shift)/hpet_period
 237          *  mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
 238          */
 239         hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
 240                                       hpet_period, hpet_clockevent.shift);
 241         /* Calculate the min / max delta */
 242         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
 243                                                            &hpet_clockevent);
 244         /* 5 usec minimum reprogramming delta. */
 245         hpet_clockevent.min_delta_ns = 5000;
 246
 247         /*
 248          * Start hpet with the boot cpu mask and make it
 249          * global after the IO_APIC has been initialized.
 250          */
 251         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 252         clockevents_register_device(&hpet_clockevent);
 253         global_clock_event = &hpet_clockevent;
 254         printk(KERN_DEBUG "hpet clockevent registered\n");
 255 }
 256
 257 static int hpet_setup_msi_irq(unsigned int irq);
 258
 259 static void hpet_set_mode(enum clock_event_mode mode,
 260                           struct clock_event_device *evt, int timer)
 261 {
 262         unsigned long cfg, cmp, now;
 263         uint64_t delta;
 264
 265         switch (mode) {
 266         case CLOCK_EVT_MODE_PERIODIC:
 267                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 268                 delta >>= evt->shift;
 269                 now = hpet_readl(HPET_COUNTER);
 270                 cmp = now + (unsigned long) delta;
 271                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 272                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 273                        HPET_TN_SETVAL | HPET_TN_32BIT;
 274                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 275                 /*
 276                  * The first write after writing TN_SETVAL to the
 277                  * config register sets the counter value, the second
 278                  * write sets the period.
 279                  */
 280                 hpet_writel(cmp, HPET_Tn_CMP(timer));
 281                 udelay(1);
 282                 hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
 283                 break;
 284
 285         case CLOCK_EVT_MODE_ONESHOT:
 286                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 287                 cfg &= ~HPET_TN_PERIODIC;
 288                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 289                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 290                 break;
 291
 292         case CLOCK_EVT_MODE_UNUSED:
 293         case CLOCK_EVT_MODE_SHUTDOWN:
 294                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 295                 cfg &= ~HPET_TN_ENABLE;
 296                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 297                 break;
 298
 299         case CLOCK_EVT_MODE_RESUME:
 300                 if (timer == 0) {
 301                         hpet_enable_legacy_int();
 302                 } else {
 303                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 304                         hpet_setup_msi_irq(hdev->irq);
 305                         disable_irq(hdev->irq);
 306                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 307                         enable_irq(hdev->irq);
 308                 }
 309                 break;
 310         }
 311 }
 312
 313 static int hpet_next_event(unsigned long delta,
 314                            struct clock_event_device *evt, int timer)
 315 {
 316         u32 cnt;
 317
 318         cnt = hpet_readl(HPET_COUNTER);
 319         cnt += (u32) delta;
 320         hpet_writel(cnt, HPET_Tn_CMP(timer));
 321
 322         /*
 323          * We need to read back the CMP register to make sure that
 324          * what we wrote hit the chip before we compare it to the
 325          * counter.
 326          */
 327         WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt);
 328
 329         return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
 330 }
 331
 332 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 333                         struct clock_event_device *evt)
 334 {
 335         hpet_set_mode(mode, evt, 0);
 336 }
 337
 338 static int hpet_legacy_next_event(unsigned long delta,
 339                         struct clock_event_device *evt)
 340 {
 341         return hpet_next_event(delta, evt, 0);
 342 }
 343
 344 /*
 345  * HPET MSI Support
 346  */
 347 #ifdef CONFIG_PCI_MSI
 348
 349 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 350 static struct hpet_dev  *hpet_devs;
 351
 352 void hpet_msi_unmask(unsigned int irq)
 353 {
 354         struct hpet_dev *hdev = get_irq_data(irq);
 355         unsigned long cfg;
 356
 357         /* unmask it */
 358         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 359         cfg |= HPET_TN_FSB;
 360         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 361 }
 362
 363 void hpet_msi_mask(unsigned int irq)
 364 {
 365         unsigned long cfg;
 366         struct hpet_dev *hdev = get_irq_data(irq);
 367
 368         /* mask it */
 369         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 370         cfg &= ~HPET_TN_FSB;
 371         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 372 }
 373
 374 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
 375 {
 376         struct hpet_dev *hdev = get_irq_data(irq);
 377
 378         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 379         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 380 }
 381
 382 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
 383 {
 384         struct hpet_dev *hdev = get_irq_data(irq);
 385
 386         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 387         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 388         msg->address_hi = 0;
 389 }
 390
 391 static void hpet_msi_set_mode(enum clock_event_mode mode,
 392                                 struct clock_event_device *evt)
 393 {
 394         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 395         hpet_set_mode(mode, evt, hdev->num);
 396 }
 397
 398 static int hpet_msi_next_event(unsigned long delta,
 399                                 struct clock_event_device *evt)
 400 {
 401         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 402         return hpet_next_event(delta, evt, hdev->num);
 403 }
 404
 405 static int hpet_setup_msi_irq(unsigned int irq)
 406 {
 407         if (arch_setup_hpet_msi(irq)) {
 408                 destroy_irq(irq);
 409                 return -EINVAL;
 410         }
 411         return 0;
 412 }
 413
 414 static int hpet_assign_irq(struct hpet_dev *dev)
 415 {
 416         unsigned int irq;
 417
 418         irq = create_irq();
 419         if (!irq)
 420                 return -EINVAL;
 421
 422         set_irq_data(irq, dev);
 423
 424         if (hpet_setup_msi_irq(irq))
 425                 return -EINVAL;
 426
 427         dev->irq = irq;
 428         return 0;
 429 }
 430
 431 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 432 {
 433         struct hpet_dev *dev = (struct hpet_dev *)data;
 434         struct clock_event_device *hevt = &dev->evt;
 435
 436         if (!hevt->event_handler) {
 437                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 438                                 dev->num);
 439                 return IRQ_HANDLED;
 440         }
 441
 442         hevt->event_handler(hevt);
 443         return IRQ_HANDLED;
 444 }
 445
 446 static int hpet_setup_irq(struct hpet_dev *dev)
 447 {
 448
 449         if (request_irq(dev->irq, hpet_interrupt_handler,
 450                         IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev))
 451                 return -1;
 452
 453         disable_irq(dev->irq);
 454         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 455         enable_irq(dev->irq);
 456
 457         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 458                          dev->name, dev->irq);
 459
 460         return 0;
 461 }
 462
 463 /* This should be called in specific @cpu */
 464 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 465 {
 466         struct clock_event_device *evt = &hdev->evt;
 467         uint64_t hpet_freq;
 468
 469         WARN_ON(cpu != smp_processor_id());
 470         if (!(hdev->flags & HPET_DEV_VALID))
 471                 return;
 472
 473         if (hpet_setup_msi_irq(hdev->irq))
 474                 return;
 475
 476         hdev->cpu = cpu;
 477         per_cpu(cpu_hpet_dev, cpu) = hdev;
 478         evt->name = hdev->name;
 479         hpet_setup_irq(hdev);
 480         evt->irq = hdev->irq;
 481
 482         evt->rating = 110;
 483         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 484         if (hdev->flags & HPET_DEV_PERI_CAP)
 485                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 486
 487         evt->set_mode = hpet_msi_set_mode;
 488         evt->set_next_event = hpet_msi_next_event;
 489         evt->shift = 32;
 490
 491         /*
 492          * The period is a femto seconds value. We need to calculate the
 493          * scaled math multiplication factor for nanosecond to hpet tick
 494          * conversion.
 495          */
 496         hpet_freq = 1000000000000000ULL;
 497         do_div(hpet_freq, hpet_period);
 498         evt->mult = div_sc((unsigned long) hpet_freq,
 499                                       NSEC_PER_SEC, evt->shift);
 500         /* Calculate the max delta */
 501         evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
 502         /* 5 usec minimum reprogramming delta. */
 503         evt->min_delta_ns = 5000;
 504
 505         evt->cpumask = cpumask_of(hdev->cpu);
 506         clockevents_register_device(evt);
 507 }
 508
 509 #ifdef CONFIG_HPET
 510 /* Reserve at least one timer for userspace (/dev/hpet) */
 511 #define RESERVE_TIMERS 1
 512 #else
 513 #define RESERVE_TIMERS 0
 514 #endif
 515
 516 static void hpet_msi_capability_lookup(unsigned int start_timer)
 517 {
 518         unsigned int id;
 519         unsigned int num_timers;
 520         unsigned int num_timers_used = 0;
 521         int i;
 522
 523         id = hpet_readl(HPET_ID);
 524
 525         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 526         num_timers++; /* Value read out starts from 0 */
 527
 528         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 529         if (!hpet_devs)
 530                 return;
 531
 532         hpet_num_timers = num_timers;
 533
 534         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 535                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 536                 unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
 537
 538                 /* Only consider HPET timer with MSI support */
 539                 if (!(cfg & HPET_TN_FSB_CAP))
 540                         continue;
 541
 542                 hdev->flags = 0;
 543                 if (cfg & HPET_TN_PERIODIC_CAP)
 544                         hdev->flags |= HPET_DEV_PERI_CAP;
 545                 hdev->num = i;
 546
 547                 sprintf(hdev->name, "hpet%d", i);
 548                 if (hpet_assign_irq(hdev))
 549                         continue;
 550
 551                 hdev->flags |= HPET_DEV_FSB_CAP;
 552                 hdev->flags |= HPET_DEV_VALID;
 553                 num_timers_used++;
 554                 if (num_timers_used == num_possible_cpus())
 555                         break;
 556         }
 557
 558         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 559                 num_timers, num_timers_used);
 560 }
 561
 562 #ifdef CONFIG_HPET
 563 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 564 {
 565         int i;
 566
 567         if (!hpet_devs)
 568                 return;
 569
 570         for (i = 0; i < hpet_num_timers; i++) {
 571                 struct hpet_dev *hdev = &hpet_devs[i];
 572
 573                 if (!(hdev->flags & HPET_DEV_VALID))
 574                         continue;
 575
 576                 hd->hd_irq[hdev->num] = hdev->irq;
 577                 hpet_reserve_timer(hd, hdev->num);
 578         }
 579 }
 580 #endif
 581
 582 static struct hpet_dev *hpet_get_unused_timer(void)
 583 {
 584         int i;
 585
 586         if (!hpet_devs)
 587                 return NULL;
 588
 589         for (i = 0; i < hpet_num_timers; i++) {
 590                 struct hpet_dev *hdev = &hpet_devs[i];
 591
 592                 if (!(hdev->flags & HPET_DEV_VALID))
 593                         continue;
 594                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 595                         (unsigned long *)&hdev->flags))
 596                         continue;
 597                 return hdev;
 598         }
 599         return NULL;
 600 }
 601
 602 struct hpet_work_struct {
 603         struct delayed_work work;
 604         struct completion complete;
 605 };
 606
 607 static void hpet_work(struct work_struct *w)
 608 {
 609         struct hpet_dev *hdev;
 610         int cpu = smp_processor_id();
 611         struct hpet_work_struct *hpet_work;
 612
 613         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 614
 615         hdev = hpet_get_unused_timer();
 616         if (hdev)
 617                 init_one_hpet_msi_clockevent(hdev, cpu);
 618
 619         complete(&hpet_work->complete);
 620 }
 621
 622 static int hpet_cpuhp_notify(struct notifier_block *n,
 623                 unsigned long action, void *hcpu)
 624 {
 625         unsigned long cpu = (unsigned long)hcpu;
 626         struct hpet_work_struct work;
 627         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 628
 629         switch (action & 0xf) {
 630         case CPU_ONLINE:
 631                 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
 632                 init_completion(&work.complete);
 633                 /* FIXME: add schedule_work_on() */
 634                 schedule_delayed_work_on(cpu, &work.work, 0);
 635                 wait_for_completion(&work.complete);
 636                 destroy_timer_on_stack(&work.work.timer);
 637                 break;
 638         case CPU_DEAD:
 639                 if (hdev) {
 640                         free_irq(hdev->irq, hdev);
 641                         hdev->flags &= ~HPET_DEV_USED;
 642                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 643                 }
 644                 break;
 645         }
 646         return NOTIFY_OK;
 647 }
 648 #else
 649
 650 static int hpet_setup_msi_irq(unsigned int irq)
 651 {
 652         return 0;
 653 }
 654 static void hpet_msi_capability_lookup(unsigned int start_timer)
 655 {
 656         return;
 657 }
 658
 659 #ifdef CONFIG_HPET
 660 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 661 {
 662         return;
 663 }
 664 #endif
 665
 666 static int hpet_cpuhp_notify(struct notifier_block *n,
 667                 unsigned long action, void *hcpu)
 668 {
 669         return NOTIFY_OK;
 670 }
 671
 672 #endif
 673
 674 /*
 675  * Clock source related code
 676  */
 677 static cycle_t read_hpet(void)
 678 {
 679         return (cycle_t)hpet_readl(HPET_COUNTER);
 680 }
 681
 682 #ifdef CONFIG_X86_64
 683 static cycle_t __vsyscall_fn vread_hpet(void)
 684 {
 685         return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
 686 }
 687 #endif
 688
 689 static struct clocksource clocksource_hpet = {
 690         .name           = "hpet",
 691         .rating         = 250,
 692         .read           = read_hpet,
 693         .mask           = HPET_MASK,
 694         .shift          = HPET_SHIFT,
 695         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 696         .resume         = hpet_restart_counter,
 697 #ifdef CONFIG_X86_64
 698         .vread          = vread_hpet,
 699 #endif
 700 };
 701
 702 static int hpet_clocksource_register(void)
 703 {
 704         u64 start, now;
 705         cycle_t t1;
 706
 707         /* Start the counter */
 708         hpet_start_counter();
 709
 710         /* Verify whether hpet counter works */
 711         t1 = read_hpet();
 712         rdtscll(start);
 713
 714         /*
 715          * We don't know the TSC frequency yet, but waiting for
 716          * 200000 TSC cycles is safe:
 717          * 4 GHz == 50us
 718          * 1 GHz == 200us
 719          */
 720         do {
 721                 rep_nop();
 722                 rdtscll(now);
 723         } while ((now - start) < 200000UL);
 724
 725         if (t1 == read_hpet()) {
 726                 printk(KERN_WARNING
 727                        "HPET counter not counting. HPET disabled\n");
 728                 return -ENODEV;
 729         }
 730
 731         /*
 732          * The definition of mult is (include/linux/clocksource.h)
 733          * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
 734          * so we first need to convert hpet_period to ns/cyc units:
 735          *  mult/2^shift = ns/cyc = hpet_period/10^6
 736          *  mult = (hpet_period * 2^shift)/10^6
 737          *  mult = (hpet_period << shift)/FSEC_PER_NSEC
 738          */
 739         clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
 740
 741         clocksource_register(&clocksource_hpet);
 742
 743         return 0;
 744 }
 745
 746 /**
 747  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 748  */
 749 int __init hpet_enable(void)
 750 {
 751         unsigned long id;
 752         int i;
 753
 754         if (!is_hpet_capable())
 755                 return 0;
 756
 757         hpet_set_mapping();
 758
 759         /*
 760          * Read the period and check for a sane value:
 761          */
 762         hpet_period = hpet_readl(HPET_PERIOD);
 763
 764         /*
 765          * AMD SB700 based systems with spread spectrum enabled use a
 766          * SMM based HPET emulation to provide proper frequency
 767          * setting. The SMM code is initialized with the first HPET
 768          * register access and takes some time to complete. During
 769          * this time the config register reads 0xffffffff. We check
 770          * for max. 1000 loops whether the config register reads a non
 771          * 0xffffffff value to make sure that HPET is up and running
 772          * before we go further. A counting loop is safe, as the HPET
 773          * access takes thousands of CPU cycles. On non SB700 based
 774          * machines this check is only done once and has no side
 775          * effects.
 776          */
 777         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 778                 if (i == 1000) {
 779                         printk(KERN_WARNING
 780                                "HPET config register value = 0xFFFFFFFF. "
 781                                "Disabling HPET\n");
 782                         goto out_nohpet;
 783                 }
 784         }
 785
 786         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 787                 goto out_nohpet;
 788
 789         /*
 790          * Read the HPET ID register to retrieve the IRQ routing
 791          * information and the number of channels
 792          */
 793         id = hpet_readl(HPET_ID);
 794
 795 #ifdef CONFIG_HPET_EMULATE_RTC
 796         /*
 797          * The legacy routing mode needs at least two channels, tick timer
 798          * and the rtc emulation channel.
 799          */
 800         if (!(id & HPET_ID_NUMBER))
 801                 goto out_nohpet;
 802 #endif
 803
 804         if (hpet_clocksource_register())
 805                 goto out_nohpet;
 806
 807         if (id & HPET_ID_LEGSUP) {
 808                 hpet_legacy_clockevent_register();
 809                 hpet_msi_capability_lookup(2);
 810                 return 1;
 811         }
 812         hpet_msi_capability_lookup(0);
 813         return 0;
 814
 815 out_nohpet:
 816         hpet_clear_mapping();
 817         hpet_address = 0;
 818         return 0;
 819 }
 820
 821 /*
 822  * Needs to be late, as the reserve_timer code calls kalloc !
 823  *
 824  * Not a problem on i386 as hpet_enable is called from late_time_init,
 825  * but on x86_64 it is necessary !
 826  */
 827 static __init int hpet_late_init(void)
 828 {
 829         int cpu;
 830
 831         if (boot_hpet_disable)
 832                 return -ENODEV;
 833
 834         if (!hpet_address) {
 835                 if (!force_hpet_address)
 836                         return -ENODEV;
 837
 838                 hpet_address = force_hpet_address;
 839                 hpet_enable();
 840         }
 841
 842         if (!hpet_virt_address)
 843                 return -ENODEV;
 844
 845         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 846
 847         for_each_online_cpu(cpu) {
 848                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 849         }
 850
 851         /* This notifier should be called after workqueue is ready */
 852         hotcpu_notifier(hpet_cpuhp_notify, -20);
 853
 854         return 0;
 855 }
 856 fs_initcall(hpet_late_init);
 857
 858 void hpet_disable(void)
 859 {
 860         if (is_hpet_capable()) {
 861                 unsigned long cfg = hpet_readl(HPET_CFG);
 862
 863                 if (hpet_legacy_int_enabled) {
 864                         cfg &= ~HPET_CFG_LEGACY;
 865                         hpet_legacy_int_enabled = 0;
 866                 }
 867                 cfg &= ~HPET_CFG_ENABLE;
 868                 hpet_writel(cfg, HPET_CFG);
 869         }
 870 }
 871
 872 #ifdef CONFIG_HPET_EMULATE_RTC
 873
 874 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 875  * is enabled, we support RTC interrupt functionality in software.
 876  * RTC has 3 kinds of interrupts:
 877  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 878  *    is updated
 879  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 880  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 881  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 882  * (1) and (2) above are implemented using polling at a frequency of
 883  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 884  * overhead. (DEFAULT_RTC_INT_FREQ)
 885  * For (3), we use interrupts at 64Hz or user specified periodic
 886  * frequency, whichever is higher.
 887  */
 888 #include <linux/mc146818rtc.h>
 889 #include <linux/rtc.h>
 890 #include <asm/rtc.h>
 891
 892 #define DEFAULT_RTC_INT_FREQ    64
 893 #define DEFAULT_RTC_SHIFT       6
 894 #define RTC_NUM_INTS            1
 895
 896 static unsigned long hpet_rtc_flags;
 897 static int hpet_prev_update_sec;
 898 static struct rtc_time hpet_alarm_time;
 899 static unsigned long hpet_pie_count;
 900 static unsigned long hpet_t1_cmp;
 901 static unsigned long hpet_default_delta;
 902 static unsigned long hpet_pie_delta;
 903 static unsigned long hpet_pie_limit;
 904
 905 static rtc_irq_handler irq_handler;
 906
 907 /*
 908  * Registers a IRQ handler.
 909  */
 910 int hpet_register_irq_handler(rtc_irq_handler handler)
 911 {
 912         if (!is_hpet_enabled())
 913                 return -ENODEV;
 914         if (irq_handler)
 915                 return -EBUSY;
 916
 917         irq_handler = handler;
 918
 919         return 0;
 920 }
 921 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
 922
 923 /*
 924  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
 925  * and does cleanup.
 926  */
 927 void hpet_unregister_irq_handler(rtc_irq_handler handler)
 928 {
 929         if (!is_hpet_enabled())
 930                 return;
 931
 932         irq_handler = NULL;
 933         hpet_rtc_flags = 0;
 934 }
 935 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
 936
 937 /*
 938  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 939  * is not supported by all HPET implementations for timer 1.
 940  *
 941  * hpet_rtc_timer_init() is called when the rtc is initialized.
 942  */
 943 int hpet_rtc_timer_init(void)
 944 {
 945         unsigned long cfg, cnt, delta, flags;
 946
 947         if (!is_hpet_enabled())
 948                 return 0;
 949
 950         if (!hpet_default_delta) {
 951                 uint64_t clc;
 952
 953                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 954                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
 955                 hpet_default_delta = (unsigned long) clc;
 956         }
 957
 958         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 959                 delta = hpet_default_delta;
 960         else
 961                 delta = hpet_pie_delta;
 962
 963         local_irq_save(flags);
 964
 965         cnt = delta + hpet_readl(HPET_COUNTER);
 966         hpet_writel(cnt, HPET_T1_CMP);
 967         hpet_t1_cmp = cnt;
 968
 969         cfg = hpet_readl(HPET_T1_CFG);
 970         cfg &= ~HPET_TN_PERIODIC;
 971         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 972         hpet_writel(cfg, HPET_T1_CFG);
 973
 974         local_irq_restore(flags);
 975
 976         return 1;
 977 }
 978 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
 979
 980 /*
 981  * The functions below are called from rtc driver.
 982  * Return 0 if HPET is not being used.
 983  * Otherwise do the necessary changes and return 1.
 984  */
 985 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
 986 {
 987         if (!is_hpet_enabled())
 988                 return 0;
 989
 990         hpet_rtc_flags &= ~bit_mask;
 991         return 1;
 992 }
 993 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
 994
 995 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
 996 {
 997         unsigned long oldbits = hpet_rtc_flags;
 998
 999         if (!is_hpet_enabled())
1000                 return 0;
1001
1002         hpet_rtc_flags |= bit_mask;
1003
1004         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1005                 hpet_prev_update_sec = -1;
1006
1007         if (!oldbits)
1008                 hpet_rtc_timer_init();
1009
1010         return 1;
1011 }
1012 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1013
1014 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1015                         unsigned char sec)
1016 {
1017         if (!is_hpet_enabled())
1018                 return 0;
1019
1020         hpet_alarm_time.tm_hour = hrs;
1021         hpet_alarm_time.tm_min = min;
1022         hpet_alarm_time.tm_sec = sec;
1023
1024         return 1;
1025 }
1026 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1027
1028 int hpet_set_periodic_freq(unsigned long freq)
1029 {
1030         uint64_t clc;
1031
1032         if (!is_hpet_enabled())
1033                 return 0;
1034
1035         if (freq <= DEFAULT_RTC_INT_FREQ)
1036                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1037         else {
1038                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1039                 do_div(clc, freq);
1040                 clc >>= hpet_clockevent.shift;
1041                 hpet_pie_delta = (unsigned long) clc;
1042         }
1043         return 1;
1044 }
1045 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1046
1047 int hpet_rtc_dropped_irq(void)
1048 {
1049         return is_hpet_enabled();
1050 }
1051 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1052
1053 static void hpet_rtc_timer_reinit(void)
1054 {
1055         unsigned long cfg, delta;
1056         int lost_ints = -1;
1057
1058         if (unlikely(!hpet_rtc_flags)) {
1059                 cfg = hpet_readl(HPET_T1_CFG);
1060                 cfg &= ~HPET_TN_ENABLE;
1061                 hpet_writel(cfg, HPET_T1_CFG);
1062                 return;
1063         }
1064
1065         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1066                 delta = hpet_default_delta;
1067         else
1068                 delta = hpet_pie_delta;
1069
1070         /*
1071          * Increment the comparator value until we are ahead of the
1072          * current count.
1073          */
1074         do {
1075                 hpet_t1_cmp += delta;
1076                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1077                 lost_ints++;
1078         } while ((s32)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
1079
1080         if (lost_ints) {
1081                 if (hpet_rtc_flags & RTC_PIE)
1082                         hpet_pie_count += lost_ints;
1083                 if (printk_ratelimit())
1084                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1085                                 lost_ints);
1086         }
1087 }
1088
1089 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1090 {
1091         struct rtc_time curr_time;
1092         unsigned long rtc_int_flag = 0;
1093
1094         hpet_rtc_timer_reinit();
1095         memset(&curr_time, 0, sizeof(struct rtc_time));
1096
1097         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1098                 get_rtc_time(&curr_time);
1099
1100         if (hpet_rtc_flags & RTC_UIE &&
1101             curr_time.tm_sec != hpet_prev_update_sec) {
1102                 if (hpet_prev_update_sec >= 0)
1103                         rtc_int_flag = RTC_UF;
1104                 hpet_prev_update_sec = curr_time.tm_sec;
1105         }
1106
1107         if (hpet_rtc_flags & RTC_PIE &&
1108             ++hpet_pie_count >= hpet_pie_limit) {
1109                 rtc_int_flag |= RTC_PF;
1110                 hpet_pie_count = 0;
1111         }
1112
1113         if (hpet_rtc_flags & RTC_AIE &&
1114             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1115             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1116             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1117                         rtc_int_flag |= RTC_AF;
1118
1119         if (rtc_int_flag) {
1120                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1121                 if (irq_handler)
1122                         irq_handler(rtc_int_flag, dev_id);
1123         }
1124         return IRQ_HANDLED;
1125 }
1126 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1127 #endif