arch/x86/kernel/cpu/perf_event_amd.c

   1 #include <linux/perf_event.h>
   2 #include <linux/types.h>
   3 #include <linux/init.h>
   4 #include <linux/slab.h>
   5 #include <asm/apicdef.h>
   6
   7 #include "perf_event.h"
   8
   9 static __initconst const u64 amd_hw_cache_event_ids
  10                                 [PERF_COUNT_HW_CACHE_MAX]
  11                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  12                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  13 {
  14  [ C(L1D) ] = {
  15         [ C(OP_READ) ] = {
  16                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
  17                 [ C(RESULT_MISS)   ] = 0x0141, /* Data Cache Misses          */
  18         },
  19         [ C(OP_WRITE) ] = {
  20                 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
  21                 [ C(RESULT_MISS)   ] = 0,
  22         },
  23         [ C(OP_PREFETCH) ] = {
  24                 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
  25                 [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
  26         },
  27  },
  28  [ C(L1I ) ] = {
  29         [ C(OP_READ) ] = {
  30                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
  31                 [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
  32         },
  33         [ C(OP_WRITE) ] = {
  34                 [ C(RESULT_ACCESS) ] = -1,
  35                 [ C(RESULT_MISS)   ] = -1,
  36         },
  37         [ C(OP_PREFETCH) ] = {
  38                 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
  39                 [ C(RESULT_MISS)   ] = 0,
  40         },
  41  },
  42  [ C(LL  ) ] = {
  43         [ C(OP_READ) ] = {
  44                 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
  45                 [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
  46         },
  47         [ C(OP_WRITE) ] = {
  48                 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
  49                 [ C(RESULT_MISS)   ] = 0,
  50         },
  51         [ C(OP_PREFETCH) ] = {
  52                 [ C(RESULT_ACCESS) ] = 0,
  53                 [ C(RESULT_MISS)   ] = 0,
  54         },
  55  },
  56  [ C(DTLB) ] = {
  57         [ C(OP_READ) ] = {
  58                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
  59                 [ C(RESULT_MISS)   ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
  60         },
  61         [ C(OP_WRITE) ] = {
  62                 [ C(RESULT_ACCESS) ] = 0,
  63                 [ C(RESULT_MISS)   ] = 0,
  64         },
  65         [ C(OP_PREFETCH) ] = {
  66                 [ C(RESULT_ACCESS) ] = 0,
  67                 [ C(RESULT_MISS)   ] = 0,
  68         },
  69  },
  70  [ C(ITLB) ] = {
  71         [ C(OP_READ) ] = {
  72                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
  73                 [ C(RESULT_MISS)   ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
  74         },
  75         [ C(OP_WRITE) ] = {
  76                 [ C(RESULT_ACCESS) ] = -1,
  77                 [ C(RESULT_MISS)   ] = -1,
  78         },
  79         [ C(OP_PREFETCH) ] = {
  80                 [ C(RESULT_ACCESS) ] = -1,
  81                 [ C(RESULT_MISS)   ] = -1,
  82         },
  83  },
  84  [ C(BPU ) ] = {
  85         [ C(OP_READ) ] = {
  86                 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
  87                 [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
  88         },
  89         [ C(OP_WRITE) ] = {
  90                 [ C(RESULT_ACCESS) ] = -1,
  91                 [ C(RESULT_MISS)   ] = -1,
  92         },
  93         [ C(OP_PREFETCH) ] = {
  94                 [ C(RESULT_ACCESS) ] = -1,
  95                 [ C(RESULT_MISS)   ] = -1,
  96         },
  97  },
  98  [ C(NODE) ] = {
  99         [ C(OP_READ) ] = {
 100                 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
 101                 [ C(RESULT_MISS)   ] = 0x98e9, /* CPU Request to Memory, r   */
 102         },
 103         [ C(OP_WRITE) ] = {
 104                 [ C(RESULT_ACCESS) ] = -1,
 105                 [ C(RESULT_MISS)   ] = -1,
 106         },
 107         [ C(OP_PREFETCH) ] = {
 108                 [ C(RESULT_ACCESS) ] = -1,
 109                 [ C(RESULT_MISS)   ] = -1,
 110         },
 111  },
 112 };
 113
 114 /*
 115  * AMD Performance Monitor K7 and later.
 116  */
 117 static const u64 amd_perfmon_event_map[] =
 118 {
 119   [PERF_COUNT_HW_CPU_CYCLES]                    = 0x0076,
 120   [PERF_COUNT_HW_INSTRUCTIONS]                  = 0x00c0,
 121   [PERF_COUNT_HW_CACHE_REFERENCES]              = 0x0080,
 122   [PERF_COUNT_HW_CACHE_MISSES]                  = 0x0081,
 123   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]           = 0x00c2,
 124   [PERF_COUNT_HW_BRANCH_MISSES]                 = 0x00c3,
 125   [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]       = 0x00d0, /* "Decoder empty" event */
 126   [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]        = 0x00d1, /* "Dispatch stalls" event */
 127 };
 128
 129 static u64 amd_pmu_event_map(int hw_event)
 130 {
 131         return amd_perfmon_event_map[hw_event];
 132 }
 133
 134 static int amd_pmu_hw_config(struct perf_event *event)
 135 {
 136         int ret = x86_pmu_hw_config(event);
 137
 138         if (ret)
 139                 return ret;
 140
 141         if (event->attr.type != PERF_TYPE_RAW)
 142                 return 0;
 143
 144         event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
 145
 146         return 0;
 147 }
 148
 149 /*
 150  * AMD64 events are detected based on their event codes.
 151  */
 152 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc)
 153 {
 154         return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff);
 155 }
 156
 157 static inline int amd_is_nb_event(struct hw_perf_event *hwc)
 158 {
 159         return (hwc->config & 0xe0) == 0xe0;
 160 }
 161
 162 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 163 {
 164         struct amd_nb *nb = cpuc->amd_nb;
 165
 166         return nb && nb->nb_id != -1;
 167 }
 168
 169 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
 170                                       struct perf_event *event)
 171 {
 172         struct hw_perf_event *hwc = &event->hw;
 173         struct amd_nb *nb = cpuc->amd_nb;
 174         int i;
 175
 176         /*
 177          * only care about NB events
 178          */
 179         if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
 180                 return;
 181
 182         /*
 183          * need to scan whole list because event may not have
 184          * been assigned during scheduling
 185          *
 186          * no race condition possible because event can only
 187          * be removed on one CPU at a time AND PMU is disabled
 188          * when we come here
 189          */
 190         for (i = 0; i < x86_pmu.num_counters; i++) {
 191                 if (nb->owners[i] == event) {
 192                         cmpxchg(nb->owners+i, event, NULL);
 193                         break;
 194                 }
 195         }
 196 }
 197
 198  /*
 199   * AMD64 NorthBridge events need special treatment because
 200   * counter access needs to be synchronized across all cores
 201   * of a package. Refer to BKDG section 3.12
 202   *
 203   * NB events are events measuring L3 cache, Hypertransport
 204   * traffic. They are identified by an event code >= 0xe00.
 205   * They measure events on the NorthBride which is shared
 206   * by all cores on a package. NB events are counted on a
 207   * shared set of counters. When a NB event is programmed
 208   * in a counter, the data actually comes from a shared
 209   * counter. Thus, access to those counters needs to be
 210   * synchronized.
 211   *
 212   * We implement the synchronization such that no two cores
 213   * can be measuring NB events using the same counters. Thus,
 214   * we maintain a per-NB allocation table. The available slot
 215   * is propagated using the event_constraint structure.
 216   *
 217   * We provide only one choice for each NB event based on
 218   * the fact that only NB events have restrictions. Consequently,
 219   * if a counter is available, there is a guarantee the NB event
 220   * will be assigned to it. If no slot is available, an empty
 221   * constraint is returned and scheduling will eventually fail
 222   * for this event.
 223   *
 224   * Note that all cores attached the same NB compete for the same
 225   * counters to host NB events, this is why we use atomic ops. Some
 226   * multi-chip CPUs may have more than one NB.
 227   *
 228   * Given that resources are allocated (cmpxchg), they must be
 229   * eventually freed for others to use. This is accomplished by
 230   * calling amd_put_event_constraints().
 231   *
 232   * Non NB events are not impacted by this restriction.
 233   */
 234 static struct event_constraint *
 235 amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 236 {
 237         struct hw_perf_event *hwc = &event->hw;
 238         struct amd_nb *nb = cpuc->amd_nb;
 239         struct perf_event *old = NULL;
 240         int max = x86_pmu.num_counters;
 241         int i, j, k = -1;
 242
 243         /*
 244          * if not NB event or no NB, then no constraints
 245          */
 246         if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
 247                 return &unconstrained;
 248
 249         /*
 250          * detect if already present, if so reuse
 251          *
 252          * cannot merge with actual allocation
 253          * because of possible holes
 254          *
 255          * event can already be present yet not assigned (in hwc->idx)
 256          * because of successive calls to x86_schedule_events() from
 257          * hw_perf_group_sched_in() without hw_perf_enable()
 258          */
 259         for (i = 0; i < max; i++) {
 260                 /*
 261                  * keep track of first free slot
 262                  */
 263                 if (k == -1 && !nb->owners[i])
 264                         k = i;
 265
 266                 /* already present, reuse */
 267                 if (nb->owners[i] == event)
 268                         goto done;
 269         }
 270         /*
 271          * not present, so grab a new slot
 272          * starting either at:
 273          */
 274         if (hwc->idx != -1) {
 275                 /* previous assignment */
 276                 i = hwc->idx;
 277         } else if (k != -1) {
 278                 /* start from free slot found */
 279                 i = k;
 280         } else {
 281                 /*
 282                  * event not found, no slot found in
 283                  * first pass, try again from the
 284                  * beginning
 285                  */
 286                 i = 0;
 287         }
 288         j = i;
 289         do {
 290                 old = cmpxchg(nb->owners+i, NULL, event);
 291                 if (!old)
 292                         break;
 293                 if (++i == max)
 294                         i = 0;
 295         } while (i != j);
 296 done:
 297         if (!old)
 298                 return &nb->event_constraints[i];
 299
 300         return &emptyconstraint;
 301 }
 302
 303 static struct amd_nb *amd_alloc_nb(int cpu)
 304 {
 305         struct amd_nb *nb;
 306         int i;
 307
 308         nb = kmalloc_node(sizeof(struct amd_nb), GFP_KERNEL | __GFP_ZERO,
 309                           cpu_to_node(cpu));
 310         if (!nb)
 311                 return NULL;
 312
 313         nb->nb_id = -1;
 314
 315         /*
 316          * initialize all possible NB constraints
 317          */
 318         for (i = 0; i < x86_pmu.num_counters; i++) {
 319                 __set_bit(i, nb->event_constraints[i].idxmsk);
 320                 nb->event_constraints[i].weight = 1;
 321         }
 322         return nb;
 323 }
 324
 325 static int amd_pmu_cpu_prepare(int cpu)
 326 {
 327         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 328
 329         WARN_ON_ONCE(cpuc->amd_nb);
 330
 331         if (boot_cpu_data.x86_max_cores < 2)
 332                 return NOTIFY_OK;
 333
 334         cpuc->amd_nb = amd_alloc_nb(cpu);
 335         if (!cpuc->amd_nb)
 336                 return NOTIFY_BAD;
 337
 338         return NOTIFY_OK;
 339 }
 340
 341 static void amd_pmu_cpu_starting(int cpu)
 342 {
 343         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 344         struct amd_nb *nb;
 345         int i, nb_id;
 346
 347         if (boot_cpu_data.x86_max_cores < 2)
 348                 return;
 349
 350         nb_id = amd_get_nb_id(cpu);
 351         WARN_ON_ONCE(nb_id == BAD_APICID);
 352
 353         for_each_online_cpu(i) {
 354                 nb = per_cpu(cpu_hw_events, i).amd_nb;
 355                 if (WARN_ON_ONCE(!nb))
 356                         continue;
 357
 358                 if (nb->nb_id == nb_id) {
 359                         cpuc->kfree_on_online = cpuc->amd_nb;
 360                         cpuc->amd_nb = nb;
 361                         break;
 362                 }
 363         }
 364
 365         cpuc->amd_nb->nb_id = nb_id;
 366         cpuc->amd_nb->refcnt++;
 367 }
 368
 369 static void amd_pmu_cpu_dead(int cpu)
 370 {
 371         struct cpu_hw_events *cpuhw;
 372
 373         if (boot_cpu_data.x86_max_cores < 2)
 374                 return;
 375
 376         cpuhw = &per_cpu(cpu_hw_events, cpu);
 377
 378         if (cpuhw->amd_nb) {
 379                 struct amd_nb *nb = cpuhw->amd_nb;
 380
 381                 if (nb->nb_id == -1 || --nb->refcnt == 0)
 382                         kfree(nb);
 383
 384                 cpuhw->amd_nb = NULL;
 385         }
 386 }
 387
 388 static __initconst const struct x86_pmu amd_pmu = {
 389         .name                   = "AMD",
 390         .handle_irq             = x86_pmu_handle_irq,
 391         .disable_all            = x86_pmu_disable_all,
 392         .enable_all             = x86_pmu_enable_all,
 393         .enable                 = x86_pmu_enable_event,
 394         .disable                = x86_pmu_disable_event,
 395         .hw_config              = amd_pmu_hw_config,
 396         .schedule_events        = x86_schedule_events,
 397         .eventsel               = MSR_K7_EVNTSEL0,
 398         .perfctr                = MSR_K7_PERFCTR0,
 399         .event_map              = amd_pmu_event_map,
 400         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
 401         .num_counters           = 4,
 402         .cntval_bits            = 48,
 403         .cntval_mask            = (1ULL << 48) - 1,
 404         .apic                   = 1,
 405         /* use highest bit to detect overflow */
 406         .max_period             = (1ULL << 47) - 1,
 407         .get_event_constraints  = amd_get_event_constraints,
 408         .put_event_constraints  = amd_put_event_constraints,
 409
 410         .cpu_prepare            = amd_pmu_cpu_prepare,
 411         .cpu_starting           = amd_pmu_cpu_starting,
 412         .cpu_dead               = amd_pmu_cpu_dead,
 413 };
 414
 415 /* AMD Family 15h */
 416
 417 #define AMD_EVENT_TYPE_MASK     0x000000F0ULL
 418
 419 #define AMD_EVENT_FP            0x00000000ULL ... 0x00000010ULL
 420 #define AMD_EVENT_LS            0x00000020ULL ... 0x00000030ULL
 421 #define AMD_EVENT_DC            0x00000040ULL ... 0x00000050ULL
 422 #define AMD_EVENT_CU            0x00000060ULL ... 0x00000070ULL
 423 #define AMD_EVENT_IC_DE         0x00000080ULL ... 0x00000090ULL
 424 #define AMD_EVENT_EX_LS         0x000000C0ULL
 425 #define AMD_EVENT_DE            0x000000D0ULL
 426 #define AMD_EVENT_NB            0x000000E0ULL ... 0x000000F0ULL
 427
 428 /*
 429  * AMD family 15h event code/PMC mappings:
 430  *
 431  * type = event_code & 0x0F0:
 432  *
 433  * 0x000        FP      PERF_CTL[5:3]
 434  * 0x010        FP      PERF_CTL[5:3]
 435  * 0x020        LS      PERF_CTL[5:0]
 436  * 0x030        LS      PERF_CTL[5:0]
 437  * 0x040        DC      PERF_CTL[5:0]
 438  * 0x050        DC      PERF_CTL[5:0]
 439  * 0x060        CU      PERF_CTL[2:0]
 440  * 0x070        CU      PERF_CTL[2:0]
 441  * 0x080        IC/DE   PERF_CTL[2:0]
 442  * 0x090        IC/DE   PERF_CTL[2:0]
 443  * 0x0A0        ---
 444  * 0x0B0        ---
 445  * 0x0C0        EX/LS   PERF_CTL[5:0]
 446  * 0x0D0        DE      PERF_CTL[2:0]
 447  * 0x0E0        NB      NB_PERF_CTL[3:0]
 448  * 0x0F0        NB      NB_PERF_CTL[3:0]
 449  *
 450  * Exceptions:
 451  *
 452  * 0x000        FP      PERF_CTL[3], PERF_CTL[5:3] (*)
 453  * 0x003        FP      PERF_CTL[3]
 454  * 0x004        FP      PERF_CTL[3], PERF_CTL[5:3] (*)
 455  * 0x00B        FP      PERF_CTL[3]
 456  * 0x00D        FP      PERF_CTL[3]
 457  * 0x023        DE      PERF_CTL[2:0]
 458  * 0x02D        LS      PERF_CTL[3]
 459  * 0x02E        LS      PERF_CTL[3,0]
 460  * 0x043        CU      PERF_CTL[2:0]
 461  * 0x045        CU      PERF_CTL[2:0]
 462  * 0x046        CU      PERF_CTL[2:0]
 463  * 0x054        CU      PERF_CTL[2:0]
 464  * 0x055        CU      PERF_CTL[2:0]
 465  * 0x08F        IC      PERF_CTL[0]
 466  * 0x187        DE      PERF_CTL[0]
 467  * 0x188        DE      PERF_CTL[0]
 468  * 0x0DB        EX      PERF_CTL[5:0]
 469  * 0x0DC        LS      PERF_CTL[5:0]
 470  * 0x0DD        LS      PERF_CTL[5:0]
 471  * 0x0DE        LS      PERF_CTL[5:0]
 472  * 0x0DF        LS      PERF_CTL[5:0]
 473  * 0x1D6        EX      PERF_CTL[5:0]
 474  * 0x1D8        EX      PERF_CTL[5:0]
 475  *
 476  * (*) depending on the umask all FPU counters may be used
 477  */
 478
 479 static struct event_constraint amd_f15_PMC0  = EVENT_CONSTRAINT(0, 0x01, 0);
 480 static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0);
 481 static struct event_constraint amd_f15_PMC3  = EVENT_CONSTRAINT(0, 0x08, 0);
 482 static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT(0, 0x09, 0);
 483 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
 484 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
 485
 486 static struct event_constraint *
 487 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
 488 {
 489         struct hw_perf_event *hwc = &event->hw;
 490         unsigned int event_code = amd_get_event_code(hwc);
 491
 492         switch (event_code & AMD_EVENT_TYPE_MASK) {
 493         case AMD_EVENT_FP:
 494                 switch (event_code) {
 495                 case 0x000:
 496                         if (!(hwc->config & 0x0000F000ULL))
 497                                 break;
 498                         if (!(hwc->config & 0x00000F00ULL))
 499                                 break;
 500                         return &amd_f15_PMC3;
 501                 case 0x004:
 502                         if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
 503                                 break;
 504                         return &amd_f15_PMC3;
 505                 case 0x003:
 506                 case 0x00B:
 507                 case 0x00D:
 508                         return &amd_f15_PMC3;
 509                 }
 510                 return &amd_f15_PMC53;
 511         case AMD_EVENT_LS:
 512         case AMD_EVENT_DC:
 513         case AMD_EVENT_EX_LS:
 514                 switch (event_code) {
 515                 case 0x023:
 516                 case 0x043:
 517                 case 0x045:
 518                 case 0x046:
 519                 case 0x054:
 520                 case 0x055:
 521                         return &amd_f15_PMC20;
 522                 case 0x02D:
 523                         return &amd_f15_PMC3;
 524                 case 0x02E:
 525                         return &amd_f15_PMC30;
 526                 default:
 527                         return &amd_f15_PMC50;
 528                 }
 529         case AMD_EVENT_CU:
 530         case AMD_EVENT_IC_DE:
 531         case AMD_EVENT_DE:
 532                 switch (event_code) {
 533                 case 0x08F:
 534                 case 0x187:
 535                 case 0x188:
 536                         return &amd_f15_PMC0;
 537                 case 0x0DB ... 0x0DF:
 538                 case 0x1D6:
 539                 case 0x1D8:
 540                         return &amd_f15_PMC50;
 541                 default:
 542                         return &amd_f15_PMC20;
 543                 }
 544         case AMD_EVENT_NB:
 545                 /* not yet implemented */
 546                 return &emptyconstraint;
 547         default:
 548                 return &emptyconstraint;
 549         }
 550 }
 551
 552 static __initconst const struct x86_pmu amd_pmu_f15h = {
 553         .name                   = "AMD Family 15h",
 554         .handle_irq             = x86_pmu_handle_irq,
 555         .disable_all            = x86_pmu_disable_all,
 556         .enable_all             = x86_pmu_enable_all,
 557         .enable                 = x86_pmu_enable_event,
 558         .disable                = x86_pmu_disable_event,
 559         .hw_config              = amd_pmu_hw_config,
 560         .schedule_events        = x86_schedule_events,
 561         .eventsel               = MSR_F15H_PERF_CTL,
 562         .perfctr                = MSR_F15H_PERF_CTR,
 563         .event_map              = amd_pmu_event_map,
 564         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
 565         .num_counters           = 6,
 566         .cntval_bits            = 48,
 567         .cntval_mask            = (1ULL << 48) - 1,
 568         .apic                   = 1,
 569         /* use highest bit to detect overflow */
 570         .max_period             = (1ULL << 47) - 1,
 571         .get_event_constraints  = amd_get_event_constraints_f15h,
 572         /* nortbridge counters not yet implemented: */
 573 #if 0
 574         .put_event_constraints  = amd_put_event_constraints,
 575
 576         .cpu_prepare            = amd_pmu_cpu_prepare,
 577         .cpu_starting           = amd_pmu_cpu_starting,
 578         .cpu_dead               = amd_pmu_cpu_dead,
 579 #endif
 580 };
 581
 582 __init int amd_pmu_init(void)
 583 {
 584         /* Performance-monitoring supported from K7 and later: */
 585         if (boot_cpu_data.x86 < 6)
 586                 return -ENODEV;
 587
 588         /*
 589          * If core performance counter extensions exists, it must be
 590          * family 15h, otherwise fail. See x86_pmu_addr_offset().
 591          */
 592         switch (boot_cpu_data.x86) {
 593         case 0x15:
 594                 if (!cpu_has_perfctr_core)
 595                         return -ENODEV;
 596                 x86_pmu = amd_pmu_f15h;
 597                 break;
 598         default:
 599                 if (cpu_has_perfctr_core)
 600                         return -ENODEV;
 601                 x86_pmu = amd_pmu;
 602                 break;
 603         }
 604
 605         /* Events are common for all AMDs */
 606         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
 607                sizeof(hw_cache_event_ids));
 608
 609         return 0;
 610 }