2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
40 #include <linux/irq_work.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
94 static DEFINE_PER_CPU(struct mce, mces_seen);
95 static int cpu_missing;
98 * CPU/chipset specific EDAC code can register a notifier call here to print
99 * MCE errors in a human-readable form.
101 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
102 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
104 /* MCA banks polled by the period polling timer for corrected events */
105 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
106 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
109 static DEFINE_PER_CPU(struct work_struct, mce_work);
111 /* Do initial initialization of a struct mce */
112 void mce_setup(struct mce *m)
114 memset(m, 0, sizeof(struct mce));
115 m->cpu = m->extcpu = smp_processor_id();
117 /* We hope get_seconds stays lockless */
118 m->time = get_seconds();
119 m->cpuvendor = boot_cpu_data.x86_vendor;
120 m->cpuid = cpuid_eax(1);
122 m->socketid = cpu_data(m->extcpu).phys_proc_id;
124 m->apicid = cpu_data(m->extcpu).initial_apicid;
125 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
128 DEFINE_PER_CPU(struct mce, injectm);
129 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
132 * Lockless MCE logging infrastructure.
133 * This avoids deadlocks on printk locks without having to break locks. Also
134 * separate MCEs from kernel messages to avoid bogus bug reports.
137 static struct mce_log mcelog = {
138 .signature = MCE_LOG_SIGNATURE,
140 .recordlen = sizeof(struct mce),
143 void mce_log(struct mce *mce)
145 unsigned next, entry;
147 /* Emit the trace record: */
148 trace_mce_record(mce);
153 entry = rcu_dereference_check_mce(mcelog.next);
156 * If edac_mce is enabled, it will check the error type
157 * and will process it, if it is a known error.
158 * Otherwise, the error will be sent through mcelog
161 if (edac_mce_parse(mce))
165 * When the buffer fills up discard new entries.
166 * Assume that the earlier errors are the more
169 if (entry >= MCE_LOG_LEN) {
170 set_bit(MCE_OVERFLOW,
171 (unsigned long *)&mcelog.flags);
174 /* Old left over entry. Skip: */
175 if (mcelog.entry[entry].finished) {
183 if (cmpxchg(&mcelog.next, entry, next) == entry)
186 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
188 mcelog.entry[entry].finished = 1;
192 set_bit(0, &mce_need_notify);
195 static void print_mce(struct mce *m)
199 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
200 m->extcpu, m->mcgstatus, m->bank, m->status);
203 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
204 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
207 if (m->cs == __KERNEL_CS)
208 print_symbol("{%s}", m->ip);
212 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
214 pr_cont("ADDR %llx ", m->addr);
216 pr_cont("MISC %llx ", m->misc);
219 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
220 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
223 * Print out human-readable details about the MCE error,
224 * (if the CPU has an implementation for that)
226 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
227 if (ret == NOTIFY_STOP)
230 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
233 #define PANIC_TIMEOUT 5 /* 5 seconds */
235 static atomic_t mce_paniced;
237 static int fake_panic;
238 static atomic_t mce_fake_paniced;
240 /* Panic in progress. Enable interrupts and wait for final IPI */
241 static void wait_for_panic(void)
243 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
247 while (timeout-- > 0)
249 if (panic_timeout == 0)
250 panic_timeout = mce_panic_timeout;
251 panic("Panicing machine check CPU died");
254 static void mce_panic(char *msg, struct mce *final, char *exp)
260 * Make sure only one CPU runs in machine check panic
262 if (atomic_inc_return(&mce_paniced) > 1)
269 /* Don't log too much for fake panic */
270 if (atomic_inc_return(&mce_fake_paniced) > 1)
273 /* First print corrected ones that are still unlogged */
274 for (i = 0; i < MCE_LOG_LEN; i++) {
275 struct mce *m = &mcelog.entry[i];
276 if (!(m->status & MCI_STATUS_VAL))
278 if (!(m->status & MCI_STATUS_UC)) {
281 apei_err = apei_write_mce(m);
284 /* Now print uncorrected but with the final one last */
285 for (i = 0; i < MCE_LOG_LEN; i++) {
286 struct mce *m = &mcelog.entry[i];
287 if (!(m->status & MCI_STATUS_VAL))
289 if (!(m->status & MCI_STATUS_UC))
291 if (!final || memcmp(m, final, sizeof(struct mce))) {
294 apei_err = apei_write_mce(m);
300 apei_err = apei_write_mce(final);
303 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
305 pr_emerg(HW_ERR "Machine check: %s\n", exp);
307 if (panic_timeout == 0)
308 panic_timeout = mce_panic_timeout;
311 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
314 /* Support code for software error injection */
316 static int msr_to_offset(u32 msr)
318 unsigned bank = __this_cpu_read(injectm.bank);
321 return offsetof(struct mce, ip);
322 if (msr == MSR_IA32_MCx_STATUS(bank))
323 return offsetof(struct mce, status);
324 if (msr == MSR_IA32_MCx_ADDR(bank))
325 return offsetof(struct mce, addr);
326 if (msr == MSR_IA32_MCx_MISC(bank))
327 return offsetof(struct mce, misc);
328 if (msr == MSR_IA32_MCG_STATUS)
329 return offsetof(struct mce, mcgstatus);
333 /* MSR access wrappers used for error injection */
334 static u64 mce_rdmsrl(u32 msr)
338 if (__this_cpu_read(injectm.finished)) {
339 int offset = msr_to_offset(msr);
343 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
346 if (rdmsrl_safe(msr, &v)) {
347 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
349 * Return zero in case the access faulted. This should
350 * not happen normally but can happen if the CPU does
351 * something weird, or if the code is buggy.
359 static void mce_wrmsrl(u32 msr, u64 v)
361 if (__this_cpu_read(injectm.finished)) {
362 int offset = msr_to_offset(msr);
365 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
372 * Collect all global (w.r.t. this processor) status about this machine
373 * check into our "mce" struct so that we can use it later to assess
374 * the severity of the problem as we read per-bank specific details.
376 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
380 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
383 * Get the address of the instruction at the time of
384 * the machine check error.
386 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
390 /* Use accurate RIP reporting if available. */
392 m->ip = mce_rdmsrl(rip_msr);
397 * Simple lockless ring to communicate PFNs from the exception handler with the
398 * process context work function. This is vastly simplified because there's
399 * only a single reader and a single writer.
401 #define MCE_RING_SIZE 16 /* we use one entry less */
404 unsigned short start;
406 unsigned long ring[MCE_RING_SIZE];
408 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
410 /* Runs with CPU affinity in workqueue */
411 static int mce_ring_empty(void)
413 struct mce_ring *r = &__get_cpu_var(mce_ring);
415 return r->start == r->end;
418 static int mce_ring_get(unsigned long *pfn)
425 r = &__get_cpu_var(mce_ring);
426 if (r->start == r->end)
428 *pfn = r->ring[r->start];
429 r->start = (r->start + 1) % MCE_RING_SIZE;
436 /* Always runs in MCE context with preempt off */
437 static int mce_ring_add(unsigned long pfn)
439 struct mce_ring *r = &__get_cpu_var(mce_ring);
442 next = (r->end + 1) % MCE_RING_SIZE;
443 if (next == r->start)
445 r->ring[r->end] = pfn;
451 int mce_available(struct cpuinfo_x86 *c)
455 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
458 static void mce_schedule_work(void)
460 if (!mce_ring_empty()) {
461 struct work_struct *work = &__get_cpu_var(mce_work);
462 if (!work_pending(work))
467 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
469 static void mce_irq_work_cb(struct irq_work *entry)
475 static void mce_report_event(struct pt_regs *regs)
477 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
480 * Triggering the work queue here is just an insurance
481 * policy in case the syscall exit notify handler
482 * doesn't run soon enough or ends up running on the
483 * wrong CPU (can happen when audit sleeps)
489 irq_work_queue(&__get_cpu_var(mce_irq_work));
492 DEFINE_PER_CPU(unsigned, mce_poll_count);
495 * Poll for corrected events or events that happened before reset.
496 * Those are just logged through /dev/mcelog.
498 * This is executed in standard interrupt context.
500 * Note: spec recommends to panic for fatal unsignalled
501 * errors here. However this would be quite problematic --
502 * we would need to reimplement the Monarch handling and
503 * it would mess up the exclusion between exception handler
504 * and poll hander -- * so we skip this for now.
505 * These cases should not happen anyways, or only when the CPU
506 * is already totally * confused. In this case it's likely it will
507 * not fully execute the machine check handler either.
509 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
514 percpu_inc(mce_poll_count);
516 mce_gather_info(&m, NULL);
518 for (i = 0; i < banks; i++) {
519 if (!mce_banks[i].ctl || !test_bit(i, *b))
528 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
529 if (!(m.status & MCI_STATUS_VAL))
533 * Uncorrected or signalled events are handled by the exception
534 * handler when it is enabled, so don't process those here.
536 * TBD do the same check for MCI_STATUS_EN here?
538 if (!(flags & MCP_UC) &&
539 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
542 if (m.status & MCI_STATUS_MISCV)
543 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
544 if (m.status & MCI_STATUS_ADDRV)
545 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
547 if (!(flags & MCP_TIMESTAMP))
550 * Don't get the IP here because it's unlikely to
551 * have anything to do with the actual error location.
553 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
555 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
559 * Clear state for this bank.
561 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
565 * Don't clear MCG_STATUS here because it's only defined for
571 EXPORT_SYMBOL_GPL(machine_check_poll);
574 * Do a quick check if any of the events requires a panic.
575 * This decides if we keep the events around or clear them.
577 static int mce_no_way_out(struct mce *m, char **msg)
581 for (i = 0; i < banks; i++) {
582 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
583 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
590 * Variable to establish order between CPUs while scanning.
591 * Each CPU spins initially until executing is equal its number.
593 static atomic_t mce_executing;
596 * Defines order of CPUs on entry. First CPU becomes Monarch.
598 static atomic_t mce_callin;
601 * Check if a timeout waiting for other CPUs happened.
603 static int mce_timed_out(u64 *t)
606 * The others already did panic for some reason.
607 * Bail out like in a timeout.
608 * rmb() to tell the compiler that system_state
609 * might have been modified by someone else.
612 if (atomic_read(&mce_paniced))
614 if (!monarch_timeout)
616 if ((s64)*t < SPINUNIT) {
617 /* CHECKME: Make panic default for 1 too? */
619 mce_panic("Timeout synchronizing machine check over CPUs",
626 touch_nmi_watchdog();
631 * The Monarch's reign. The Monarch is the CPU who entered
632 * the machine check handler first. It waits for the others to
633 * raise the exception too and then grades them. When any
634 * error is fatal panic. Only then let the others continue.
636 * The other CPUs entering the MCE handler will be controlled by the
637 * Monarch. They are called Subjects.
639 * This way we prevent any potential data corruption in a unrecoverable case
640 * and also makes sure always all CPU's errors are examined.
642 * Also this detects the case of a machine check event coming from outer
643 * space (not detected by any CPUs) In this case some external agent wants
644 * us to shut down, so panic too.
646 * The other CPUs might still decide to panic if the handler happens
647 * in a unrecoverable place, but in this case the system is in a semi-stable
648 * state and won't corrupt anything by itself. It's ok to let the others
649 * continue for a bit first.
651 * All the spin loops have timeouts; when a timeout happens a CPU
652 * typically elects itself to be Monarch.
654 static void mce_reign(void)
657 struct mce *m = NULL;
658 int global_worst = 0;
663 * This CPU is the Monarch and the other CPUs have run
664 * through their handlers.
665 * Grade the severity of the errors of all the CPUs.
667 for_each_possible_cpu(cpu) {
668 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
670 if (severity > global_worst) {
672 global_worst = severity;
673 m = &per_cpu(mces_seen, cpu);
678 * Cannot recover? Panic here then.
679 * This dumps all the mces in the log buffer and stops the
682 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
683 mce_panic("Fatal Machine check", m, msg);
686 * For UC somewhere we let the CPU who detects it handle it.
687 * Also must let continue the others, otherwise the handling
688 * CPU could deadlock on a lock.
692 * No machine check event found. Must be some external
693 * source or one CPU is hung. Panic.
695 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
696 mce_panic("Machine check from unknown source", NULL, NULL);
699 * Now clear all the mces_seen so that they don't reappear on
702 for_each_possible_cpu(cpu)
703 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
706 static atomic_t global_nwo;
709 * Start of Monarch synchronization. This waits until all CPUs have
710 * entered the exception handler and then determines if any of them
711 * saw a fatal event that requires panic. Then it executes them
712 * in the entry order.
713 * TBD double check parallel CPU hotunplug
715 static int mce_start(int *no_way_out)
718 int cpus = num_online_cpus();
719 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
724 atomic_add(*no_way_out, &global_nwo);
726 * global_nwo should be updated before mce_callin
729 order = atomic_inc_return(&mce_callin);
734 while (atomic_read(&mce_callin) != cpus) {
735 if (mce_timed_out(&timeout)) {
736 atomic_set(&global_nwo, 0);
743 * mce_callin should be read before global_nwo
749 * Monarch: Starts executing now, the others wait.
751 atomic_set(&mce_executing, 1);
754 * Subject: Now start the scanning loop one by one in
755 * the original callin order.
756 * This way when there are any shared banks it will be
757 * only seen by one CPU before cleared, avoiding duplicates.
759 while (atomic_read(&mce_executing) < order) {
760 if (mce_timed_out(&timeout)) {
761 atomic_set(&global_nwo, 0);
769 * Cache the global no_way_out state.
771 *no_way_out = atomic_read(&global_nwo);
777 * Synchronize between CPUs after main scanning loop.
778 * This invokes the bulk of the Monarch processing.
780 static int mce_end(int order)
783 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
791 * Allow others to run.
793 atomic_inc(&mce_executing);
796 /* CHECKME: Can this race with a parallel hotplug? */
797 int cpus = num_online_cpus();
800 * Monarch: Wait for everyone to go through their scanning
803 while (atomic_read(&mce_executing) <= cpus) {
804 if (mce_timed_out(&timeout))
814 * Subject: Wait for Monarch to finish.
816 while (atomic_read(&mce_executing) != 0) {
817 if (mce_timed_out(&timeout))
823 * Don't reset anything. That's done by the Monarch.
829 * Reset all global state.
832 atomic_set(&global_nwo, 0);
833 atomic_set(&mce_callin, 0);
837 * Let others run again.
839 atomic_set(&mce_executing, 0);
844 * Check if the address reported by the CPU is in a format we can parse.
845 * It would be possible to add code for most other cases, but all would
846 * be somewhat complicated (e.g. segment offset would require an instruction
847 * parser). So only support physical addresses up to page granuality for now.
849 static int mce_usable_address(struct mce *m)
851 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
853 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
855 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
860 static void mce_clear_state(unsigned long *toclear)
864 for (i = 0; i < banks; i++) {
865 if (test_bit(i, toclear))
866 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
871 * The actual machine check handler. This only handles real
872 * exceptions when something got corrupted coming in through int 18.
874 * This is executed in NMI context not subject to normal locking rules. This
875 * implies that most kernel services cannot be safely used. Don't even
876 * think about putting a printk in there!
878 * On Intel systems this is entered on all CPUs in parallel through
879 * MCE broadcast. However some CPUs might be broken beyond repair,
880 * so be always careful when synchronizing with others.
882 void do_machine_check(struct pt_regs *regs, long error_code)
884 struct mce m, *final;
889 * Establish sequential order between the CPUs entering the machine
894 * If no_way_out gets set, there is no safe way to recover from this
895 * MCE. If tolerant is cranked up, we'll try anyway.
899 * If kill_it gets set, there might be a way to recover from this
903 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
904 char *msg = "Unknown";
906 atomic_inc(&mce_entry);
908 percpu_inc(mce_exception_count);
910 if (notify_die(DIE_NMI, "machine check", regs, error_code,
911 18, SIGKILL) == NOTIFY_STOP)
916 mce_gather_info(&m, regs);
918 final = &__get_cpu_var(mces_seen);
921 no_way_out = mce_no_way_out(&m, &msg);
926 * When no restart IP must always kill or panic.
928 if (!(m.mcgstatus & MCG_STATUS_RIPV))
932 * Go through all the banks in exclusion of the other CPUs.
933 * This way we don't report duplicated events on shared banks
934 * because the first one to see it will clear it.
936 order = mce_start(&no_way_out);
937 for (i = 0; i < banks; i++) {
938 __clear_bit(i, toclear);
939 if (!mce_banks[i].ctl)
946 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
947 if ((m.status & MCI_STATUS_VAL) == 0)
951 * Non uncorrected or non signaled errors are handled by
952 * machine_check_poll. Leave them alone, unless this panics.
954 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
959 * Set taint even when machine check was not enabled.
961 add_taint(TAINT_MACHINE_CHECK);
963 severity = mce_severity(&m, tolerant, NULL);
966 * When machine check was for corrected handler don't touch,
967 * unless we're panicing.
969 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
971 __set_bit(i, toclear);
972 if (severity == MCE_NO_SEVERITY) {
974 * Machine check event was not enabled. Clear, but
981 * Kill on action required.
983 if (severity == MCE_AR_SEVERITY)
986 if (m.status & MCI_STATUS_MISCV)
987 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
988 if (m.status & MCI_STATUS_ADDRV)
989 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
992 * Action optional error. Queue address for later processing.
993 * When the ring overflows we just ignore the AO error.
994 * RED-PEN add some logging mechanism when
995 * usable_address or mce_add_ring fails.
996 * RED-PEN don't ignore overflow for tolerant == 0
998 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
999 mce_ring_add(m.addr >> PAGE_SHIFT);
1003 if (severity > worst) {
1010 mce_clear_state(toclear);
1013 * Do most of the synchronization with other CPUs.
1014 * When there's any problem use only local no_way_out state.
1016 if (mce_end(order) < 0)
1017 no_way_out = worst >= MCE_PANIC_SEVERITY;
1020 * If we have decided that we just CAN'T continue, and the user
1021 * has not set tolerant to an insane level, give up and die.
1023 * This is mainly used in the case when the system doesn't
1024 * support MCE broadcasting or it has been disabled.
1026 if (no_way_out && tolerant < 3)
1027 mce_panic("Fatal machine check on current CPU", final, msg);
1030 * If the error seems to be unrecoverable, something should be
1031 * done. Try to kill as little as possible. If we can kill just
1032 * one task, do that. If the user has set the tolerance very
1033 * high, don't try to do anything at all.
1036 if (kill_it && tolerant < 3)
1037 force_sig(SIGBUS, current);
1039 /* notify userspace ASAP */
1040 set_thread_flag(TIF_MCE_NOTIFY);
1043 mce_report_event(regs);
1044 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1046 atomic_dec(&mce_entry);
1049 EXPORT_SYMBOL_GPL(do_machine_check);
1051 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1052 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1054 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1058 * Called after mce notification in process context. This code
1059 * is allowed to sleep. Call the high level VM handler to process
1060 * any corrupted pages.
1061 * Assume that the work queue code only calls this one at a time
1063 * Note we don't disable preemption, so this code might run on the wrong
1064 * CPU. In this case the event is picked up by the scheduled work queue.
1065 * This is merely a fast path to expedite processing in some common
1068 void mce_notify_process(void)
1072 while (mce_ring_get(&pfn))
1073 memory_failure(pfn, MCE_VECTOR);
1076 static void mce_process_work(struct work_struct *dummy)
1078 mce_notify_process();
1081 #ifdef CONFIG_X86_MCE_INTEL
1083 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1084 * @cpu: The CPU on which the event occurred.
1085 * @status: Event status information
1087 * This function should be called by the thermal interrupt after the
1088 * event has been processed and the decision was made to log the event
1091 * The status parameter will be saved to the 'status' field of 'struct mce'
1092 * and historically has been the register value of the
1093 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1095 void mce_log_therm_throt_event(__u64 status)
1100 m.bank = MCE_THERMAL_BANK;
1104 #endif /* CONFIG_X86_MCE_INTEL */
1107 * Periodic polling timer for "silent" machine check errors. If the
1108 * poller finds an MCE, poll 2x faster. When the poller finds no more
1109 * errors, poll 2x slower (up to check_interval seconds).
1111 static int check_interval = 5 * 60; /* 5 minutes */
1113 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1114 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1116 static void mce_start_timer(unsigned long data)
1118 struct timer_list *t = &per_cpu(mce_timer, data);
1121 WARN_ON(smp_processor_id() != data);
1123 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1124 machine_check_poll(MCP_TIMESTAMP,
1125 &__get_cpu_var(mce_poll_banks));
1129 * Alert userspace if needed. If we logged an MCE, reduce the
1130 * polling interval, otherwise increase the polling interval.
1132 n = &__get_cpu_var(mce_next_interval);
1133 if (mce_notify_irq())
1134 *n = max(*n/2, HZ/100);
1136 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1138 t->expires = jiffies + *n;
1139 add_timer_on(t, smp_processor_id());
1142 static void mce_do_trigger(struct work_struct *work)
1144 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1147 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1150 * Notify the user(s) about new machine check events.
1151 * Can be called from interrupt context, but not from machine check/NMI
1154 int mce_notify_irq(void)
1156 /* Not more than two messages every minute */
1157 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1159 clear_thread_flag(TIF_MCE_NOTIFY);
1161 if (test_and_clear_bit(0, &mce_need_notify)) {
1162 wake_up_interruptible(&mce_wait);
1165 * There is no risk of missing notifications because
1166 * work_pending is always cleared before the function is
1169 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1170 schedule_work(&mce_trigger_work);
1172 if (__ratelimit(&ratelimit))
1173 pr_info(HW_ERR "Machine check events logged\n");
1179 EXPORT_SYMBOL_GPL(mce_notify_irq);
1181 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1185 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1188 for (i = 0; i < banks; i++) {
1189 struct mce_bank *b = &mce_banks[i];
1198 * Initialize Machine Checks for a CPU.
1200 static int __cpuinit __mcheck_cpu_cap_init(void)
1205 rdmsrl(MSR_IA32_MCG_CAP, cap);
1207 b = cap & MCG_BANKCNT_MASK;
1209 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1211 if (b > MAX_NR_BANKS) {
1213 "MCE: Using only %u machine check banks out of %u\n",
1218 /* Don't support asymmetric configurations today */
1219 WARN_ON(banks != 0 && b != banks);
1222 int err = __mcheck_cpu_mce_banks_init();
1228 /* Use accurate RIP reporting if available. */
1229 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1230 rip_msr = MSR_IA32_MCG_EIP;
1232 if (cap & MCG_SER_P)
1238 static void __mcheck_cpu_init_generic(void)
1240 mce_banks_t all_banks;
1245 * Log the machine checks left over from the previous reset.
1247 bitmap_fill(all_banks, MAX_NR_BANKS);
1248 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1250 set_in_cr4(X86_CR4_MCE);
1252 rdmsrl(MSR_IA32_MCG_CAP, cap);
1253 if (cap & MCG_CTL_P)
1254 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1256 for (i = 0; i < banks; i++) {
1257 struct mce_bank *b = &mce_banks[i];
1261 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1262 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1266 /* Add per CPU specific workarounds here */
1267 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1269 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1270 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1274 /* This should be disabled by the BIOS, but isn't always */
1275 if (c->x86_vendor == X86_VENDOR_AMD) {
1276 if (c->x86 == 15 && banks > 4) {
1278 * disable GART TBL walk error reporting, which
1279 * trips off incorrectly with the IOMMU & 3ware
1282 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1284 if (c->x86 <= 17 && mce_bootlog < 0) {
1286 * Lots of broken BIOS around that don't clear them
1287 * by default and leave crap in there. Don't log:
1292 * Various K7s with broken bank 0 around. Always disable
1295 if (c->x86 == 6 && banks > 0)
1296 mce_banks[0].ctl = 0;
1299 if (c->x86_vendor == X86_VENDOR_INTEL) {
1301 * SDM documents that on family 6 bank 0 should not be written
1302 * because it aliases to another special BIOS controlled
1304 * But it's not aliased anymore on model 0x1a+
1305 * Don't ignore bank 0 completely because there could be a
1306 * valid event later, merely don't write CTL0.
1309 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1310 mce_banks[0].init = 0;
1313 * All newer Intel systems support MCE broadcasting. Enable
1314 * synchronization with a one second timeout.
1316 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1317 monarch_timeout < 0)
1318 monarch_timeout = USEC_PER_SEC;
1321 * There are also broken BIOSes on some Pentium M and
1324 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1327 if (monarch_timeout < 0)
1328 monarch_timeout = 0;
1329 if (mce_bootlog != 0)
1330 mce_panic_timeout = 30;
1335 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1340 switch (c->x86_vendor) {
1341 case X86_VENDOR_INTEL:
1342 intel_p5_mcheck_init(c);
1345 case X86_VENDOR_CENTAUR:
1346 winchip_mcheck_init(c);
1354 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1356 switch (c->x86_vendor) {
1357 case X86_VENDOR_INTEL:
1358 mce_intel_feature_init(c);
1360 case X86_VENDOR_AMD:
1361 mce_amd_feature_init(c);
1368 static void __mcheck_cpu_init_timer(void)
1370 struct timer_list *t = &__get_cpu_var(mce_timer);
1371 int *n = &__get_cpu_var(mce_next_interval);
1373 setup_timer(t, mce_start_timer, smp_processor_id());
1378 *n = check_interval * HZ;
1381 t->expires = round_jiffies(jiffies + *n);
1382 add_timer_on(t, smp_processor_id());
1385 /* Handle unconfigured int18 (should never happen) */
1386 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1388 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1389 smp_processor_id());
1392 /* Call the installed machine check handler for this CPU setup. */
1393 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1394 unexpected_machine_check;
1397 * Called for each booted CPU to set up machine checks.
1398 * Must be called with preempt off:
1400 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1405 if (__mcheck_cpu_ancient_init(c))
1408 if (!mce_available(c))
1411 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1416 machine_check_vector = do_machine_check;
1418 __mcheck_cpu_init_generic();
1419 __mcheck_cpu_init_vendor(c);
1420 __mcheck_cpu_init_timer();
1421 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1422 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1426 * Character device to read and clear the MCE log.
1429 static DEFINE_SPINLOCK(mce_state_lock);
1430 static int open_count; /* #times opened */
1431 static int open_exclu; /* already open exclusive? */
1433 static int mce_open(struct inode *inode, struct file *file)
1435 spin_lock(&mce_state_lock);
1437 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1438 spin_unlock(&mce_state_lock);
1443 if (file->f_flags & O_EXCL)
1447 spin_unlock(&mce_state_lock);
1449 return nonseekable_open(inode, file);
1452 static int mce_release(struct inode *inode, struct file *file)
1454 spin_lock(&mce_state_lock);
1459 spin_unlock(&mce_state_lock);
1464 static void collect_tscs(void *data)
1466 unsigned long *cpu_tsc = (unsigned long *)data;
1468 rdtscll(cpu_tsc[smp_processor_id()]);
1471 static int mce_apei_read_done;
1473 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1474 static int __mce_read_apei(char __user **ubuf, size_t usize)
1480 if (usize < sizeof(struct mce))
1483 rc = apei_read_mce(&m, &record_id);
1484 /* Error or no more MCE record */
1486 mce_apei_read_done = 1;
1490 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1493 * In fact, we should have cleared the record after that has
1494 * been flushed to the disk or sent to network in
1495 * /sbin/mcelog, but we have no interface to support that now,
1496 * so just clear it to avoid duplication.
1498 rc = apei_clear_mce(record_id);
1500 mce_apei_read_done = 1;
1503 *ubuf += sizeof(struct mce);
1508 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1511 char __user *buf = ubuf;
1512 unsigned long *cpu_tsc;
1513 unsigned prev, next;
1516 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1520 mutex_lock(&mce_read_mutex);
1522 if (!mce_apei_read_done) {
1523 err = __mce_read_apei(&buf, usize);
1524 if (err || buf != ubuf)
1528 next = rcu_dereference_check_mce(mcelog.next);
1530 /* Only supports full reads right now */
1532 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1538 for (i = prev; i < next; i++) {
1539 unsigned long start = jiffies;
1540 struct mce *m = &mcelog.entry[i];
1542 while (!m->finished) {
1543 if (time_after_eq(jiffies, start + 2)) {
1544 memset(m, 0, sizeof(*m));
1550 err |= copy_to_user(buf, m, sizeof(*m));
1556 memset(mcelog.entry + prev, 0,
1557 (next - prev) * sizeof(struct mce));
1559 next = cmpxchg(&mcelog.next, prev, 0);
1560 } while (next != prev);
1562 synchronize_sched();
1565 * Collect entries that were still getting written before the
1568 on_each_cpu(collect_tscs, cpu_tsc, 1);
1570 for (i = next; i < MCE_LOG_LEN; i++) {
1571 struct mce *m = &mcelog.entry[i];
1573 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1574 err |= copy_to_user(buf, m, sizeof(*m));
1577 memset(m, 0, sizeof(*m));
1585 mutex_unlock(&mce_read_mutex);
1588 return err ? err : buf - ubuf;
1591 static unsigned int mce_poll(struct file *file, poll_table *wait)
1593 poll_wait(file, &mce_wait, wait);
1594 if (rcu_access_index(mcelog.next))
1595 return POLLIN | POLLRDNORM;
1596 if (!mce_apei_read_done && apei_check_mce())
1597 return POLLIN | POLLRDNORM;
1601 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1603 int __user *p = (int __user *)arg;
1605 if (!capable(CAP_SYS_ADMIN))
1609 case MCE_GET_RECORD_LEN:
1610 return put_user(sizeof(struct mce), p);
1611 case MCE_GET_LOG_LEN:
1612 return put_user(MCE_LOG_LEN, p);
1613 case MCE_GETCLEAR_FLAGS: {
1617 flags = mcelog.flags;
1618 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1620 return put_user(flags, p);
1627 /* Modified in mce-inject.c, so not static or const */
1628 struct file_operations mce_chrdev_ops = {
1630 .release = mce_release,
1633 .unlocked_ioctl = mce_ioctl,
1634 .llseek = no_llseek,
1636 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1638 static struct miscdevice mce_log_device = {
1645 * mce=off Disables machine check
1646 * mce=no_cmci Disables CMCI
1647 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1648 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1649 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1650 * monarchtimeout is how long to wait for other CPUs on machine
1651 * check, or 0 to not wait
1652 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1653 * mce=nobootlog Don't log MCEs from before booting.
1655 static int __init mcheck_enable(char *str)
1663 if (!strcmp(str, "off"))
1665 else if (!strcmp(str, "no_cmci"))
1666 mce_cmci_disabled = 1;
1667 else if (!strcmp(str, "dont_log_ce"))
1668 mce_dont_log_ce = 1;
1669 else if (!strcmp(str, "ignore_ce"))
1671 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1672 mce_bootlog = (str[0] == 'b');
1673 else if (isdigit(str[0])) {
1674 get_option(&str, &tolerant);
1677 get_option(&str, &monarch_timeout);
1680 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1686 __setup("mce", mcheck_enable);
1688 int __init mcheck_init(void)
1690 mcheck_intel_therm_init();
1700 * Disable machine checks on suspend and shutdown. We can't really handle
1703 static int mce_disable_error_reporting(void)
1707 for (i = 0; i < banks; i++) {
1708 struct mce_bank *b = &mce_banks[i];
1711 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1716 static int mce_suspend(void)
1718 return mce_disable_error_reporting();
1721 static void mce_shutdown(void)
1723 mce_disable_error_reporting();
1727 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1728 * Only one CPU is active at this time, the others get re-added later using
1731 static void mce_resume(void)
1733 __mcheck_cpu_init_generic();
1734 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1737 static struct syscore_ops mce_syscore_ops = {
1738 .suspend = mce_suspend,
1739 .shutdown = mce_shutdown,
1740 .resume = mce_resume,
1743 static void mce_cpu_restart(void *data)
1745 del_timer_sync(&__get_cpu_var(mce_timer));
1746 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1748 __mcheck_cpu_init_generic();
1749 __mcheck_cpu_init_timer();
1752 /* Reinit MCEs after user configuration changes */
1753 static void mce_restart(void)
1755 on_each_cpu(mce_cpu_restart, NULL, 1);
1758 /* Toggle features for corrected errors */
1759 static void mce_disable_ce(void *all)
1761 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1764 del_timer_sync(&__get_cpu_var(mce_timer));
1768 static void mce_enable_ce(void *all)
1770 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1775 __mcheck_cpu_init_timer();
1778 static struct sysdev_class mce_sysclass = {
1779 .name = "machinecheck",
1782 DEFINE_PER_CPU(struct sys_device, mce_dev);
1785 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1787 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1789 return container_of(attr, struct mce_bank, attr);
1792 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1795 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1798 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1799 const char *buf, size_t size)
1803 if (strict_strtoull(buf, 0, &new) < 0)
1806 attr_to_bank(attr)->ctl = new;
1813 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1815 strcpy(buf, mce_helper);
1817 return strlen(mce_helper) + 1;
1820 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1821 const char *buf, size_t siz)
1825 strncpy(mce_helper, buf, sizeof(mce_helper));
1826 mce_helper[sizeof(mce_helper)-1] = 0;
1827 p = strchr(mce_helper, '\n');
1832 return strlen(mce_helper) + !!p;
1835 static ssize_t set_ignore_ce(struct sys_device *s,
1836 struct sysdev_attribute *attr,
1837 const char *buf, size_t size)
1841 if (strict_strtoull(buf, 0, &new) < 0)
1844 if (mce_ignore_ce ^ !!new) {
1846 /* disable ce features */
1847 on_each_cpu(mce_disable_ce, (void *)1, 1);
1850 /* enable ce features */
1852 on_each_cpu(mce_enable_ce, (void *)1, 1);
1858 static ssize_t set_cmci_disabled(struct sys_device *s,
1859 struct sysdev_attribute *attr,
1860 const char *buf, size_t size)
1864 if (strict_strtoull(buf, 0, &new) < 0)
1867 if (mce_cmci_disabled ^ !!new) {
1870 on_each_cpu(mce_disable_ce, NULL, 1);
1871 mce_cmci_disabled = 1;
1874 mce_cmci_disabled = 0;
1875 on_each_cpu(mce_enable_ce, NULL, 1);
1881 static ssize_t store_int_with_restart(struct sys_device *s,
1882 struct sysdev_attribute *attr,
1883 const char *buf, size_t size)
1885 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1890 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1891 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1892 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1893 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1895 static struct sysdev_ext_attribute attr_check_interval = {
1896 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1897 store_int_with_restart),
1901 static struct sysdev_ext_attribute attr_ignore_ce = {
1902 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1906 static struct sysdev_ext_attribute attr_cmci_disabled = {
1907 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1911 static struct sysdev_attribute *mce_attrs[] = {
1912 &attr_tolerant.attr,
1913 &attr_check_interval.attr,
1915 &attr_monarch_timeout.attr,
1916 &attr_dont_log_ce.attr,
1917 &attr_ignore_ce.attr,
1918 &attr_cmci_disabled.attr,
1922 static cpumask_var_t mce_dev_initialized;
1924 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1925 static __cpuinit int mce_create_device(unsigned int cpu)
1927 struct sys_device *sysdev = &per_cpu(mce_dev, cpu);
1931 if (!mce_available(&boot_cpu_data))
1934 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1936 sysdev->cls = &mce_sysclass;
1938 err = sysdev_register(sysdev);
1942 for (i = 0; mce_attrs[i]; i++) {
1943 err = sysdev_create_file(sysdev, mce_attrs[i]);
1947 for (j = 0; j < banks; j++) {
1948 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
1952 cpumask_set_cpu(cpu, mce_dev_initialized);
1957 sysdev_remove_file(sysdev, &mce_banks[j].attr);
1960 sysdev_remove_file(sysdev, mce_attrs[i]);
1962 sysdev_unregister(sysdev);
1967 static __cpuinit void mce_remove_device(unsigned int cpu)
1969 struct sys_device *sysdev = &per_cpu(mce_dev, cpu);
1972 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1975 for (i = 0; mce_attrs[i]; i++)
1976 sysdev_remove_file(sysdev, mce_attrs[i]);
1978 for (i = 0; i < banks; i++)
1979 sysdev_remove_file(sysdev, &mce_banks[i].attr);
1981 sysdev_unregister(sysdev);
1982 cpumask_clear_cpu(cpu, mce_dev_initialized);
1985 /* Make sure there are no machine checks on offlined CPUs. */
1986 static void __cpuinit mce_disable_cpu(void *h)
1988 unsigned long action = *(unsigned long *)h;
1991 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1994 if (!(action & CPU_TASKS_FROZEN))
1996 for (i = 0; i < banks; i++) {
1997 struct mce_bank *b = &mce_banks[i];
2000 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2004 static void __cpuinit mce_reenable_cpu(void *h)
2006 unsigned long action = *(unsigned long *)h;
2009 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2012 if (!(action & CPU_TASKS_FROZEN))
2014 for (i = 0; i < banks; i++) {
2015 struct mce_bank *b = &mce_banks[i];
2018 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2022 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2023 static int __cpuinit
2024 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2026 unsigned int cpu = (unsigned long)hcpu;
2027 struct timer_list *t = &per_cpu(mce_timer, cpu);
2031 case CPU_ONLINE_FROZEN:
2032 mce_create_device(cpu);
2033 if (threshold_cpu_callback)
2034 threshold_cpu_callback(action, cpu);
2037 case CPU_DEAD_FROZEN:
2038 if (threshold_cpu_callback)
2039 threshold_cpu_callback(action, cpu);
2040 mce_remove_device(cpu);
2042 case CPU_DOWN_PREPARE:
2043 case CPU_DOWN_PREPARE_FROZEN:
2045 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2047 case CPU_DOWN_FAILED:
2048 case CPU_DOWN_FAILED_FROZEN:
2049 if (!mce_ignore_ce && check_interval) {
2050 t->expires = round_jiffies(jiffies +
2051 __get_cpu_var(mce_next_interval));
2052 add_timer_on(t, cpu);
2054 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2057 /* intentionally ignoring frozen here */
2058 cmci_rediscover(cpu);
2064 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2065 .notifier_call = mce_cpu_callback,
2068 static __init void mce_init_banks(void)
2072 for (i = 0; i < banks; i++) {
2073 struct mce_bank *b = &mce_banks[i];
2074 struct sysdev_attribute *a = &b->attr;
2076 sysfs_attr_init(&a->attr);
2077 a->attr.name = b->attrname;
2078 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2080 a->attr.mode = 0644;
2081 a->show = show_bank;
2082 a->store = set_bank;
2086 static __init int mcheck_init_device(void)
2091 if (!mce_available(&boot_cpu_data))
2094 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2098 err = sysdev_class_register(&mce_sysclass);
2102 for_each_online_cpu(i) {
2103 err = mce_create_device(i);
2108 register_syscore_ops(&mce_syscore_ops);
2109 register_hotcpu_notifier(&mce_cpu_notifier);
2110 misc_register(&mce_log_device);
2115 device_initcall(mcheck_init_device);
2118 * Old style boot options parsing. Only for compatibility.
2120 static int __init mcheck_disable(char *str)
2125 __setup("nomce", mcheck_disable);
2127 #ifdef CONFIG_DEBUG_FS
2128 struct dentry *mce_get_debugfs_dir(void)
2130 static struct dentry *dmce;
2133 dmce = debugfs_create_dir("mce", NULL);
2138 static void mce_reset(void)
2141 atomic_set(&mce_fake_paniced, 0);
2142 atomic_set(&mce_executing, 0);
2143 atomic_set(&mce_callin, 0);
2144 atomic_set(&global_nwo, 0);
2147 static int fake_panic_get(void *data, u64 *val)
2153 static int fake_panic_set(void *data, u64 val)
2160 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2161 fake_panic_set, "%llu\n");
2163 static int __init mcheck_debugfs_init(void)
2165 struct dentry *dmce, *ffake_panic;
2167 dmce = mce_get_debugfs_dir();
2170 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2177 late_initcall(mcheck_debugfs_init);