1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/sections.h>
22 #include <linux/topology.h>
23 #include <linux/cpumask.h>
24 #include <asm/pgtable.h>
25 #include <linux/atomic.h>
26 #include <asm/proto.h>
27 #include <asm/setup.h>
32 #include <linux/numa.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/uv/uv.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_initialized_mask;
47 cpumask_var_t cpu_callout_mask;
48 cpumask_var_t cpu_callin_mask;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask;
53 /* correctly size the local cpu masks */
54 void __init setup_cpu_local_masks(void)
56 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
57 alloc_bootmem_cpumask_var(&cpu_callin_mask);
58 alloc_bootmem_cpumask_var(&cpu_callout_mask);
59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
62 static void __cpuinit default_init(struct cpuinfo_x86 *c)
65 cpu_detect_cache_sizes(c);
67 /* Not much we can do here... */
68 /* Check if at least it has cpuid */
69 if (c->cpuid_level == -1) {
70 /* No cpuid. It must be an ancient CPU */
72 strcpy(c->x86_model_id, "486");
74 strcpy(c->x86_model_id, "386");
79 static const struct cpu_dev __cpuinitconst default_cpu = {
80 .c_init = default_init,
81 .c_vendor = "Unknown",
82 .c_x86_vendor = X86_VENDOR_UNKNOWN,
85 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
87 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(struct gdt_page, gdt_page) = { .gdt = {
90 * We need valid kernel segments for data and code in long mode too
91 * IRET will check the segment types kkeil 2000/10/28
92 * Also sysret mandates a special GDT layout
94 * TLS descriptors are currently at a different place compared to i386.
95 * Hopefully nobody expects them at a fixed place (Wine?)
97 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
99 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
102 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
109 * Segments used for calling PnP BIOS have byte granularity.
110 * They code segments and data segments have fixed 64k limits,
111 * the transfer segment sizes are set at run time.
114 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
116 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
118 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
120 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
122 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
124 * The APM segments have byte granularity and their bases
125 * are set at run time. All have 64k limits.
128 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
130 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
132 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
134 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
136 GDT_STACK_CANARY_INIT
139 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
141 static int __init x86_xsave_setup(char *s)
145 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
146 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149 __setup("noxsave", x86_xsave_setup);
151 static int __init x86_xsaveopt_setup(char *s)
153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
156 __setup("noxsaveopt", x86_xsaveopt_setup);
159 static int __init x86_pcid_setup(char *s)
161 /* require an exact match without trailing characters */
165 /* do not emit a message if the feature is not present */
166 if (!boot_cpu_has(X86_FEATURE_PCID))
169 setup_clear_cpu_cap(X86_FEATURE_PCID);
170 pr_info("nopcid: PCID feature disabled\n");
173 __setup("nopcid", x86_pcid_setup);
175 static int __init x86_nokaiser_setup(char *s)
177 /* nokaiser doesn't accept parameters */
182 setup_clear_cpu_cap(X86_FEATURE_KAISER);
183 pr_info("nokaiser: KAISER feature disabled\n");
187 early_param("nokaiser", x86_nokaiser_setup);
190 static int __init x86_noinvpcid_setup(char *s)
192 /* noinvpcid doesn't accept parameters */
196 /* do not emit a message if the feature is not present */
197 if (!boot_cpu_has(X86_FEATURE_INVPCID))
200 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
201 pr_info("noinvpcid: INVPCID feature disabled\n");
204 early_param("noinvpcid", x86_noinvpcid_setup);
207 static int cachesize_override __cpuinitdata = -1;
208 static int disable_x86_serial_nr __cpuinitdata = 1;
210 static int __init cachesize_setup(char *str)
212 get_option(&str, &cachesize_override);
215 __setup("cachesize=", cachesize_setup);
217 static int __init x86_fxsr_setup(char *s)
219 setup_clear_cpu_cap(X86_FEATURE_FXSR);
220 setup_clear_cpu_cap(X86_FEATURE_XMM);
223 __setup("nofxsr", x86_fxsr_setup);
225 static int __init x86_sep_setup(char *s)
227 setup_clear_cpu_cap(X86_FEATURE_SEP);
230 __setup("nosep", x86_sep_setup);
232 /* Standard macro to see if a specific flag is changeable */
233 static inline int flag_is_changeable_p(u32 flag)
238 * Cyrix and IDT cpus allow disabling of CPUID
239 * so the code below may return different results
240 * when it is executed before and after enabling
241 * the CPUID. Add "volatile" to not allow gcc to
242 * optimize the subsequent calls to this function.
244 asm volatile ("pushfl \n\t"
255 : "=&r" (f1), "=&r" (f2)
258 return ((f1^f2) & flag) != 0;
261 /* Probe for the CPUID instruction */
262 static int __cpuinit have_cpuid_p(void)
264 return flag_is_changeable_p(X86_EFLAGS_ID);
267 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
269 unsigned long lo, hi;
271 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
274 /* Disable processor serial number: */
276 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
278 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
280 printk(KERN_NOTICE "CPU serial number disabled.\n");
281 clear_cpu_cap(c, X86_FEATURE_PN);
283 /* Disabling the serial number may affect the cpuid level */
284 c->cpuid_level = cpuid_eax(0);
287 static int __init x86_serial_nr_setup(char *s)
289 disable_x86_serial_nr = 0;
292 __setup("serialnumber", x86_serial_nr_setup);
294 static inline int flag_is_changeable_p(u32 flag)
298 /* Probe for the CPUID instruction */
299 static inline int have_cpuid_p(void)
303 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
308 static int disable_smep __cpuinitdata;
309 static __init int setup_disable_smep(char *arg)
314 __setup("nosmep", setup_disable_smep);
316 static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
318 if (cpu_has(c, X86_FEATURE_SMEP)) {
319 if (unlikely(disable_smep)) {
320 setup_clear_cpu_cap(X86_FEATURE_SMEP);
321 clear_in_cr4(X86_CR4_SMEP);
323 set_in_cr4(X86_CR4_SMEP);
327 static void setup_pcid(struct cpuinfo_x86 *c)
329 if (cpu_has(c, X86_FEATURE_PCID)) {
330 if (IS_ENABLED(CONFIG_X86_64) &&
331 (cpu_has(c, X86_FEATURE_PGE) || kaiser_enabled)) {
333 * Regardless of whether PCID is enumerated, the
334 * SDM says that it can't be enabled in 32-bit mode.
336 set_in_cr4(X86_CR4_PCIDE);
338 * INVPCID has two "groups" of types:
339 * 1/2: Invalidate an individual address
340 * 3/4: Invalidate all contexts
342 * 1/2 take a PCID, but 3/4 do not. So, 3/4
343 * ignore the PCID argument in the descriptor.
344 * But, we have to be careful not to call 1/2
345 * with an actual non-zero PCID in them before
346 * we do the above set_in_cr4().
348 if (cpu_has(c, X86_FEATURE_INVPCID))
349 set_cpu_cap(c, X86_FEATURE_INVPCID_SINGLE);
352 * flush_tlb_all(), as currently implemented, won't
353 * work if PCID is on but PGE is not. Since that
354 * combination doesn't exist on real hardware, there's
355 * no reason to try to fully support it, but it's
356 * polite to avoid corrupting data if we're on
357 * an improperly configured VM.
359 clear_cpu_cap(c, X86_FEATURE_PCID);
366 * Some CPU features depend on higher CPUID levels, which may not always
367 * be available due to CPUID level capping or broken virtualization
368 * software. Add those features to this table to auto-disable them.
370 struct cpuid_dependent_feature {
375 static const struct cpuid_dependent_feature __cpuinitconst
376 cpuid_dependent_features[] = {
377 { X86_FEATURE_MWAIT, 0x00000005 },
378 { X86_FEATURE_DCA, 0x00000009 },
379 { X86_FEATURE_XSAVE, 0x0000000d },
383 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
385 const struct cpuid_dependent_feature *df;
387 for (df = cpuid_dependent_features; df->feature; df++) {
389 if (!cpu_has(c, df->feature))
392 * Note: cpuid_level is set to -1 if unavailable, but
393 * extended_extended_level is set to 0 if unavailable
394 * and the legitimate extended levels are all negative
395 * when signed; hence the weird messing around with
398 if (!((s32)df->level < 0 ?
399 (u32)df->level > (u32)c->extended_cpuid_level :
400 (s32)df->level > (s32)c->cpuid_level))
403 clear_cpu_cap(c, df->feature);
408 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
409 x86_cap_flags[df->feature], df->level);
414 * Naming convention should be: <Name> [(<Codename>)]
415 * This table only is used unless init_<vendor>() below doesn't set it;
416 * in particular, if CPUID levels 0x80000002..4 are supported, this
420 /* Look up CPU names by table lookup. */
421 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
423 const struct cpu_model_info *info;
425 if (c->x86_model >= 16)
426 return NULL; /* Range check */
431 info = this_cpu->c_models;
433 while (info && info->family) {
434 if (info->family == c->x86)
435 return info->model_names[c->x86_model];
438 return NULL; /* Not found */
441 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
442 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
444 void load_percpu_segment(int cpu)
447 loadsegment(fs, __KERNEL_PERCPU);
450 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
452 load_stack_canary_segment();
456 * Current gdt points %fs at the "master" per-cpu area: after this,
457 * it's on the real one.
459 void switch_to_new_gdt(int cpu)
461 struct desc_ptr gdt_descr;
463 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
464 gdt_descr.size = GDT_SIZE - 1;
465 load_gdt(&gdt_descr);
466 /* Reload the per-cpu base */
468 load_percpu_segment(cpu);
471 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
473 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
478 if (c->extended_cpuid_level < 0x80000004)
481 v = (unsigned int *)c->x86_model_id;
482 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
483 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
484 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
485 c->x86_model_id[48] = 0;
488 * Intel chips right-justify this string for some dumb reason;
489 * undo that brain damage:
491 p = q = &c->x86_model_id[0];
497 while (q <= &c->x86_model_id[48])
498 *q++ = '\0'; /* Zero-pad the rest */
502 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
504 unsigned int n, dummy, ebx, ecx, edx, l2size;
506 n = c->extended_cpuid_level;
508 if (n >= 0x80000005) {
509 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
510 c->x86_cache_size = (ecx>>24) + (edx>>24);
512 /* On K8 L1 TLB is inclusive, so don't count it */
517 if (n < 0x80000006) /* Some chips just has a large L1. */
520 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
524 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
526 /* do processor-specific cache resizing */
527 if (this_cpu->c_size_cache)
528 l2size = this_cpu->c_size_cache(c, l2size);
530 /* Allow user to override all this if necessary. */
531 if (cachesize_override != -1)
532 l2size = cachesize_override;
535 return; /* Again, no L2 cache is possible */
538 c->x86_cache_size = l2size;
541 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
544 u32 eax, ebx, ecx, edx;
545 int index_msb, core_bits;
548 if (!cpu_has(c, X86_FEATURE_HT))
551 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
554 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
557 cpuid(1, &eax, &ebx, &ecx, &edx);
559 smp_num_siblings = (ebx & 0xff0000) >> 16;
561 if (smp_num_siblings == 1) {
562 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
566 if (smp_num_siblings <= 1)
569 index_msb = get_count_order(smp_num_siblings);
570 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
572 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
574 index_msb = get_count_order(smp_num_siblings);
576 core_bits = get_count_order(c->x86_max_cores);
578 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
579 ((1 << core_bits) - 1);
582 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
583 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
585 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
592 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
594 char *v = c->x86_vendor_id;
597 for (i = 0; i < X86_VENDOR_NUM; i++) {
601 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
602 (cpu_devs[i]->c_ident[1] &&
603 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
605 this_cpu = cpu_devs[i];
606 c->x86_vendor = this_cpu->c_x86_vendor;
612 "CPU: vendor_id '%s' unknown, using generic init.\n" \
613 "CPU: Your system may be unstable.\n", v);
615 c->x86_vendor = X86_VENDOR_UNKNOWN;
616 this_cpu = &default_cpu;
619 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
621 /* Get vendor name */
622 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
623 (unsigned int *)&c->x86_vendor_id[0],
624 (unsigned int *)&c->x86_vendor_id[8],
625 (unsigned int *)&c->x86_vendor_id[4]);
628 /* Intel-defined flags: level 0x00000001 */
629 if (c->cpuid_level >= 0x00000001) {
630 u32 junk, tfms, cap0, misc;
632 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
633 c->x86 = (tfms >> 8) & 0xf;
634 c->x86_model = (tfms >> 4) & 0xf;
635 c->x86_mask = tfms & 0xf;
638 c->x86 += (tfms >> 20) & 0xff;
640 c->x86_model += ((tfms >> 16) & 0xf) << 4;
642 if (cap0 & (1<<19)) {
643 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
644 c->x86_cache_alignment = c->x86_clflush_size;
649 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
654 /* Intel-defined flags: level 0x00000001 */
655 if (c->cpuid_level >= 0x00000001) {
656 u32 capability, excap;
658 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
659 c->x86_capability[0] = capability;
660 c->x86_capability[4] = excap;
663 /* Additional Intel-defined flags: level 0x00000007 */
664 if (c->cpuid_level >= 0x00000007) {
665 u32 eax, ebx, ecx, edx;
667 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
669 c->x86_capability[9] = ebx;
672 /* AMD-defined flags: level 0x80000001 */
673 xlvl = cpuid_eax(0x80000000);
674 c->extended_cpuid_level = xlvl;
676 if ((xlvl & 0xffff0000) == 0x80000000) {
677 if (xlvl >= 0x80000001) {
678 c->x86_capability[1] = cpuid_edx(0x80000001);
679 c->x86_capability[6] = cpuid_ecx(0x80000001);
683 if (c->extended_cpuid_level >= 0x80000008) {
684 u32 eax = cpuid_eax(0x80000008);
686 c->x86_virt_bits = (eax >> 8) & 0xff;
687 c->x86_phys_bits = eax & 0xff;
690 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
691 c->x86_phys_bits = 36;
694 if (c->extended_cpuid_level >= 0x80000007)
695 c->x86_power = cpuid_edx(0x80000007);
697 init_scattered_cpuid_features(c);
700 set_cpu_cap(c, X86_FEATURE_KAISER);
704 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
710 * First of all, decide if this is a 486 or higher
711 * It's a 486 if we can modify the AC flag
713 if (flag_is_changeable_p(X86_EFLAGS_AC))
718 for (i = 0; i < X86_VENDOR_NUM; i++)
719 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
720 c->x86_vendor_id[0] = 0;
721 cpu_devs[i]->c_identify(c);
722 if (c->x86_vendor_id[0]) {
731 * Do minimum CPU detection early.
732 * Fields really needed: vendor, cpuid_level, family, model, mask,
734 * The others are not touched to avoid unwanted side effects.
736 * WARNING: this function is only called on the BP. Don't add code here
737 * that is supposed to run on all CPUs.
739 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
742 c->x86_clflush_size = 64;
743 c->x86_phys_bits = 36;
744 c->x86_virt_bits = 48;
746 c->x86_clflush_size = 32;
747 c->x86_phys_bits = 32;
748 c->x86_virt_bits = 32;
750 c->x86_cache_alignment = c->x86_clflush_size;
752 memset(&c->x86_capability, 0, sizeof c->x86_capability);
753 c->extended_cpuid_level = 0;
756 identify_cpu_without_cpuid(c);
758 /* cyrix could have cpuid enabled via c_identify()*/
768 if (this_cpu->c_early_init)
769 this_cpu->c_early_init(c);
772 filter_cpuid_features(c, false);
776 if (this_cpu->c_bsp_init)
777 this_cpu->c_bsp_init(c);
780 void __init early_cpu_init(void)
782 const struct cpu_dev *const *cdev;
785 #ifdef CONFIG_PROCESSOR_SELECT
786 printk(KERN_INFO "KERNEL supported cpus:\n");
789 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
790 const struct cpu_dev *cpudev = *cdev;
792 if (count >= X86_VENDOR_NUM)
794 cpu_devs[count] = cpudev;
797 #ifdef CONFIG_PROCESSOR_SELECT
801 for (j = 0; j < 2; j++) {
802 if (!cpudev->c_ident[j])
804 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
810 early_identify_cpu(&boot_cpu_data);
814 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
815 * unfortunately, that's not true in practice because of early VIA
816 * chips and (more importantly) broken virtualizers that are not easy
817 * to detect. In the latter case it doesn't even *fail* reliably, so
818 * probing for it doesn't even work. Disable it completely on 32-bit
819 * unless we can find a reliable way to detect all the broken cases.
820 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
822 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
825 clear_cpu_cap(c, X86_FEATURE_NOPL);
827 set_cpu_cap(c, X86_FEATURE_NOPL);
831 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
833 c->extended_cpuid_level = 0;
836 identify_cpu_without_cpuid(c);
838 /* cyrix could have cpuid enabled via c_identify()*/
848 if (c->cpuid_level >= 0x00000001) {
849 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
851 # ifdef CONFIG_X86_HT
852 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
854 c->apicid = c->initial_apicid;
857 c->phys_proc_id = c->initial_apicid;
862 get_model_name(c); /* Default name */
868 * This does the hard work of actually picking apart the CPU stuff...
870 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
874 c->loops_per_jiffy = loops_per_jiffy;
875 c->x86_cache_size = -1;
876 c->x86_vendor = X86_VENDOR_UNKNOWN;
877 c->x86_model = c->x86_mask = 0; /* So far unknown... */
878 c->x86_vendor_id[0] = '\0'; /* Unset */
879 c->x86_model_id[0] = '\0'; /* Unset */
880 c->x86_max_cores = 1;
881 c->x86_coreid_bits = 0;
883 c->x86_clflush_size = 64;
884 c->x86_phys_bits = 36;
885 c->x86_virt_bits = 48;
887 c->cpuid_level = -1; /* CPUID not detected */
888 c->x86_clflush_size = 32;
889 c->x86_phys_bits = 32;
890 c->x86_virt_bits = 32;
892 c->x86_cache_alignment = c->x86_clflush_size;
893 memset(&c->x86_capability, 0, sizeof c->x86_capability);
897 if (this_cpu->c_identify)
898 this_cpu->c_identify(c);
900 /* Clear/Set all flags overriden by options, after probe */
901 for (i = 0; i < NCAPINTS; i++) {
902 c->x86_capability[i] &= ~cpu_caps_cleared[i];
903 c->x86_capability[i] |= cpu_caps_set[i];
907 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
911 * Vendor-specific initialization. In this section we
912 * canonicalize the feature flags, meaning if there are
913 * features a certain CPU supports which CPUID doesn't
914 * tell us, CPUID claiming incorrect flags, or other bugs,
915 * we handle them here.
917 * At the end of this section, c->x86_capability better
918 * indicate the features this CPU genuinely supports!
920 if (this_cpu->c_init)
923 /* Disable the PN if appropriate */
924 squash_the_stupid_serial_number(c);
930 * The vendor-specific functions might have changed features.
931 * Now we do "generic changes."
934 /* Filter out anything that depends on CPUID levels we don't have */
935 filter_cpuid_features(c, true);
937 /* If the model name is still unset, do table lookup. */
938 if (!c->x86_model_id[0]) {
940 p = table_lookup_model(c);
942 strcpy(c->x86_model_id, p);
945 sprintf(c->x86_model_id, "%02x/%02x",
946 c->x86, c->x86_model);
957 * Clear/Set all flags overriden by options, need do it
958 * before following smp all cpus cap AND.
960 for (i = 0; i < NCAPINTS; i++) {
961 c->x86_capability[i] &= ~cpu_caps_cleared[i];
962 c->x86_capability[i] |= cpu_caps_set[i];
966 * On SMP, boot_cpu_data holds the common feature set between
967 * all CPUs; so make sure that we indicate which features are
968 * common between the CPUs. The first time this routine gets
969 * executed, c == &boot_cpu_data.
971 if (c != &boot_cpu_data) {
972 /* AND the already accumulated flags with these */
973 for (i = 0; i < NCAPINTS; i++)
974 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
977 /* Init Machine Check Exception if available. */
980 select_idle_routine(c);
983 numa_add_cpu(smp_processor_id());
988 static void vgetcpu_set_mode(void)
990 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
991 vgetcpu_mode = VGETCPU_RDTSCP;
993 vgetcpu_mode = VGETCPU_LSL;
997 void __init identify_boot_cpu(void)
999 identify_cpu(&boot_cpu_data);
1000 init_amd_e400_c1e_mask();
1001 #ifdef CONFIG_X86_32
1009 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1011 BUG_ON(c == &boot_cpu_data);
1013 #ifdef CONFIG_X86_32
1024 static const struct msr_range msr_range_array[] __cpuinitconst = {
1025 { 0x00000000, 0x00000418},
1026 { 0xc0000000, 0xc000040b},
1027 { 0xc0010000, 0xc0010142},
1028 { 0xc0011000, 0xc001103b},
1031 static void __cpuinit print_cpu_msr(void)
1033 unsigned index_min, index_max;
1038 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1039 index_min = msr_range_array[i].min;
1040 index_max = msr_range_array[i].max;
1042 for (index = index_min; index < index_max; index++) {
1043 if (rdmsrl_amd_safe(index, &val))
1045 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1050 static int show_msr __cpuinitdata;
1052 static __init int setup_show_msr(char *arg)
1056 get_option(&arg, &num);
1062 __setup("show_msr=", setup_show_msr);
1064 static __init int setup_noclflush(char *arg)
1066 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1069 __setup("noclflush", setup_noclflush);
1071 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1073 const char *vendor = NULL;
1075 if (c->x86_vendor < X86_VENDOR_NUM) {
1076 vendor = this_cpu->c_vendor;
1078 if (c->cpuid_level >= 0)
1079 vendor = c->x86_vendor_id;
1082 if (vendor && !strstr(c->x86_model_id, vendor))
1083 printk(KERN_CONT "%s ", vendor);
1085 if (c->x86_model_id[0])
1086 printk(KERN_CONT "%s", c->x86_model_id);
1088 printk(KERN_CONT "%d86", c->x86);
1090 if (c->x86_mask || c->cpuid_level >= 0)
1091 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1093 printk(KERN_CONT "\n");
1096 if (c->cpu_index < show_msr)
1104 static __init int setup_disablecpuid(char *arg)
1108 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1109 setup_clear_cpu_cap(bit);
1115 __setup("clearcpuid=", setup_disablecpuid);
1117 #ifdef CONFIG_X86_64
1118 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1120 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1121 irq_stack_union) __aligned(PAGE_SIZE);
1124 * The following four percpu variables are hot. Align current_task to
1125 * cacheline size such that all four fall in the same cacheline.
1127 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1129 EXPORT_PER_CPU_SYMBOL(current_task);
1131 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1132 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1133 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1135 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1136 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1138 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1141 * Special IST stacks which the CPU switches to when it calls
1142 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1143 * limit), all of them are 4K, except the debug stack which
1146 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1147 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1148 [DEBUG_STACK - 1] = DEBUG_STKSZ
1151 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(char, exception_stacks
1152 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1154 /* May not be marked __init: used by software suspend */
1155 void syscall_init(void)
1158 * LSTAR and STAR live in a bit strange symbiosis.
1159 * They both write to the same internal register. STAR allows to
1160 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1162 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1163 wrmsrl(MSR_LSTAR, system_call);
1164 wrmsrl(MSR_CSTAR, ignore_sysret);
1166 #ifdef CONFIG_IA32_EMULATION
1167 syscall32_cpu_init();
1170 /* Flags to clear on syscall */
1171 wrmsrl(MSR_SYSCALL_MASK,
1172 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1175 unsigned long kernel_eflags;
1178 * Copies of the original ist values from the tss are only accessed during
1179 * debugging, no special alignment required.
1181 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1183 #else /* CONFIG_X86_64 */
1185 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1186 EXPORT_PER_CPU_SYMBOL(current_task);
1188 #ifdef CONFIG_CC_STACKPROTECTOR
1189 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1192 /* Make sure %fs and %gs are initialized properly in idle threads */
1193 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1195 memset(regs, 0, sizeof(struct pt_regs));
1196 regs->fs = __KERNEL_PERCPU;
1197 regs->gs = __KERNEL_STACK_CANARY;
1201 #endif /* CONFIG_X86_64 */
1204 * Clear all 6 debug registers:
1206 static void clear_all_debug_regs(void)
1210 for (i = 0; i < 8; i++) {
1211 /* Ignore db4, db5 */
1212 if ((i == 4) || (i == 5))
1221 * Restore debug regs if using kgdbwait and you have a kernel debugger
1222 * connection established.
1224 static void dbg_restore_debug_regs(void)
1226 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1227 arch_kgdb_ops.correct_hw_break();
1229 #else /* ! CONFIG_KGDB */
1230 #define dbg_restore_debug_regs()
1231 #endif /* ! CONFIG_KGDB */
1234 * cpu_init() initializes state that is per-CPU. Some data is already
1235 * initialized (naturally) in the bootstrap process, such as the GDT
1236 * and IDT. We reload them nevertheless, this function acts as a
1237 * 'CPU state barrier', nothing should get across.
1238 * A lot of state is already set up in PDA init for 64 bit
1240 #ifdef CONFIG_X86_64
1242 void __cpuinit cpu_init(void)
1244 struct orig_ist *oist;
1245 struct task_struct *me;
1246 struct tss_struct *t;
1251 if (!kaiser_enabled) {
1253 * secondary_startup_64() deferred setting PGE in cr4:
1254 * init_memory_mapping() sets it on the boot cpu,
1255 * but it needs to be set on each secondary cpu.
1257 set_in_cr4(X86_CR4_PGE);
1260 cpu = stack_smp_processor_id();
1261 t = &per_cpu(init_tss, cpu);
1262 oist = &per_cpu(orig_ist, cpu);
1265 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1266 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1267 set_numa_node(early_cpu_to_node(cpu));
1272 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1273 panic("CPU#%d already initialized!\n", cpu);
1275 pr_debug("Initializing CPU#%d\n", cpu);
1277 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1280 * Initialize the per-CPU GDT with the boot GDT,
1281 * and set up the GDT descriptor:
1284 switch_to_new_gdt(cpu);
1287 load_idt((const struct desc_ptr *)&idt_descr);
1289 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1292 wrmsrl(MSR_FS_BASE, 0);
1293 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1301 * set up and load the per-CPU TSS
1303 if (!oist->ist[0]) {
1304 char *estacks = per_cpu(exception_stacks, cpu);
1306 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1307 estacks += exception_stack_sizes[v];
1308 oist->ist[v] = t->x86_tss.ist[v] =
1309 (unsigned long)estacks;
1313 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1316 * <= is required because the CPU will access up to
1317 * 8 bits beyond the end of the IO permission bitmap.
1319 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1320 t->io_bitmap[i] = ~0UL;
1322 atomic_inc(&init_mm.mm_count);
1323 me->active_mm = &init_mm;
1325 enter_lazy_tlb(&init_mm, me);
1327 load_sp0(t, ¤t->thread);
1328 set_tss_desc(cpu, t);
1330 load_mm_ldt(&init_mm);
1332 clear_all_debug_regs();
1333 dbg_restore_debug_regs();
1338 raw_local_save_flags(kernel_eflags);
1346 void __cpuinit cpu_init(void)
1348 int cpu = smp_processor_id();
1349 struct task_struct *curr = current;
1350 struct tss_struct *t = &per_cpu(init_tss, cpu);
1351 struct thread_struct *thread = &curr->thread;
1353 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1354 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1359 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1361 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1362 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1364 load_idt(&idt_descr);
1365 switch_to_new_gdt(cpu);
1368 * Set up and load the per-CPU TSS and LDT
1370 atomic_inc(&init_mm.mm_count);
1371 curr->active_mm = &init_mm;
1373 enter_lazy_tlb(&init_mm, curr);
1375 load_sp0(t, thread);
1376 set_tss_desc(cpu, t);
1378 load_mm_ldt(&init_mm);
1380 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1382 #ifdef CONFIG_DOUBLEFAULT
1383 /* Set up doublefault TSS pointer in the GDT */
1384 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1387 clear_all_debug_regs();
1388 dbg_restore_debug_regs();