1 #ifndef _ASM_X86_TLBFLUSH_H
2 #define _ASM_X86_TLBFLUSH_H
5 #include <linux/sched.h>
7 #include <asm/processor.h>
8 #include <asm/system.h>
11 static inline void __invpcid(unsigned long pcid, unsigned long addr,
14 struct { u64 d[2]; } desc = { { pcid, addr } };
17 * The memory clobber is because the whole point is to invalidate
18 * stale TLB entries and, especially if we're flushing global
19 * mappings, we don't want the compiler to reorder any subsequent
20 * memory accesses before the TLB flush.
22 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
23 * invpcid (%rcx), %rax in long mode.
25 asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
26 : : "m" (desc), "a" (type), "c" (&desc) : "memory");
29 #define INVPCID_TYPE_INDIV_ADDR 0
30 #define INVPCID_TYPE_SINGLE_CTXT 1
31 #define INVPCID_TYPE_ALL_INCL_GLOBAL 2
32 #define INVPCID_TYPE_ALL_NON_GLOBAL 3
34 /* Flush all mappings for a given pcid and addr, not including globals. */
35 static inline void invpcid_flush_one(unsigned long pcid,
38 __invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
41 /* Flush all mappings for a given PCID, not including globals. */
42 static inline void invpcid_flush_single_context(unsigned long pcid)
44 __invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
47 /* Flush all mappings, including globals, for all PCIDs. */
48 static inline void invpcid_flush_all(void)
50 __invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
53 /* Flush all mappings for all PCIDs except globals. */
54 static inline void invpcid_flush_all_nonglobals(void)
56 __invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
59 #ifdef CONFIG_PARAVIRT
60 #include <asm/paravirt.h>
62 #define __flush_tlb() __native_flush_tlb()
63 #define __flush_tlb_global() __native_flush_tlb_global()
64 #define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
67 static inline void __native_flush_tlb(void)
70 * If current->mm == NULL then we borrow a mm which may change during a
71 * task switch and therefore we must not be preempted while we write CR3
75 native_write_cr3(native_read_cr3());
79 static inline void __native_flush_tlb_global(void)
84 if (static_cpu_has(X86_FEATURE_INVPCID)) {
86 * Using INVPCID is considerably faster than a pair of writes
87 * to CR4 sandwiched inside an IRQ flag save/restore.
94 * Read-modify-write to CR4 - protect it from preemption and
95 * from interrupts. (Use the raw variant because this code can
96 * be called from deep inside debugging code.)
98 raw_local_irq_save(flags);
100 cr4 = native_read_cr4();
102 native_write_cr4(cr4 & ~X86_CR4_PGE);
103 /* write old PGE again and flush TLBs */
104 native_write_cr4(cr4);
106 raw_local_irq_restore(flags);
109 static inline void __native_flush_tlb_single(unsigned long addr)
111 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
114 static inline void __flush_tlb_all(void)
117 __flush_tlb_global();
122 * Note: if we somehow had PCID but not PGE, then this wouldn't work --
123 * we'd end up flushing kernel translations for the current ASID but
124 * we might fail to flush kernel translations for other cached ASIDs.
126 * To avoid this issue, we force PCID off if PGE is off.
130 static inline void __flush_tlb_one(unsigned long addr)
133 __flush_tlb_single(addr);
139 # define TLB_FLUSH_ALL 0xffffffff
141 # define TLB_FLUSH_ALL -1ULL
147 * - flush_tlb() flushes the current mm struct TLBs
148 * - flush_tlb_all() flushes all processes TLBs
149 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
150 * - flush_tlb_page(vma, vmaddr) flushes one page
151 * - flush_tlb_range(vma, start, end) flushes a range of pages
152 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
153 * - flush_tlb_others(cpumask, mm, va) flushes TLBs on other cpus
155 * ..but the i386 has somewhat limited tlb flushing capabilities,
156 * and page-granular flushes are available only on i486 and up.
159 #define local_flush_tlb() __flush_tlb()
161 extern void flush_tlb_all(void);
162 extern void flush_tlb_current_task(void);
163 extern void flush_tlb_mm(struct mm_struct *);
164 extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
166 #define flush_tlb() flush_tlb_current_task()
168 static inline void flush_tlb_range(struct vm_area_struct *vma,
169 unsigned long start, unsigned long end)
171 flush_tlb_mm(vma->vm_mm);
174 void native_flush_tlb_others(const struct cpumask *cpumask,
175 struct mm_struct *mm, unsigned long va);
177 #define TLBSTATE_OK 1
178 #define TLBSTATE_LAZY 2
181 struct mm_struct *active_mm;
184 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
186 static inline void reset_lazy_tlbstate(void)
188 percpu_write(cpu_tlbstate.state, 0);
189 percpu_write(cpu_tlbstate.active_mm, &init_mm);
192 #ifndef CONFIG_PARAVIRT
193 #define flush_tlb_others(mask, mm, va) native_flush_tlb_others(mask, mm, va)
196 static inline void flush_tlb_kernel_range(unsigned long start,
202 #endif /* _ASM_X86_TLBFLUSH_H */