1 #ifndef _ASM_X86_MSR_INDEX_H
2 #define _ASM_X86_MSR_INDEX_H
4 /* CPU model specific register (MSR) numbers */
6 /* x86-64 specific MSRs */
7 #define MSR_EFER 0xc0000080 /* extended feature register */
8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
19 #define _EFER_LME 8 /* Long mode enable */
20 #define _EFER_LMA 10 /* Long mode active (read-only) */
21 #define _EFER_NX 11 /* No execute enable */
22 #define _EFER_SVME 12 /* Enable virtualization */
23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
26 #define EFER_SCE (1<<_EFER_SCE)
27 #define EFER_LME (1<<_EFER_LME)
28 #define EFER_LMA (1<<_EFER_LMA)
29 #define EFER_NX (1<<_EFER_NX)
30 #define EFER_SVME (1<<_EFER_SVME)
31 #define EFER_LMSLE (1<<_EFER_LMSLE)
32 #define EFER_FFXSR (1<<_EFER_FFXSR)
34 /* Intel MSRs. Some also available on other CPUs */
35 #define MSR_IA32_PERFCTR0 0x000000c1
36 #define MSR_IA32_PERFCTR1 0x000000c2
37 #define MSR_FSB_FREQ 0x000000cd
39 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
40 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
41 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
42 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
44 #define MSR_MTRRcap 0x000000fe
45 #define MSR_IA32_BBL_CR_CTL 0x00000119
46 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
48 #define MSR_IA32_SYSENTER_CS 0x00000174
49 #define MSR_IA32_SYSENTER_ESP 0x00000175
50 #define MSR_IA32_SYSENTER_EIP 0x00000176
52 #define MSR_IA32_MCG_CAP 0x00000179
53 #define MSR_IA32_MCG_STATUS 0x0000017a
54 #define MSR_IA32_MCG_CTL 0x0000017b
56 #define MSR_OFFCORE_RSP_0 0x000001a6
57 #define MSR_OFFCORE_RSP_1 0x000001a7
59 #define MSR_IA32_PEBS_ENABLE 0x000003f1
60 #define MSR_IA32_DS_AREA 0x00000600
61 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
63 #define MSR_MTRRfix64K_00000 0x00000250
64 #define MSR_MTRRfix16K_80000 0x00000258
65 #define MSR_MTRRfix16K_A0000 0x00000259
66 #define MSR_MTRRfix4K_C0000 0x00000268
67 #define MSR_MTRRfix4K_C8000 0x00000269
68 #define MSR_MTRRfix4K_D0000 0x0000026a
69 #define MSR_MTRRfix4K_D8000 0x0000026b
70 #define MSR_MTRRfix4K_E0000 0x0000026c
71 #define MSR_MTRRfix4K_E8000 0x0000026d
72 #define MSR_MTRRfix4K_F0000 0x0000026e
73 #define MSR_MTRRfix4K_F8000 0x0000026f
74 #define MSR_MTRRdefType 0x000002ff
76 #define MSR_IA32_CR_PAT 0x00000277
78 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
79 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
80 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
81 #define MSR_IA32_LASTINTFROMIP 0x000001dd
82 #define MSR_IA32_LASTINTTOIP 0x000001de
84 /* DEBUGCTLMSR bits (others vary by model): */
85 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
86 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
87 #define DEBUGCTLMSR_TR (1UL << 6)
88 #define DEBUGCTLMSR_BTS (1UL << 7)
89 #define DEBUGCTLMSR_BTINT (1UL << 8)
90 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
91 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
92 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
94 #define MSR_IA32_MC0_CTL 0x00000400
95 #define MSR_IA32_MC0_STATUS 0x00000401
96 #define MSR_IA32_MC0_ADDR 0x00000402
97 #define MSR_IA32_MC0_MISC 0x00000403
99 #define MSR_AMD64_MC0_MASK 0xc0010044
101 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
102 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
103 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
104 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
106 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
108 /* These are consecutive and not in the normal 4er MCE bank block */
109 #define MSR_IA32_MC0_CTL2 0x00000280
110 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
112 #define MSR_P6_PERFCTR0 0x000000c1
113 #define MSR_P6_PERFCTR1 0x000000c2
114 #define MSR_P6_EVNTSEL0 0x00000186
115 #define MSR_P6_EVNTSEL1 0x00000187
117 /* AMD64 MSRs. Not complete. See the architecture manual for a more
120 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
121 #define MSR_AMD64_TSC_RATIO 0xc0000104
122 #define MSR_AMD64_NB_CFG 0xc001001f
123 #define MSR_AMD64_PATCH_LOADER 0xc0010020
124 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
125 #define MSR_AMD64_OSVW_STATUS 0xc0010141
126 #define MSR_AMD64_LS_CFG 0xc0011020
127 #define MSR_AMD64_DC_CFG 0xc0011022
128 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
129 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
130 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
131 #define MSR_AMD64_IBSOPCTL 0xc0011033
132 #define MSR_AMD64_IBSOPRIP 0xc0011034
133 #define MSR_AMD64_IBSOPDATA 0xc0011035
134 #define MSR_AMD64_IBSOPDATA2 0xc0011036
135 #define MSR_AMD64_IBSOPDATA3 0xc0011037
136 #define MSR_AMD64_IBSDCLINAD 0xc0011038
137 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
138 #define MSR_AMD64_IBSCTL 0xc001103a
139 #define MSR_AMD64_IBSBRTARGET 0xc001103b
142 #define MSR_F15H_PERF_CTL 0xc0010200
143 #define MSR_F15H_PERF_CTR 0xc0010201
146 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
147 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
148 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
149 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
150 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
151 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
152 #define MSR_FAM10H_NODE_ID 0xc001100c
155 #define MSR_K8_TOP_MEM1 0xc001001a
156 #define MSR_K8_TOP_MEM2 0xc001001d
157 #define MSR_K8_SYSCFG 0xc0010010
158 #define MSR_K8_INT_PENDING_MSG 0xc0010055
159 /* C1E active bits in int pending message */
160 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
161 #define MSR_K8_TSEG_ADDR 0xc0010112
162 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
163 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
164 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
167 #define MSR_K7_EVNTSEL0 0xc0010000
168 #define MSR_K7_PERFCTR0 0xc0010004
169 #define MSR_K7_EVNTSEL1 0xc0010001
170 #define MSR_K7_PERFCTR1 0xc0010005
171 #define MSR_K7_EVNTSEL2 0xc0010002
172 #define MSR_K7_PERFCTR2 0xc0010006
173 #define MSR_K7_EVNTSEL3 0xc0010003
174 #define MSR_K7_PERFCTR3 0xc0010007
175 #define MSR_K7_CLK_CTL 0xc001001b
176 #define MSR_K7_HWCR 0xc0010015
177 #define MSR_K7_FID_VID_CTL 0xc0010041
178 #define MSR_K7_FID_VID_STATUS 0xc0010042
181 #define MSR_K6_WHCR 0xc0000082
182 #define MSR_K6_UWCCR 0xc0000085
183 #define MSR_K6_EPMR 0xc0000086
184 #define MSR_K6_PSOR 0xc0000087
185 #define MSR_K6_PFIR 0xc0000088
187 /* Centaur-Hauls/IDT defined MSRs. */
188 #define MSR_IDT_FCR1 0x00000107
189 #define MSR_IDT_FCR2 0x00000108
190 #define MSR_IDT_FCR3 0x00000109
191 #define MSR_IDT_FCR4 0x0000010a
193 #define MSR_IDT_MCR0 0x00000110
194 #define MSR_IDT_MCR1 0x00000111
195 #define MSR_IDT_MCR2 0x00000112
196 #define MSR_IDT_MCR3 0x00000113
197 #define MSR_IDT_MCR4 0x00000114
198 #define MSR_IDT_MCR5 0x00000115
199 #define MSR_IDT_MCR6 0x00000116
200 #define MSR_IDT_MCR7 0x00000117
201 #define MSR_IDT_MCR_CTRL 0x00000120
203 /* VIA Cyrix defined MSRs*/
204 #define MSR_VIA_FCR 0x00001107
205 #define MSR_VIA_LONGHAUL 0x0000110a
206 #define MSR_VIA_RNG 0x0000110b
207 #define MSR_VIA_BCR2 0x00001147
209 /* Transmeta defined MSRs */
210 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
211 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
212 #define MSR_TMTA_LRTI_READOUT 0x80868018
213 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
215 /* Intel defined MSRs. */
216 #define MSR_IA32_P5_MC_ADDR 0x00000000
217 #define MSR_IA32_P5_MC_TYPE 0x00000001
218 #define MSR_IA32_TSC 0x00000010
219 #define MSR_IA32_PLATFORM_ID 0x00000017
220 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
221 #define MSR_EBC_FREQUENCY_ID 0x0000002c
222 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
224 #define FEATURE_CONTROL_LOCKED (1<<0)
225 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
226 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
228 #define MSR_IA32_APICBASE 0x0000001b
229 #define MSR_IA32_APICBASE_BSP (1<<8)
230 #define MSR_IA32_APICBASE_ENABLE (1<<11)
231 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
233 #define MSR_IA32_TSCDEADLINE 0x000006e0
235 #define MSR_IA32_UCODE_WRITE 0x00000079
236 #define MSR_IA32_UCODE_REV 0x0000008b
238 #define MSR_IA32_PERF_STATUS 0x00000198
239 #define MSR_IA32_PERF_CTL 0x00000199
241 #define MSR_IA32_MPERF 0x000000e7
242 #define MSR_IA32_APERF 0x000000e8
244 #define MSR_IA32_THERM_CONTROL 0x0000019a
245 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
247 #define THERM_INT_HIGH_ENABLE (1 << 0)
248 #define THERM_INT_LOW_ENABLE (1 << 1)
249 #define THERM_INT_PLN_ENABLE (1 << 24)
251 #define MSR_IA32_THERM_STATUS 0x0000019c
253 #define THERM_STATUS_PROCHOT (1 << 0)
254 #define THERM_STATUS_POWER_LIMIT (1 << 10)
256 #define MSR_THERM2_CTL 0x0000019d
258 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
260 #define MSR_IA32_MISC_ENABLE 0x000001a0
262 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
264 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
265 #define ENERGY_PERF_BIAS_PERFORMANCE 0
266 #define ENERGY_PERF_BIAS_NORMAL 6
267 #define ENERGY_PERF_BIAS_POWERSAVE 15
269 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
271 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
272 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
274 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
276 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
277 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
278 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
280 /* Thermal Thresholds Support */
281 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
282 #define THERM_SHIFT_THRESHOLD0 8
283 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
284 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
285 #define THERM_SHIFT_THRESHOLD1 16
286 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
287 #define THERM_STATUS_THRESHOLD0 (1 << 6)
288 #define THERM_LOG_THRESHOLD0 (1 << 7)
289 #define THERM_STATUS_THRESHOLD1 (1 << 8)
290 #define THERM_LOG_THRESHOLD1 (1 << 9)
292 /* MISC_ENABLE bits: architectural */
293 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
294 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
295 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
296 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
297 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
298 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
299 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
300 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
301 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
302 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
304 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
305 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
306 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
307 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
308 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
309 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
310 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
311 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
312 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
313 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
314 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
315 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
316 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
317 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
318 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
319 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
321 /* P4/Xeon+ specific */
322 #define MSR_IA32_MCG_EAX 0x00000180
323 #define MSR_IA32_MCG_EBX 0x00000181
324 #define MSR_IA32_MCG_ECX 0x00000182
325 #define MSR_IA32_MCG_EDX 0x00000183
326 #define MSR_IA32_MCG_ESI 0x00000184
327 #define MSR_IA32_MCG_EDI 0x00000185
328 #define MSR_IA32_MCG_EBP 0x00000186
329 #define MSR_IA32_MCG_ESP 0x00000187
330 #define MSR_IA32_MCG_EFLAGS 0x00000188
331 #define MSR_IA32_MCG_EIP 0x00000189
332 #define MSR_IA32_MCG_RESERVED 0x0000018a
334 /* Pentium IV performance counter MSRs */
335 #define MSR_P4_BPU_PERFCTR0 0x00000300
336 #define MSR_P4_BPU_PERFCTR1 0x00000301
337 #define MSR_P4_BPU_PERFCTR2 0x00000302
338 #define MSR_P4_BPU_PERFCTR3 0x00000303
339 #define MSR_P4_MS_PERFCTR0 0x00000304
340 #define MSR_P4_MS_PERFCTR1 0x00000305
341 #define MSR_P4_MS_PERFCTR2 0x00000306
342 #define MSR_P4_MS_PERFCTR3 0x00000307
343 #define MSR_P4_FLAME_PERFCTR0 0x00000308
344 #define MSR_P4_FLAME_PERFCTR1 0x00000309
345 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
346 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
347 #define MSR_P4_IQ_PERFCTR0 0x0000030c
348 #define MSR_P4_IQ_PERFCTR1 0x0000030d
349 #define MSR_P4_IQ_PERFCTR2 0x0000030e
350 #define MSR_P4_IQ_PERFCTR3 0x0000030f
351 #define MSR_P4_IQ_PERFCTR4 0x00000310
352 #define MSR_P4_IQ_PERFCTR5 0x00000311
353 #define MSR_P4_BPU_CCCR0 0x00000360
354 #define MSR_P4_BPU_CCCR1 0x00000361
355 #define MSR_P4_BPU_CCCR2 0x00000362
356 #define MSR_P4_BPU_CCCR3 0x00000363
357 #define MSR_P4_MS_CCCR0 0x00000364
358 #define MSR_P4_MS_CCCR1 0x00000365
359 #define MSR_P4_MS_CCCR2 0x00000366
360 #define MSR_P4_MS_CCCR3 0x00000367
361 #define MSR_P4_FLAME_CCCR0 0x00000368
362 #define MSR_P4_FLAME_CCCR1 0x00000369
363 #define MSR_P4_FLAME_CCCR2 0x0000036a
364 #define MSR_P4_FLAME_CCCR3 0x0000036b
365 #define MSR_P4_IQ_CCCR0 0x0000036c
366 #define MSR_P4_IQ_CCCR1 0x0000036d
367 #define MSR_P4_IQ_CCCR2 0x0000036e
368 #define MSR_P4_IQ_CCCR3 0x0000036f
369 #define MSR_P4_IQ_CCCR4 0x00000370
370 #define MSR_P4_IQ_CCCR5 0x00000371
371 #define MSR_P4_ALF_ESCR0 0x000003ca
372 #define MSR_P4_ALF_ESCR1 0x000003cb
373 #define MSR_P4_BPU_ESCR0 0x000003b2
374 #define MSR_P4_BPU_ESCR1 0x000003b3
375 #define MSR_P4_BSU_ESCR0 0x000003a0
376 #define MSR_P4_BSU_ESCR1 0x000003a1
377 #define MSR_P4_CRU_ESCR0 0x000003b8
378 #define MSR_P4_CRU_ESCR1 0x000003b9
379 #define MSR_P4_CRU_ESCR2 0x000003cc
380 #define MSR_P4_CRU_ESCR3 0x000003cd
381 #define MSR_P4_CRU_ESCR4 0x000003e0
382 #define MSR_P4_CRU_ESCR5 0x000003e1
383 #define MSR_P4_DAC_ESCR0 0x000003a8
384 #define MSR_P4_DAC_ESCR1 0x000003a9
385 #define MSR_P4_FIRM_ESCR0 0x000003a4
386 #define MSR_P4_FIRM_ESCR1 0x000003a5
387 #define MSR_P4_FLAME_ESCR0 0x000003a6
388 #define MSR_P4_FLAME_ESCR1 0x000003a7
389 #define MSR_P4_FSB_ESCR0 0x000003a2
390 #define MSR_P4_FSB_ESCR1 0x000003a3
391 #define MSR_P4_IQ_ESCR0 0x000003ba
392 #define MSR_P4_IQ_ESCR1 0x000003bb
393 #define MSR_P4_IS_ESCR0 0x000003b4
394 #define MSR_P4_IS_ESCR1 0x000003b5
395 #define MSR_P4_ITLB_ESCR0 0x000003b6
396 #define MSR_P4_ITLB_ESCR1 0x000003b7
397 #define MSR_P4_IX_ESCR0 0x000003c8
398 #define MSR_P4_IX_ESCR1 0x000003c9
399 #define MSR_P4_MOB_ESCR0 0x000003aa
400 #define MSR_P4_MOB_ESCR1 0x000003ab
401 #define MSR_P4_MS_ESCR0 0x000003c0
402 #define MSR_P4_MS_ESCR1 0x000003c1
403 #define MSR_P4_PMH_ESCR0 0x000003ac
404 #define MSR_P4_PMH_ESCR1 0x000003ad
405 #define MSR_P4_RAT_ESCR0 0x000003bc
406 #define MSR_P4_RAT_ESCR1 0x000003bd
407 #define MSR_P4_SAAT_ESCR0 0x000003ae
408 #define MSR_P4_SAAT_ESCR1 0x000003af
409 #define MSR_P4_SSU_ESCR0 0x000003be
410 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
412 #define MSR_P4_TBPU_ESCR0 0x000003c2
413 #define MSR_P4_TBPU_ESCR1 0x000003c3
414 #define MSR_P4_TC_ESCR0 0x000003c4
415 #define MSR_P4_TC_ESCR1 0x000003c5
416 #define MSR_P4_U2L_ESCR0 0x000003b0
417 #define MSR_P4_U2L_ESCR1 0x000003b1
419 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
421 /* Intel Core-based CPU performance counters */
422 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
423 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
424 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
425 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
426 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
427 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
428 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
430 /* Geode defined MSRs */
431 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
434 #define MSR_IA32_VMX_BASIC 0x00000480
435 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
436 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
437 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
438 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
439 #define MSR_IA32_VMX_MISC 0x00000485
440 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
441 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
442 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
443 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
444 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
445 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
446 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
447 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
448 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
449 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
450 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
452 /* VMX_BASIC bits and bitmasks */
453 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
454 #define VMX_BASIC_64 0x0001000000000000LLU
455 #define VMX_BASIC_MEM_TYPE_SHIFT 50
456 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
457 #define VMX_BASIC_MEM_TYPE_WB 6LLU
458 #define VMX_BASIC_INOUT 0x0040000000000000LLU
462 #define MSR_VM_CR 0xc0010114
463 #define MSR_VM_IGNNE 0xc0010115
464 #define MSR_VM_HSAVE_PA 0xc0010117
466 #endif /* _ASM_X86_MSR_INDEX_H */