2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/cache.h>
15 #include <asm/errno.h>
16 #include <asm/ptrace.h>
17 #include <asm/thread_info.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/unistd.h>
23 * Stack layout for the system_call stack entry.
24 * The first few entries are identical to the user_regs_struct.
26 SP_PTREGS = STACK_FRAME_OVERHEAD
27 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
28 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
29 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
30 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
31 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
32 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
33 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
34 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
35 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
36 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
37 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
38 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
39 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
40 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
41 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
42 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
43 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
44 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
45 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
46 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
47 SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR
48 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
50 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
51 STACK_SIZE = 1 << STACK_SHIFT
53 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
54 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
55 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
57 _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
58 _TIF_SECCOMP>>8 | _TIF_SYSCALL_TRACEPOINT>>8)
60 #define BASED(name) name-system_call(%r13)
62 #ifdef CONFIG_TRACE_IRQFLAGS
65 brasl %r14,trace_hardirqs_on_caller
70 brasl %r14,trace_hardirqs_off_caller
73 .macro TRACE_IRQS_CHECK_ON
74 tm SP_PSW(%r15),0x03 # irqs enabled?
80 .macro TRACE_IRQS_CHECK_OFF
81 tm SP_PSW(%r15),0x03 # irqs enabled?
88 #define TRACE_IRQS_OFF
89 #define TRACE_IRQS_CHECK_ON
90 #define TRACE_IRQS_CHECK_OFF
94 .macro LOCKDEP_SYS_EXIT
95 tm SP_PSW+1(%r15),0x01 # returning to user ?
97 brasl %r14,lockdep_sys_exit
101 #define LOCKDEP_SYS_EXIT
104 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
112 * Register usage in interrupt handlers:
113 * R9 - pointer to current task structure
114 * R13 - pointer to literal pool
115 * R14 - return register for function calls
116 * R15 - kernel stack pointer
119 .macro SAVE_ALL_BASE savearea
120 stmg %r12,%r15,\savearea
121 larl %r13,system_call
124 .macro SAVE_ALL_SVC psworg,savearea
126 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
129 .macro SAVE_ALL_SYNC psworg,savearea
131 tm \psworg+1,0x01 # test problem state bit
132 jz 2f # skip stack setup save
133 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
134 #ifdef CONFIG_CHECK_STACK
136 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
143 .macro SAVE_ALL_ASYNC psworg,savearea
145 tm \psworg+1,0x01 # test problem state bit
146 jnz 1f # from user -> load kernel stack
147 clc \psworg+8(8),BASED(.Lcritical_end)
149 clc \psworg+8(8),BASED(.Lcritical_start)
151 brasl %r14,cleanup_critical
152 tm 1(%r12),0x01 # retest problem state after cleanup
154 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
156 srag %r14,%r14,STACK_SHIFT
158 1: lg %r15,__LC_ASYNC_STACK # load async stack
159 #ifdef CONFIG_CHECK_STACK
161 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
168 .macro CREATE_STACK_FRAME psworg,savearea
169 aghi %r15,-SP_SIZE # make room for registers & psw
170 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
171 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
172 icm %r12,3,__LC_SVC_ILC
173 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
174 st %r12,SP_SVCNR(%r15)
175 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
177 stg %r12,__SF_BACKCHAIN(%r15)
180 .macro RESTORE_ALL psworg,sync
181 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
183 ni \psworg+1,0xfd # clear wait state bit
185 lg %r14,__LC_VDSO_PER_CPU
186 lmg %r0,%r13,SP_R0(%r15) # load gprs 0-13 of user
188 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
189 lmg %r14,%r15,SP_R14(%r15) # load grps 14-15 of user
190 lpswe \psworg # back to caller
194 * Scheduler resume function, called by switch_to
195 * gpr2 = (task_struct *) prev
196 * gpr3 = (task_struct *) next
202 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
203 jz __switch_to_noper # if not we're fine
204 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
205 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
206 je __switch_to_noper # we got away without bashing TLB's
207 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
209 lg %r4,__THREAD_info(%r2) # get thread_info of prev
210 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
211 jz __switch_to_no_mcck
212 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
213 lg %r4,__THREAD_info(%r3) # get thread_info of next
214 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
216 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
217 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
218 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
219 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
220 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
221 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
222 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
223 stg %r3,__LC_THREAD_INFO
225 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
230 * SVC interrupt handler routine. System calls are synchronous events and
231 * are executed with interrupts enabled.
236 stpt __LC_SYNC_ENTER_TIMER
238 SAVE_ALL_BASE __LC_SAVE_AREA
239 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
240 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
241 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
243 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
245 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
247 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
249 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
250 ltgr %r7,%r7 # test for svc 0
252 # svc 0: system call number in %r1
253 cl %r1,BASED(.Lnr_syscalls)
255 lgfr %r7,%r1 # clear high word in r1
257 mvc SP_ARGS(8,%r15),SP_R7(%r15)
259 sth %r7,SP_SVCNR(%r15)
260 sllg %r7,%r7,2 # svc number * 4
261 larl %r10,sys_call_table
263 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
265 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
268 tm __TI_flags+6(%r9),_TIF_SYSCALL
269 lgf %r8,0(%r7,%r10) # load address of system call routine
271 basr %r14,%r8 # call sys_xxxx
272 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
277 tm __TI_flags+7(%r9),_TIF_WORK_SVC
278 jnz sysc_work # there is work to do (signals etc.)
280 RESTORE_ALL __LC_RETURN_PSW,1
284 # There is work to do, but first we need to check if we return to userspace.
287 tm SP_PSW+1(%r15),0x01 # returning to user ?
291 # One of the work bits is on. Find out which one.
294 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
296 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
298 tm __TI_flags+7(%r9),_TIF_SIGPENDING
300 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
301 jo sysc_notify_resume
302 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
304 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
306 j sysc_return # beware of critical section cleanup
309 # _TIF_NEED_RESCHED is set, call schedule
312 larl %r14,sysc_return
313 jg schedule # return point is sysc_return
316 # _TIF_MCCK_PENDING is set, call handler
319 larl %r14,sysc_return
320 jg s390_handle_mcck # TIF bit will be cleared by handler
323 # _TIF_SIGPENDING is set, call do_signal
326 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
327 la %r2,SP_PTREGS(%r15) # load pt_regs
328 brasl %r14,do_signal # call do_signal
329 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
331 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
336 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
339 la %r2,SP_PTREGS(%r15) # load pt_regs
340 larl %r14,sysc_return
341 jg do_notify_resume # call do_notify_resume
344 # _TIF_RESTART_SVC is set, set up registers and restart svc
347 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
348 lg %r7,SP_R2(%r15) # load new svc number
349 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
350 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
351 j sysc_do_restart # restart svc
354 # _TIF_SINGLE_STEP is set, call do_single_step
357 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
358 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
359 la %r2,SP_PTREGS(%r15) # address of register-save area
360 larl %r14,sysc_return # load adr. of system return
361 jg do_single_step # branch to do_sigtrap
364 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
365 # and after the system call
368 la %r2,SP_PTREGS(%r15) # load pt_regs
372 brasl %r14,do_syscall_trace_enter
376 sllg %r7,%r2,2 # svc number *4
379 lmg %r3,%r6,SP_R3(%r15)
380 lg %r2,SP_ORIG_R2(%r15)
381 basr %r14,%r8 # call sys_xxx
382 stg %r2,SP_R2(%r15) # store return value
384 tm __TI_flags+6(%r9),_TIF_SYSCALL
386 la %r2,SP_PTREGS(%r15) # load pt_regs
387 larl %r14,sysc_return # return point is sysc_return
388 jg do_syscall_trace_exit
391 # a new process exits the kernel with ret_from_fork
395 lg %r13,__LC_SVC_NEW_PSW+8
396 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
397 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
399 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
400 0: brasl %r14,schedule_tail
402 stosm 24(%r15),0x03 # reenable interrupts
406 # kernel_execve function needs to deal with pt_regs that is not
411 stmg %r12,%r15,96(%r15)
414 stg %r14,__SF_BACKCHAIN(%r15)
415 la %r12,SP_PTREGS(%r15)
416 xc 0(__PT_SIZE,%r12),0(%r12)
422 lmg %r12,%r15,96(%r15)
425 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
427 lg %r15,__LC_KERNEL_STACK # load ksp
428 aghi %r15,-SP_SIZE # make room for registers & psw
429 lg %r13,__LC_SVC_NEW_PSW+8
430 lg %r9,__LC_THREAD_INFO
431 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
432 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
434 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
435 brasl %r14,execve_tail
439 * Program check handler routine
442 .globl pgm_check_handler
445 * First we need to check for a special case:
446 * Single stepping an instruction that disables the PER event mask will
447 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
448 * For a single stepped SVC the program check handler gets control after
449 * the SVC new PSW has been loaded. But we want to execute the SVC first and
450 * then handle the PER event. Therefore we update the SVC old PSW to point
451 * to the pgm_check_handler and branch to the SVC handler after we checked
452 * if we have to load the kernel stack register.
453 * For every other possible cause for PER event without the PER mask set
454 * we just ignore the PER event (FIXME: is there anything we have to do
457 stpt __LC_SYNC_ENTER_TIMER
458 SAVE_ALL_BASE __LC_SAVE_AREA
459 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
460 jnz pgm_per # got per exception -> special case
461 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
462 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
463 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
465 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
466 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
467 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
470 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
471 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
472 lgf %r3,__LC_PGM_ILC # load program interruption code
477 larl %r1,pgm_check_table
478 lg %r1,0(%r8,%r1) # load address of handler routine
479 la %r2,SP_PTREGS(%r15) # address of register-save area
480 basr %r14,%r1 # branch to interrupt-handler
486 # handle per exception
489 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
490 jnz pgm_per_std # ok, normal per event from user space
491 # ok its one of the special cases, now we need to find out which one
492 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
494 # no interesting special case, ignore PER event
495 lmg %r12,%r15,__LC_SAVE_AREA
496 lpswe __LC_PGM_OLD_PSW
499 # Normal per exception
502 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
503 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
504 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
506 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
507 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
508 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
511 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
512 lg %r1,__TI_task(%r9)
513 tm SP_PSW+1(%r15),0x01 # kernel per event ?
515 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
516 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
517 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
518 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
519 lgf %r3,__LC_PGM_ILC # load program interruption code
521 ngr %r8,%r3 # clear per-event-bit and ilc
526 # it was a single stepped SVC that is causing all the trouble
529 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
530 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
531 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
532 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
533 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
534 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
535 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
537 lg %r8,__TI_task(%r9)
538 mvc __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID
539 mvc __THREAD_per+__PER_address(8,%r8),__LC_PER_ADDRESS
540 mvc __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
541 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
543 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
544 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
548 # per was called from kernel, must be kprobes
551 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
552 la %r2,SP_PTREGS(%r15) # address of register-save area
553 brasl %r14,do_single_step
557 * IO interrupt handler routine
559 .globl io_int_handler
562 stpt __LC_ASYNC_ENTER_TIMER
563 SAVE_ALL_BASE __LC_SAVE_AREA+32
564 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
565 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
566 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
568 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
569 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
570 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
572 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
574 la %r2,SP_PTREGS(%r15) # address of register-save area
575 brasl %r14,do_IRQ # call standard irq handler
580 tm __TI_flags+7(%r9),_TIF_WORK_INT
581 jnz io_work # there is work to do (signals etc.)
583 RESTORE_ALL __LC_RETURN_PSW,0
587 # There is work todo, find out in which context we have been interrupted:
588 # 1) if we return to user space we can do all _TIF_WORK_INT work
589 # 2) if we return to kernel code and kvm is enabled check if we need to
590 # modify the psw to leave SIE
591 # 3) if we return to kernel code and preemptive scheduling is enabled check
592 # the preemption counter and if it is zero call preempt_schedule_irq
593 # Before any work can be done, a switch to the kernel stack is required.
596 tm SP_PSW+1(%r15),0x01 # returning to user ?
597 jo io_work_user # yes -> do resched & signal
598 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
599 lg %r2,SP_PSW+8(%r15) # check if current instruction is SIE
601 chi %r1,-19948 # signed 16 bit compare with 0xb214
602 jne 0f # no -> leave PSW alone
603 aghi %r2,4 # yes-> add 4 bytes to leave SIE
604 stg %r2,SP_PSW+8(%r15)
607 #ifdef CONFIG_PREEMPT
608 # check for preemptive scheduling
609 icm %r0,15,__TI_precount(%r9)
610 jnz io_restore # preemption is disabled
611 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
613 # switch to kernel stack
616 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
617 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
619 # TRACE_IRQS_ON already done at io_return, call
620 # TRACE_IRQS_OFF to keep things symmetrical
622 brasl %r14,preempt_schedule_irq
629 # Need to do work before returning to userspace, switch to kernel stack
632 lg %r1,__LC_KERNEL_STACK
634 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
635 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
639 # One of the work bits is on. Find out which one.
640 # Checked are: _TIF_SIGPENDING, _TIF_NOTIFY_RESUME, _TIF_NEED_RESCHED
641 # and _TIF_MCCK_PENDING
644 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
646 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
648 tm __TI_flags+7(%r9),_TIF_SIGPENDING
650 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
652 j io_return # beware of critical section cleanup
655 # _TIF_MCCK_PENDING is set, call handler
658 # TRACE_IRQS_ON already done at io_return
659 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
664 # _TIF_NEED_RESCHED is set, call schedule
667 # TRACE_IRQS_ON already done at io_return
668 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
669 brasl %r14,schedule # call scheduler
670 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
675 # _TIF_SIGPENDING or is set, call do_signal
678 # TRACE_IRQS_ON already done at io_return
679 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
680 la %r2,SP_PTREGS(%r15) # load pt_regs
681 brasl %r14,do_signal # call do_signal
682 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
687 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
690 # TRACE_IRQS_ON already done at io_return
691 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
692 la %r2,SP_PTREGS(%r15) # load pt_regs
693 brasl %r14,do_notify_resume # call do_notify_resume
694 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
699 * External interrupt handler routine
701 .globl ext_int_handler
704 stpt __LC_ASYNC_ENTER_TIMER
705 SAVE_ALL_BASE __LC_SAVE_AREA+32
706 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
707 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
708 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
710 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
711 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
712 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
714 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
716 la %r2,SP_PTREGS(%r15) # address of register-save area
717 llgh %r3,__LC_EXT_INT_CODE # get interruption code
724 * Machine check handler routines
726 .globl mcck_int_handler
729 la %r1,4095 # revalidate r1
730 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
731 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
732 SAVE_ALL_BASE __LC_SAVE_AREA+64
733 la %r12,__LC_MCK_OLD_PSW
734 tm __LC_MCCK_CODE,0x80 # system damage?
735 jo mcck_int_main # yes -> rest of mcck code invalid
737 mvc __LC_MCCK_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
738 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
740 la %r14,__LC_SYNC_ENTER_TIMER
741 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
743 la %r14,__LC_ASYNC_ENTER_TIMER
744 0: clc 0(8,%r14),__LC_EXIT_TIMER
746 la %r14,__LC_EXIT_TIMER
747 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
749 la %r14,__LC_LAST_UPDATE_TIMER
751 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
752 1: tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
753 jno mcck_int_main # no -> skip cleanup critical
754 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
755 jnz mcck_int_main # from user -> load kernel stack
756 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
758 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
760 brasl %r14,cleanup_critical
762 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
764 srag %r14,%r14,PAGE_SHIFT
766 lg %r15,__LC_PANIC_STACK # load panic stack
767 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
768 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
769 jno mcck_no_vtime # no -> no timer update
770 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
772 UPDATE_VTIME __LC_EXIT_TIMER,__LC_MCCK_ENTER_TIMER,__LC_USER_TIMER
773 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
774 mvc __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER
776 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
777 la %r2,SP_PTREGS(%r15) # load pt_regs
778 brasl %r14,s390_do_machine_check
779 tm SP_PSW+1(%r15),0x01 # returning to user ?
781 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
783 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
784 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
786 stosm __SF_EMPTY(%r15),0x04 # turn dat on
787 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
790 brasl %r14,s390_handle_mcck
793 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
794 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
795 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
796 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
799 0: lpswe __LC_RETURN_MCCK_PSW # back to caller
802 * Restart interruption handler, kick starter for additional CPUs
806 .globl restart_int_handler
810 spt restart_vtime-restart_base(%r1)
811 stck __LC_LAST_UPDATE_CLOCK
812 mvc __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
813 mvc __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
814 lg %r15,__LC_SAVE_AREA+120 # load ksp
815 lghi %r10,__LC_CREGS_SAVE_AREA
816 lctlg %c0,%c15,0(%r10) # get new ctl regs
817 lghi %r10,__LC_AREGS_SAVE_AREA
819 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
820 lg %r1,__LC_THREAD_INFO
821 mvc __LC_USER_TIMER(8),__TI_user_timer(%r1)
822 mvc __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
823 xc __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
824 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
828 .long 0x7fffffff,0xffffffff
832 * If we do not run with SMP enabled, let the new CPU crash ...
834 .globl restart_int_handler
838 lpswe restart_crash-restart_base(%r1)
841 .long 0x000a0000,0x00000000,0x00000000,0x00000000
845 #ifdef CONFIG_CHECK_STACK
847 * The synchronous or the asynchronous stack overflowed. We are dead.
848 * No need to properly save the registers, we are going to panic anyway.
849 * Setup a pt_regs so that show_trace can provide a good call trace.
852 lg %r15,__LC_PANIC_STACK # change to panic stack
854 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
855 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
856 la %r1,__LC_SAVE_AREA
857 chi %r12,__LC_SVC_OLD_PSW
859 chi %r12,__LC_PGM_OLD_PSW
861 la %r1,__LC_SAVE_AREA+32
862 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
863 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
864 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
865 la %r2,SP_PTREGS(%r15) # load pt_regs
866 jg kernel_stack_overflow
869 cleanup_table_system_call:
870 .quad system_call, sysc_do_svc
871 cleanup_table_sysc_tif:
872 .quad sysc_tif, sysc_restore
873 cleanup_table_sysc_restore:
874 .quad sysc_restore, sysc_done
875 cleanup_table_io_tif:
876 .quad io_tif, io_restore
877 cleanup_table_io_restore:
878 .quad io_restore, io_done
881 clc 8(8,%r12),BASED(cleanup_table_system_call)
883 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
884 jl cleanup_system_call
886 clc 8(8,%r12),BASED(cleanup_table_sysc_tif)
888 clc 8(8,%r12),BASED(cleanup_table_sysc_tif+8)
891 clc 8(8,%r12),BASED(cleanup_table_sysc_restore)
893 clc 8(8,%r12),BASED(cleanup_table_sysc_restore+8)
894 jl cleanup_sysc_restore
896 clc 8(8,%r12),BASED(cleanup_table_io_tif)
898 clc 8(8,%r12),BASED(cleanup_table_io_tif+8)
901 clc 8(8,%r12),BASED(cleanup_table_io_restore)
903 clc 8(8,%r12),BASED(cleanup_table_io_restore+8)
904 jl cleanup_io_restore
909 mvc __LC_RETURN_PSW(16),0(%r12)
910 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
912 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
913 cghi %r12,__LC_MCK_OLD_PSW
915 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
916 0: cghi %r12,__LC_MCK_OLD_PSW
917 la %r12,__LC_SAVE_AREA+64
919 la %r12,__LC_SAVE_AREA+32
920 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
922 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
924 mvc __LC_SAVE_AREA(32),0(%r12)
926 stg %r12,__LC_SAVE_AREA+96 # argh
927 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
928 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
929 lg %r12,__LC_SAVE_AREA+96 # argh
931 llgh %r7,__LC_SVC_INT_CODE
933 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
935 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
937 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
939 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
941 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
942 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
943 la %r12,__LC_RETURN_PSW
945 cleanup_system_call_insn:
953 mvc __LC_RETURN_PSW(8),0(%r12)
954 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_tif)
955 la %r12,__LC_RETURN_PSW
958 cleanup_sysc_restore:
959 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn)
961 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn+8)
963 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
964 cghi %r12,__LC_MCK_OLD_PSW
966 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
967 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
968 cghi %r12,__LC_MCK_OLD_PSW
969 la %r12,__LC_SAVE_AREA+64
971 la %r12,__LC_SAVE_AREA+32
972 1: mvc 0(32,%r12),SP_R12(%r15)
973 lmg %r0,%r11,SP_R0(%r15)
975 2: la %r12,__LC_RETURN_PSW
977 cleanup_sysc_restore_insn:
982 mvc __LC_RETURN_PSW(8),0(%r12)
983 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_tif)
984 la %r12,__LC_RETURN_PSW
988 clc 8(8,%r12),BASED(cleanup_io_restore_insn)
990 clc 8(8,%r12),BASED(cleanup_io_restore_insn+8)
992 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
993 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
994 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
995 lmg %r0,%r11,SP_R0(%r15)
997 1: la %r12,__LC_RETURN_PSW
999 cleanup_io_restore_insn:
1008 .Lnr_syscalls: .long NR_syscalls
1009 .L0x0130: .short 0x130
1010 .L0x0140: .short 0x140
1011 .L0x0150: .short 0x150
1012 .L0x0160: .short 0x160
1013 .L0x0170: .short 0x170
1015 .quad __critical_start
1017 .quad __critical_end
1019 .section .rodata, "a"
1020 #define SYSCALL(esa,esame,emu) .long esame
1021 .globl sys_call_table
1023 #include "syscalls.S"
1026 #ifdef CONFIG_COMPAT
1028 #define SYSCALL(esa,esame,emu) .long emu
1030 #include "syscalls.S"