arch/ppc/syslib/mpc10x_common.c

   1 /*
   2  * arch/ppc/syslib/mpc10x_common.c
   3  *
   4  * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
   5  * Mem ctlr, EPIC, etc.
   6  *
   7  * Author: Mark A. Greer
   8  *         mgreer@mvista.com
   9  *
  10  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  11  * the terms of the GNU General Public License version 2.  This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15
  16 /*
  17  * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/pci.h>
  23 #include <linux/slab.h>
  24 #include <linux/serial_8250.h>
  25 #include <linux/fsl_devices.h>
  26 #include <linux/device.h>
  27
  28 #include <asm/byteorder.h>
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/machdep.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/open_pic.h>
  35 #include <asm/mpc10x.h>
  36 #include <asm/ppc_sys.h>
  37
  38 #ifdef CONFIG_MPC10X_OPENPIC
  39 #ifdef CONFIG_EPIC_SERIAL_MODE
  40 #define EPIC_IRQ_BASE (epic_serial_mode ? 16 : 5)
  41 #else
  42 #define EPIC_IRQ_BASE 5
  43 #endif
  44 #define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
  45 #define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
  46 #define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
  47 #else
  48 #define MPC10X_I2C_IRQ -1
  49 #define MPC10X_DMA0_IRQ -1
  50 #define MPC10X_DMA1_IRQ -1
  51 #endif
  52
  53 static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
  54         .device_flags           = 0,
  55 };
  56
  57 static struct plat_serial8250_port serial_platform_data[] = {
  58         { },
  59 };
  60
  61 struct platform_device ppc_sys_platform_devices[] = {
  62         [MPC10X_IIC1] = {
  63                 .name   = "fsl-i2c",
  64                 .id     = 1,
  65                 .dev.platform_data = &mpc10x_i2c_pdata,
  66                 .num_resources = 2,
  67                 .resource = (struct resource[]) {
  68                         {
  69                                 .start  = MPC10X_EUMB_I2C_OFFSET,
  70                                 .end    = MPC10X_EUMB_I2C_OFFSET +
  71                                             MPC10X_EUMB_I2C_SIZE - 1,
  72                                 .flags  = IORESOURCE_MEM,
  73                         },
  74                         {
  75                                 .flags  = IORESOURCE_IRQ
  76                         },
  77                 },
  78         },
  79         [MPC10X_DMA0] = {
  80                 .name   = "fsl-dma",
  81                 .id     = 0,
  82                 .num_resources = 2,
  83                 .resource = (struct resource[]) {
  84                         {
  85                                 .start  = MPC10X_EUMB_DMA_OFFSET + 0x10,
  86                                 .end    = MPC10X_EUMB_DMA_OFFSET + 0x1f,
  87                                 .flags  = IORESOURCE_MEM,
  88                         },
  89                         {
  90                                 .flags  = IORESOURCE_IRQ,
  91                         },
  92                 },
  93         },
  94         [MPC10X_DMA1] = {
  95                 .name   = "fsl-dma",
  96                 .id     = 1,
  97                 .num_resources = 2,
  98                 .resource = (struct resource[]) {
  99                         {
 100                                 .start  = MPC10X_EUMB_DMA_OFFSET + 0x20,
 101                                 .end    = MPC10X_EUMB_DMA_OFFSET + 0x2f,
 102                                 .flags  = IORESOURCE_MEM,
 103                         },
 104                         {
 105                                 .flags  = IORESOURCE_IRQ,
 106                         },
 107                 },
 108         },
 109         [MPC10X_DMA1] = {
 110                 .name   = "fsl-dma",
 111                 .id     = 1,
 112                 .num_resources = 2,
 113                 .resource = (struct resource[]) {
 114                         {
 115                                 .start  = MPC10X_EUMB_DMA_OFFSET + 0x20,
 116                                 .end    = MPC10X_EUMB_DMA_OFFSET + 0x2f,
 117                                 .flags  = IORESOURCE_MEM,
 118                         },
 119                         {
 120                                 .flags  = IORESOURCE_IRQ,
 121                         },
 122                 },
 123         },
 124         [MPC10X_DUART] = {
 125                 .name = "serial8250",
 126                 .id     = 0,
 127                 .dev.platform_data = serial_platform_data,
 128         },
 129 };
 130
 131 /* We use the PCI ID to match on */
 132 struct ppc_sys_spec *cur_ppc_sys_spec;
 133 struct ppc_sys_spec ppc_sys_specs[] = {
 134         {
 135                 .ppc_sys_name   = "8245",
 136                 .mask           = 0xFFFFFFFF,
 137                 .value          = MPC10X_BRIDGE_8245,
 138                 .num_devices    = 4,
 139                 .device_list    = (enum ppc_sys_devices[])
 140                 {
 141                         MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_DUART,
 142                 },
 143         },
 144         {
 145                 .ppc_sys_name   = "8240",
 146                 .mask           = 0xFFFFFFFF,
 147                 .value          = MPC10X_BRIDGE_8240,
 148                 .num_devices    = 3,
 149                 .device_list    = (enum ppc_sys_devices[])
 150                 {
 151                         MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
 152                 },
 153         },
 154         {
 155                 .ppc_sys_name   = "107",
 156                 .mask           = 0xFFFFFFFF,
 157                 .value          = MPC10X_BRIDGE_107,
 158                 .num_devices    = 3,
 159                 .device_list    = (enum ppc_sys_devices[])
 160                 {
 161                         MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
 162                 },
 163         },
 164         {       /* default match */
 165                 .ppc_sys_name   = "",
 166                 .mask           = 0x00000000,
 167                 .value          = 0x00000000,
 168         },
 169 };
 170
 171 /* Set resources to match bridge memory map */
 172 void __init
 173 mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
 174 {
 175
 176         switch (map) {
 177                 case MPC10X_MEM_MAP_A:
 178                         pci_init_resource(&hose->io_resource,
 179                                         0x00000000,
 180                                         0x3f7fffff,
 181                                         IORESOURCE_IO,
 182                                         "PCI host bridge");
 183
 184                         pci_init_resource (&hose->mem_resources[0],
 185                                         0xc0000000,
 186                                         0xfeffffff,
 187                                         IORESOURCE_MEM,
 188                                         "PCI host bridge");
 189                         break;
 190                 case MPC10X_MEM_MAP_B:
 191                         pci_init_resource(&hose->io_resource,
 192                                         0x00000000,
 193                                         0x00bfffff,
 194                                         IORESOURCE_IO,
 195                                         "PCI host bridge");
 196
 197                         pci_init_resource (&hose->mem_resources[0],
 198                                         0x80000000,
 199                                         0xfcffffff,
 200                                         IORESOURCE_MEM,
 201                                         "PCI host bridge");
 202                         break;
 203                 default:
 204                         printk("mpc10x_bridge_set_resources: "
 205                                         "Invalid map specified\n");
 206                         if (ppc_md.progress)
 207                                 ppc_md.progress("mpc10x:exit1", 0x100);
 208         }
 209 }
 210 /*
 211  * Do some initialization and put the EUMB registers at the specified address
 212  * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
 213  *
 214  * The EPIC is not on the 106, only the 8240 and 107.
 215  */
 216 int __init
 217 mpc10x_bridge_init(struct pci_controller *hose,
 218                    uint current_map,
 219                    uint new_map,
 220                    uint phys_eumb_base)
 221 {
 222         int     host_bridge, picr1, picr1_bit, i;
 223         ulong   pci_config_addr, pci_config_data;
 224         u_char  pir, byte;
 225
 226         if (ppc_md.progress) ppc_md.progress("mpc10x:enter", 0x100);
 227
 228         /* Set up for current map so we can get at config regs */
 229         switch (current_map) {
 230                 case MPC10X_MEM_MAP_A:
 231                         setup_indirect_pci(hose,
 232                                            MPC10X_MAPA_CNFG_ADDR,
 233                                            MPC10X_MAPA_CNFG_DATA);
 234                         break;
 235                 case MPC10X_MEM_MAP_B:
 236                         setup_indirect_pci(hose,
 237                                            MPC10X_MAPB_CNFG_ADDR,
 238                                            MPC10X_MAPB_CNFG_DATA);
 239                         break;
 240                 default:
 241                         printk("mpc10x_bridge_init: %s\n",
 242                                 "Invalid current map specified");
 243                         if (ppc_md.progress)
 244                                 ppc_md.progress("mpc10x:exit1", 0x100);
 245                         return -1;
 246         }
 247
 248         /* Make sure it's a supported bridge */
 249         early_read_config_dword(hose,
 250                                 0,
 251                                 PCI_DEVFN(0,0),
 252                                 PCI_VENDOR_ID,
 253                                 &host_bridge);
 254
 255         switch (host_bridge) {
 256                 case MPC10X_BRIDGE_106:
 257                 case MPC10X_BRIDGE_8240:
 258                 case MPC10X_BRIDGE_107:
 259                 case MPC10X_BRIDGE_8245:
 260                         break;
 261                 default:
 262                         if (ppc_md.progress)
 263                                 ppc_md.progress("mpc10x:exit2", 0x100);
 264                         return -1;
 265         }
 266
 267         switch (new_map) {
 268                 case MPC10X_MEM_MAP_A:
 269                         MPC10X_SETUP_HOSE(hose, A);
 270                         pci_config_addr = MPC10X_MAPA_CNFG_ADDR;
 271                         pci_config_data = MPC10X_MAPA_CNFG_DATA;
 272                         picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_A;
 273                         break;
 274                 case MPC10X_MEM_MAP_B:
 275                         MPC10X_SETUP_HOSE(hose, B);
 276                         pci_config_addr = MPC10X_MAPB_CNFG_ADDR;
 277                         pci_config_data = MPC10X_MAPB_CNFG_DATA;
 278                         picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_B;
 279                         break;
 280                 default:
 281                         printk("mpc10x_bridge_init: %s\n",
 282                                 "Invalid new map specified");
 283                         if (ppc_md.progress)
 284                                 ppc_md.progress("mpc10x:exit3", 0x100);
 285                         return -1;
 286         }
 287
 288         /* Make bridge use the 'new_map', if not already usng it */
 289         if (current_map != new_map) {
 290                 early_read_config_dword(hose,
 291                                         0,
 292                                         PCI_DEVFN(0,0),
 293                                         MPC10X_CFG_PICR1_REG,
 294                                         &picr1);
 295
 296                 picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) |
 297                          picr1_bit;
 298
 299                 early_write_config_dword(hose,
 300                                          0,
 301                                          PCI_DEVFN(0,0),
 302                                          MPC10X_CFG_PICR1_REG,
 303                                          picr1);
 304
 305                 asm volatile("sync");
 306
 307                 /* Undo old mappings & map in new cfg data/addr regs */
 308                 iounmap((void *)hose->cfg_addr);
 309                 iounmap((void *)hose->cfg_data);
 310
 311                 setup_indirect_pci(hose,
 312                                    pci_config_addr,
 313                                    pci_config_data);
 314         }
 315
 316         /* Setup resources to match map */
 317         mpc10x_bridge_set_resources(new_map, hose);
 318
 319         /*
 320          * Want processor accesses of 0xFDxxxxxx to be mapped
 321          * to PCI memory space at 0x00000000.  Do not want
 322          * host bridge to respond to PCI memory accesses of
 323          * 0xFDxxxxxx.  Do not want host bridge to respond
 324          * to PCI memory addresses 0xFD000000-0xFDFFFFFF;
 325          * want processor accesses from 0x000A0000-0x000BFFFF
 326          * to be forwarded to system memory.
 327          *
 328          * Only valid if not in agent mode and using MAP B.
 329          */
 330         if (new_map == MPC10X_MEM_MAP_B) {
 331                 early_read_config_byte(hose,
 332                                        0,
 333                                        PCI_DEVFN(0,0),
 334                                        MPC10X_CFG_MAPB_OPTIONS_REG,
 335                                        &byte);
 336
 337                 byte &= ~(MPC10X_CFG_MAPB_OPTIONS_PFAE  |
 338                           MPC10X_CFG_MAPB_OPTIONS_PCICH |
 339                           MPC10X_CFG_MAPB_OPTIONS_PROCCH);
 340
 341                 if (host_bridge != MPC10X_BRIDGE_106) {
 342                         byte |= MPC10X_CFG_MAPB_OPTIONS_CFAE;
 343                 }
 344
 345                 early_write_config_byte(hose,
 346                                         0,
 347                                         PCI_DEVFN(0,0),
 348                                         MPC10X_CFG_MAPB_OPTIONS_REG,
 349                                         byte);
 350         }
 351
 352         if (host_bridge != MPC10X_BRIDGE_106) {
 353                 early_read_config_byte(hose,
 354                                        0,
 355                                        PCI_DEVFN(0,0),
 356                                        MPC10X_CFG_PIR_REG,
 357                                        &pir);
 358
 359                 if (pir != MPC10X_CFG_PIR_HOST_BRIDGE) {
 360                         printk("Host bridge in Agent mode\n");
 361                         /* Read or Set LMBAR & PCSRBAR? */
 362                 }
 363
 364                 /* Set base addr of the 8240/107 EUMB.  */
 365                 early_write_config_dword(hose,
 366                                          0,
 367                                          PCI_DEVFN(0,0),
 368                                          MPC10X_CFG_EUMBBAR,
 369                                          phys_eumb_base);
 370 #ifdef CONFIG_MPC10X_OPENPIC
 371                 /* Map EPIC register part of EUMB into vitual memory  - PCORE
 372                    uses an i8259 instead of EPIC. */
 373                 OpenPIC_Addr =
 374                         ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,
 375                                 MPC10X_EUMB_EPIC_SIZE);
 376 #endif
 377         }
 378
 379 #ifdef CONFIG_MPC10X_STORE_GATHERING
 380         mpc10x_enable_store_gathering(hose);
 381 #else
 382         mpc10x_disable_store_gathering(hose);
 383 #endif
 384
 385         /* setup platform devices for MPC10x bridges */
 386         identify_ppc_sys_by_id (host_bridge);
 387
 388         for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) {
 389                 unsigned int dev_id = cur_ppc_sys_spec->device_list[i];
 390                 ppc_sys_fixup_mem_resource(&ppc_sys_platform_devices[dev_id],
 391                         phys_eumb_base);
 392         }
 393
 394         /* IRQ's are determined at runtime */
 395         ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ;
 396         ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ;
 397         ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ;
 398         ppc_sys_platform_devices[MPC10X_DMA0].resource[1].end = MPC10X_DMA0_IRQ;
 399         ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ;
 400         ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ;
 401
 402         /*
 403          * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative
 404          * PCI reads may return stale data so turn off.
 405          */
 406         if ((host_bridge == MPC10X_BRIDGE_8240)
 407                 || (host_bridge == MPC10X_BRIDGE_8245)
 408                 || (host_bridge == MPC10X_BRIDGE_107)) {
 409
 410                 early_read_config_dword(hose, 0, PCI_DEVFN(0,0),
 411                         MPC10X_CFG_PICR1_REG, &picr1);
 412
 413                 picr1 &= ~MPC10X_CFG_PICR1_SPEC_PCI_RD;
 414
 415                 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
 416                         MPC10X_CFG_PICR1_REG, picr1);
 417         }
 418
 419         /*
 420          * 8241/8245 erratum 28: PCI reads from local memory may return
 421          * stale data.  Workaround by setting PICR2[0] to disable copyback
 422          * optimization.  Oddly, the latest available user manual for the
 423          * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd.
 424          */
 425         if (host_bridge == MPC10X_BRIDGE_8245) {
 426                 u32     picr2;
 427
 428                 early_read_config_dword(hose, 0, PCI_DEVFN(0,0),
 429                         MPC10X_CFG_PICR2_REG, &picr2);
 430
 431                 picr2 |= MPC10X_CFG_PICR2_COPYBACK_OPT;
 432
 433                 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
 434                          MPC10X_CFG_PICR2_REG, picr2);
 435         }
 436
 437         if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100);
 438         return 0;
 439 }
 440
 441 /*
 442  * Need to make our own PCI config space access macros because
 443  * mpc10x_get_mem_size() is called before the data structures are set up for
 444  * the 'early_xxx' and 'indirect_xxx' routines to work.
 445  * Assumes bus 0.
 446  */
 447 #define MPC10X_CFG_read(val, addr, type, op)    *val = op((type)(addr))
 448 #define MPC10X_CFG_write(val, addr, type, op)   op((type *)(addr), (val))
 449
 450 #define MPC10X_PCI_OP(rw, size, type, op, mask)                         \
 451 static void                                                             \
 452 mpc10x_##rw##_config_##size(uint *cfg_addr, uint *cfg_data, int devfn, int offset, type val) \
 453 {                                                                       \
 454         out_be32(cfg_addr,                                              \
 455                  ((offset & 0xfc) << 24) | (devfn << 16)                \
 456                  | (0 << 8) | 0x80);                                    \
 457         MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op);     \
 458         return;                                                         \
 459 }
 460
 461 MPC10X_PCI_OP(read,  byte,  u8 *, in_8, 3)
 462 MPC10X_PCI_OP(read,  dword, u32 *, in_le32, 0)
 463 #if 0   /* Not used */
 464 MPC10X_PCI_OP(write, byte,  u8, out_8, 3)
 465 MPC10X_PCI_OP(read,  word,  u16 *, in_le16, 2)
 466 MPC10X_PCI_OP(write, word,  u16, out_le16, 2)
 467 MPC10X_PCI_OP(write, dword, u32, out_le32, 0)
 468 #endif
 469
 470 /*
 471  * Read the memory controller registers to determine the amount of memory in
 472  * the system.  This assumes that the firmware has correctly set up the memory
 473  * controller registers.
 474  */
 475 unsigned long __init
 476 mpc10x_get_mem_size(uint mem_map)
 477 {
 478         uint                    *config_addr, *config_data, val;
 479         ulong                   start, end, total, offset;
 480         int                     i;
 481         u_char                  bank_enables;
 482
 483         switch (mem_map) {
 484                 case MPC10X_MEM_MAP_A:
 485                         config_addr = (uint *)MPC10X_MAPA_CNFG_ADDR;
 486                         config_data = (uint *)MPC10X_MAPA_CNFG_DATA;
 487                         break;
 488                 case MPC10X_MEM_MAP_B:
 489                         config_addr = (uint *)MPC10X_MAPB_CNFG_ADDR;
 490                         config_data = (uint *)MPC10X_MAPB_CNFG_DATA;
 491                         break;
 492                 default:
 493                         return 0;
 494         }
 495
 496         mpc10x_read_config_byte(config_addr,
 497                                 config_data,
 498                                 PCI_DEVFN(0,0),
 499                                 MPC10X_MCTLR_MEM_BANK_ENABLES,
 500                                 &bank_enables);
 501
 502         total = 0;
 503
 504         for (i=0; i<8; i++) {
 505                 if (bank_enables & (1 << i)) {
 506                         offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0);
 507                         mpc10x_read_config_dword(config_addr,
 508                                                  config_data,
 509                                                  PCI_DEVFN(0,0),
 510                                                  offset,
 511                                                  &val);
 512                         start = (val >> ((i & 3) << 3)) & 0xff;
 513
 514                         offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0);
 515                         mpc10x_read_config_dword(config_addr,
 516                                                  config_data,
 517                                                  PCI_DEVFN(0,0),
 518                                                  offset,
 519                                                  &val);
 520                         val = (val >> ((i & 3) << 3)) & 0x03;
 521                         start = (val << 28) | (start << 20);
 522
 523                         offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0);
 524                         mpc10x_read_config_dword(config_addr,
 525                                                  config_data,
 526                                                  PCI_DEVFN(0,0),
 527                                                  offset,
 528                                                  &val);
 529                         end = (val >> ((i & 3) << 3)) & 0xff;
 530
 531                         offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0);
 532                         mpc10x_read_config_dword(config_addr,
 533                                                  config_data,
 534                                                  PCI_DEVFN(0,0),
 535                                                  offset,
 536                                                  &val);
 537                         val = (val >> ((i & 3) << 3)) & 0x03;
 538                         end = (val << 28) | (end << 20) | 0xfffff;
 539
 540                         total += (end - start + 1);
 541                 }
 542         }
 543
 544         return total;
 545 }
 546
 547 int __init
 548 mpc10x_enable_store_gathering(struct pci_controller *hose)
 549 {
 550         uint picr1;
 551
 552         early_read_config_dword(hose,
 553                                 0,
 554                                 PCI_DEVFN(0,0),
 555                                 MPC10X_CFG_PICR1_REG,
 556                                 &picr1);
 557
 558         picr1 |= MPC10X_CFG_PICR1_ST_GATH_EN;
 559
 560         early_write_config_dword(hose,
 561                                 0,
 562                                 PCI_DEVFN(0,0),
 563                                 MPC10X_CFG_PICR1_REG,
 564                                 picr1);
 565
 566         return 0;
 567 }
 568
 569 int __init
 570 mpc10x_disable_store_gathering(struct pci_controller *hose)
 571 {
 572         uint picr1;
 573
 574         early_read_config_dword(hose,
 575                                 0,
 576                                 PCI_DEVFN(0,0),
 577                                 MPC10X_CFG_PICR1_REG,
 578                                 &picr1);
 579
 580         picr1 &= ~MPC10X_CFG_PICR1_ST_GATH_EN;
 581
 582         early_write_config_dword(hose,
 583                                 0,
 584                                 PCI_DEVFN(0,0),
 585                                 MPC10X_CFG_PICR1_REG,
 586                                 picr1);
 587
 588         return 0;
 589 }
 590
 591 #ifdef CONFIG_MPC10X_OPENPIC
 592 void __init mpc10x_set_openpic(void)
 593 {
 594         /* Map external IRQs */
 595         openpic_set_sources(0, EPIC_IRQ_BASE, OpenPIC_Addr + 0x10200);
 596         /* Skip reserved space and map i2c and DMA Ch[01] */
 597         openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020);
 598         /* Skip reserved space and map Message Unit Interrupt (I2O) */
 599         openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0);
 600
 601         openpic_init(NUM_8259_INTERRUPTS);
 602 }
 603 #endif