2 * Freescale MPC85xx/MPC86xx RapidIO support
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
13 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/rio.h>
32 #include <linux/rio_drv.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/kfifo.h>
39 #include <asm/machdep.h>
40 #include <asm/uaccess.h>
42 #undef DEBUG_PW /* Port-Write debugging */
44 /* RapidIO definition irq, which read from OF-tree */
45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
50 #define RIO_ATMU_REGS_OFFSET 0x10c00
51 #define RIO_P_MSG_REGS_OFFSET 0x11000
52 #define RIO_S_MSG_REGS_OFFSET 0x13000
53 #define RIO_ESCSR 0x158
54 #define RIO_CCSR 0x15c
55 #define RIO_LTLEDCSR 0x0608
56 #define RIO_LTLEDCSR_IER 0x80000000
57 #define RIO_LTLEDCSR_PRT 0x01000000
58 #define RIO_LTLEECSR 0x060c
59 #define RIO_EPWISR 0x10010
60 #define RIO_ISR_AACR 0x10120
61 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
62 #define RIO_MAINT_WIN_SIZE 0x400000
63 #define RIO_DBELL_WIN_SIZE 0x1000
65 #define RIO_MSG_OMR_MUI 0x00000002
66 #define RIO_MSG_OSR_TE 0x00000080
67 #define RIO_MSG_OSR_QOI 0x00000020
68 #define RIO_MSG_OSR_QFI 0x00000010
69 #define RIO_MSG_OSR_MUB 0x00000004
70 #define RIO_MSG_OSR_EOMI 0x00000002
71 #define RIO_MSG_OSR_QEI 0x00000001
73 #define RIO_MSG_IMR_MI 0x00000002
74 #define RIO_MSG_ISR_TE 0x00000080
75 #define RIO_MSG_ISR_QFI 0x00000010
76 #define RIO_MSG_ISR_DIQI 0x00000001
78 #define RIO_IPWMR_SEN 0x00100000
79 #define RIO_IPWMR_QFIE 0x00000100
80 #define RIO_IPWMR_EIE 0x00000020
81 #define RIO_IPWMR_CQ 0x00000002
82 #define RIO_IPWMR_PWE 0x00000001
84 #define RIO_IPWSR_QF 0x00100000
85 #define RIO_IPWSR_TE 0x00000080
86 #define RIO_IPWSR_QFI 0x00000010
87 #define RIO_IPWSR_PWD 0x00000008
88 #define RIO_IPWSR_PWB 0x00000004
90 #define RIO_EPWISR_PINT 0x80000000
91 #define RIO_EPWISR_PW 0x00000001
93 #define RIO_MSG_DESC_SIZE 32
94 #define RIO_MSG_BUFFER_SIZE 4096
95 #define RIO_MIN_TX_RING_SIZE 2
96 #define RIO_MAX_TX_RING_SIZE 2048
97 #define RIO_MIN_RX_RING_SIZE 2
98 #define RIO_MAX_RX_RING_SIZE 2048
100 #define DOORBELL_DMR_DI 0x00000002
101 #define DOORBELL_DSR_TE 0x00000080
102 #define DOORBELL_DSR_QFI 0x00000010
103 #define DOORBELL_DSR_DIQI 0x00000001
104 #define DOORBELL_TID_OFFSET 0x02
105 #define DOORBELL_SID_OFFSET 0x04
106 #define DOORBELL_INFO_OFFSET 0x06
108 #define DOORBELL_MESSAGE_SIZE 0x08
109 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
110 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
111 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
113 struct rio_atmu_regs {
122 struct rio_msg_regs {
123 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
124 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
126 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
127 dequeue pointer address register */
129 u32 osar; /* 0xD_3014 - Outbound message 0 source address
131 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
133 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
135 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
138 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
139 enqueue pointer address register */
141 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
142 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
144 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
145 pointer address register*/
147 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
148 pointer address register */
150 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
151 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
153 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
155 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
158 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
159 configuration register */
161 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
162 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
164 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
167 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
170 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
171 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
172 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
174 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
189 struct rio_dbell_ring {
194 struct rio_msg_tx_ring {
197 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
198 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
204 struct rio_msg_rx_ring {
207 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
213 struct rio_port_write_msg {
223 void __iomem *regs_win;
224 struct rio_atmu_regs __iomem *atmu_regs;
225 struct rio_atmu_regs __iomem *maint_atmu_regs;
226 struct rio_atmu_regs __iomem *dbell_atmu_regs;
227 void __iomem *dbell_win;
228 void __iomem *maint_win;
229 struct rio_msg_regs __iomem *msg_regs;
230 struct rio_dbell_ring dbell_ring;
231 struct rio_msg_tx_ring msg_tx_ring;
232 struct rio_msg_rx_ring msg_rx_ring;
233 struct rio_port_write_msg port_write_msg;
238 struct work_struct pw_work;
239 struct kfifo pw_fifo;
240 spinlock_t pw_fifo_lock;
243 #define __fsl_read_rio_config(x, addr, err, op) \
244 __asm__ __volatile__( \
245 "1: "op" %1,0(%2)\n" \
248 ".section .fixup,\"ax\"\n" \
252 ".section __ex_table,\"a\"\n" \
256 : "=r" (err), "=r" (x) \
257 : "b" (addr), "i" (-EFAULT), "0" (err))
259 static void __iomem *rio_regs_win;
262 static int (*saved_mcheck_exception)(struct pt_regs *regs);
264 static int fsl_rio_mcheck_exception(struct pt_regs *regs)
266 const struct exception_table_entry *entry = NULL;
267 unsigned long reason = mfspr(SPRN_MCSR);
269 if (reason & MCSR_BUS_RBERR) {
270 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
271 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
272 /* Check if we are prepared to handle this fault */
273 entry = search_exception_tables(regs->nip);
275 pr_debug("RIO: %s - MC Exception handled\n",
277 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
280 regs->nip = entry->fixup;
286 if (saved_mcheck_exception)
287 return saved_mcheck_exception(regs);
289 return cur_cpu_spec->machine_check(regs);
294 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
295 * @mport: RapidIO master port info
296 * @index: ID of RapidIO interface
297 * @destid: Destination ID of target device
298 * @data: 16-bit info field of RapidIO doorbell message
300 * Sends a MPC85xx doorbell message. Returns %0 on success or
301 * %-EINVAL on failure.
303 static int fsl_rio_doorbell_send(struct rio_mport *mport,
304 int index, u16 destid, u16 data)
306 struct rio_priv *priv = mport->priv;
307 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
308 index, destid, data);
309 switch (mport->phy_type) {
310 case RIO_PHY_PARALLEL:
311 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
312 out_be16(priv->dbell_win, data);
315 /* In the serial version silicons, such as MPC8548, MPC8641,
316 * below operations is must be.
318 out_be32(&priv->msg_regs->odmr, 0x00000000);
319 out_be32(&priv->msg_regs->odretcr, 0x00000004);
320 out_be32(&priv->msg_regs->oddpr, destid << 16);
321 out_be32(&priv->msg_regs->oddatr, data);
322 out_be32(&priv->msg_regs->odmr, 0x00000001);
330 * fsl_local_config_read - Generate a MPC85xx local config space read
331 * @mport: RapidIO master port info
332 * @index: ID of RapdiIO interface
333 * @offset: Offset into configuration space
334 * @len: Length (in bytes) of the maintenance transaction
335 * @data: Value to be read into
337 * Generates a MPC85xx local configuration space read. Returns %0 on
338 * success or %-EINVAL on failure.
340 static int fsl_local_config_read(struct rio_mport *mport,
341 int index, u32 offset, int len, u32 *data)
343 struct rio_priv *priv = mport->priv;
344 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
346 *data = in_be32(priv->regs_win + offset);
352 * fsl_local_config_write - Generate a MPC85xx local config space write
353 * @mport: RapidIO master port info
354 * @index: ID of RapdiIO interface
355 * @offset: Offset into configuration space
356 * @len: Length (in bytes) of the maintenance transaction
357 * @data: Value to be written
359 * Generates a MPC85xx local configuration space write. Returns %0 on
360 * success or %-EINVAL on failure.
362 static int fsl_local_config_write(struct rio_mport *mport,
363 int index, u32 offset, int len, u32 data)
365 struct rio_priv *priv = mport->priv;
367 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
368 index, offset, data);
369 out_be32(priv->regs_win + offset, data);
375 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
376 * @mport: RapidIO master port info
377 * @index: ID of RapdiIO interface
378 * @destid: Destination ID of transaction
379 * @hopcount: Number of hops to target device
380 * @offset: Offset into configuration space
381 * @len: Length (in bytes) of the maintenance transaction
382 * @val: Location to be read into
384 * Generates a MPC85xx read maintenance transaction. Returns %0 on
385 * success or %-EINVAL on failure.
388 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
389 u8 hopcount, u32 offset, int len, u32 *val)
391 struct rio_priv *priv = mport->priv;
396 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
397 index, destid, hopcount, offset, len);
399 /* 16MB maintenance window possible */
400 /* allow only aligned access to maintenance registers */
401 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
404 out_be32(&priv->maint_atmu_regs->rowtar,
405 (destid << 22) | (hopcount << 12) | (offset >> 12));
406 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
408 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
411 __fsl_read_rio_config(rval, data, err, "lbz");
414 __fsl_read_rio_config(rval, data, err, "lhz");
417 __fsl_read_rio_config(rval, data, err, "lwz");
424 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
425 err, destid, hopcount, offset);
434 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
435 * @mport: RapidIO master port info
436 * @index: ID of RapdiIO interface
437 * @destid: Destination ID of transaction
438 * @hopcount: Number of hops to target device
439 * @offset: Offset into configuration space
440 * @len: Length (in bytes) of the maintenance transaction
441 * @val: Value to be written
443 * Generates an MPC85xx write maintenance transaction. Returns %0 on
444 * success or %-EINVAL on failure.
447 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
448 u8 hopcount, u32 offset, int len, u32 val)
450 struct rio_priv *priv = mport->priv;
453 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
454 index, destid, hopcount, offset, len, val);
456 /* 16MB maintenance windows possible */
457 /* allow only aligned access to maintenance registers */
458 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
461 out_be32(&priv->maint_atmu_regs->rowtar,
462 (destid << 22) | (hopcount << 12) | (offset >> 12));
463 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
465 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
468 out_8((u8 *) data, val);
471 out_be16((u16 *) data, val);
474 out_be32((u32 *) data, val);
484 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
485 * @mport: Master port with outbound message queue
486 * @rdev: Target of outbound message
487 * @mbox: Outbound mailbox
488 * @buffer: Message to add to outbound queue
489 * @len: Length of message
491 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
492 * %0 on success or %-EINVAL on failure.
495 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
496 void *buffer, size_t len)
498 struct rio_priv *priv = mport->priv;
500 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
501 + priv->msg_tx_ring.tx_slot;
505 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
506 rdev->destid, mbox, (int)buffer, len);
508 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
513 /* Copy and clear rest of buffer */
514 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
516 if (len < (RIO_MAX_MSG_SIZE - 4))
517 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
518 + len, 0, RIO_MAX_MSG_SIZE - len);
520 switch (mport->phy_type) {
521 case RIO_PHY_PARALLEL:
522 /* Set mbox field for message */
523 desc->dport = mbox & 0x3;
525 /* Enable EOMI interrupt, set priority, and set destid */
526 desc->dattr = 0x28000000 | (rdev->destid << 2);
529 /* Set mbox field for message, and set destid */
530 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
532 /* Enable EOMI interrupt and priority */
533 desc->dattr = 0x28000000;
537 /* Set transfer size aligned to next power of 2 (in double words) */
538 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
540 /* Set snooping and source buffer address */
541 desc->saddr = 0x00000004
542 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
544 /* Increment enqueue pointer */
545 omr = in_be32(&priv->msg_regs->omr);
546 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
548 /* Go to next descriptor */
549 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
550 priv->msg_tx_ring.tx_slot = 0;
556 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
559 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
560 * @irq: Linux interrupt number
561 * @dev_instance: Pointer to interrupt-specific data
563 * Handles outbound message interrupts. Executes a register outbound
564 * mailbox event handler and acks the interrupt occurrence.
567 fsl_rio_tx_handler(int irq, void *dev_instance)
570 struct rio_mport *port = (struct rio_mport *)dev_instance;
571 struct rio_priv *priv = port->priv;
573 osr = in_be32(&priv->msg_regs->osr);
575 if (osr & RIO_MSG_OSR_TE) {
576 pr_info("RIO: outbound message transmission error\n");
577 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
581 if (osr & RIO_MSG_OSR_QOI) {
582 pr_info("RIO: outbound message queue overflow\n");
583 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
587 if (osr & RIO_MSG_OSR_EOMI) {
588 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
589 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
590 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
593 /* Ack the end-of-message interrupt */
594 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
602 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
603 * @mport: Master port implementing the outbound message unit
604 * @dev_id: Device specific pointer to pass on event
605 * @mbox: Mailbox to open
606 * @entries: Number of entries in the outbound mailbox ring
608 * Initializes buffer ring, request the outbound message interrupt,
609 * and enables the outbound message unit. Returns %0 on success and
610 * %-EINVAL or %-ENOMEM on failure.
612 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
615 struct rio_priv *priv = mport->priv;
617 if ((entries < RIO_MIN_TX_RING_SIZE) ||
618 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
623 /* Initialize shadow copy ring */
624 priv->msg_tx_ring.dev_id = dev_id;
625 priv->msg_tx_ring.size = entries;
627 for (i = 0; i < priv->msg_tx_ring.size; i++) {
628 priv->msg_tx_ring.virt_buffer[i] =
629 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
630 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
631 if (!priv->msg_tx_ring.virt_buffer[i]) {
633 for (j = 0; j < priv->msg_tx_ring.size; j++)
634 if (priv->msg_tx_ring.virt_buffer[j])
635 dma_free_coherent(priv->dev,
645 /* Initialize outbound message descriptor ring */
646 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
647 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
648 &priv->msg_tx_ring.phys, GFP_KERNEL);
649 if (!priv->msg_tx_ring.virt) {
653 memset(priv->msg_tx_ring.virt, 0,
654 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
655 priv->msg_tx_ring.tx_slot = 0;
657 /* Point dequeue/enqueue pointers at first entry in ring */
658 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
659 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
661 /* Configure for snooping */
662 out_be32(&priv->msg_regs->osar, 0x00000004);
664 /* Clear interrupt status */
665 out_be32(&priv->msg_regs->osr, 0x000000b3);
667 /* Hook up outbound message handler */
668 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
669 "msg_tx", (void *)mport);
674 * Configure outbound message unit
676 * Interrupts (all enabled, except QEIE)
680 out_be32(&priv->msg_regs->omr, 0x00100220);
682 /* Set number of entries */
683 out_be32(&priv->msg_regs->omr,
684 in_be32(&priv->msg_regs->omr) |
685 ((get_bitmask_order(entries) - 2) << 12));
687 /* Now enable the unit */
688 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
694 dma_free_coherent(priv->dev,
695 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
696 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
699 for (i = 0; i < priv->msg_tx_ring.size; i++)
700 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
701 priv->msg_tx_ring.virt_buffer[i],
702 priv->msg_tx_ring.phys_buffer[i]);
708 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
709 * @mport: Master port implementing the outbound message unit
710 * @mbox: Mailbox to close
712 * Disables the outbound message unit, free all buffers, and
713 * frees the outbound message interrupt.
715 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
717 struct rio_priv *priv = mport->priv;
718 /* Disable inbound message unit */
719 out_be32(&priv->msg_regs->omr, 0);
722 dma_free_coherent(priv->dev,
723 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
724 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
727 free_irq(IRQ_RIO_TX(mport), (void *)mport);
731 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
732 * @irq: Linux interrupt number
733 * @dev_instance: Pointer to interrupt-specific data
735 * Handles inbound message interrupts. Executes a registered inbound
736 * mailbox event handler and acks the interrupt occurrence.
739 fsl_rio_rx_handler(int irq, void *dev_instance)
742 struct rio_mport *port = (struct rio_mport *)dev_instance;
743 struct rio_priv *priv = port->priv;
745 isr = in_be32(&priv->msg_regs->isr);
747 if (isr & RIO_MSG_ISR_TE) {
748 pr_info("RIO: inbound message reception error\n");
749 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
753 /* XXX Need to check/dispatch until queue empty */
754 if (isr & RIO_MSG_ISR_DIQI) {
756 * We implement *only* mailbox 0, but can receive messages
757 * for any mailbox/letter to that mailbox destination. So,
758 * make the callback with an unknown/invalid mailbox number
761 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
763 /* Ack the queueing interrupt */
764 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
772 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
773 * @mport: Master port implementing the inbound message unit
774 * @dev_id: Device specific pointer to pass on event
775 * @mbox: Mailbox to open
776 * @entries: Number of entries in the inbound mailbox ring
778 * Initializes buffer ring, request the inbound message interrupt,
779 * and enables the inbound message unit. Returns %0 on success
780 * and %-EINVAL or %-ENOMEM on failure.
782 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
785 struct rio_priv *priv = mport->priv;
787 if ((entries < RIO_MIN_RX_RING_SIZE) ||
788 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
793 /* Initialize client buffer ring */
794 priv->msg_rx_ring.dev_id = dev_id;
795 priv->msg_rx_ring.size = entries;
796 priv->msg_rx_ring.rx_slot = 0;
797 for (i = 0; i < priv->msg_rx_ring.size; i++)
798 priv->msg_rx_ring.virt_buffer[i] = NULL;
800 /* Initialize inbound message ring */
801 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
802 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
803 &priv->msg_rx_ring.phys, GFP_KERNEL);
804 if (!priv->msg_rx_ring.virt) {
809 /* Point dequeue/enqueue pointers at first entry in ring */
810 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
811 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
813 /* Clear interrupt status */
814 out_be32(&priv->msg_regs->isr, 0x00000091);
816 /* Hook up inbound message handler */
817 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
818 "msg_rx", (void *)mport);
820 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
821 priv->msg_tx_ring.virt_buffer[i],
822 priv->msg_tx_ring.phys_buffer[i]);
827 * Configure inbound message unit:
829 * 4KB max message size
830 * Unmask all interrupt sources
833 out_be32(&priv->msg_regs->imr, 0x001b0060);
835 /* Set number of queue entries */
836 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
838 /* Now enable the unit */
839 setbits32(&priv->msg_regs->imr, 0x1);
846 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
847 * @mport: Master port implementing the inbound message unit
848 * @mbox: Mailbox to close
850 * Disables the inbound message unit, free all buffers, and
851 * frees the inbound message interrupt.
853 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
855 struct rio_priv *priv = mport->priv;
856 /* Disable inbound message unit */
857 out_be32(&priv->msg_regs->imr, 0);
860 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
861 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
864 free_irq(IRQ_RIO_RX(mport), (void *)mport);
868 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
869 * @mport: Master port implementing the inbound message unit
870 * @mbox: Inbound mailbox number
871 * @buf: Buffer to add to inbound queue
873 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
874 * %0 on success or %-EINVAL on failure.
876 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
879 struct rio_priv *priv = mport->priv;
881 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
882 priv->msg_rx_ring.rx_slot);
884 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
886 "RIO: error adding inbound buffer %d, buffer exists\n",
887 priv->msg_rx_ring.rx_slot);
892 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
893 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
894 priv->msg_rx_ring.rx_slot = 0;
900 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
903 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
904 * @mport: Master port implementing the inbound message unit
905 * @mbox: Inbound mailbox number
907 * Gets the next available inbound message from the inbound message queue.
908 * A pointer to the message is returned on success or NULL on failure.
910 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
912 struct rio_priv *priv = mport->priv;
913 u32 phys_buf, virt_buf;
917 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
919 /* If no more messages, then bail out */
920 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
923 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
924 - priv->msg_rx_ring.phys);
925 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
926 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
930 "RIO: inbound message copy failed, no buffers\n");
934 /* Copy max message size, caller is expected to allocate that big */
935 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
937 /* Clear the available buffer */
938 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
941 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
947 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
950 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
951 * @irq: Linux interrupt number
952 * @dev_instance: Pointer to interrupt-specific data
954 * Handles doorbell interrupts. Parses a list of registered
955 * doorbell event handlers and executes a matching event handler.
958 fsl_rio_dbell_handler(int irq, void *dev_instance)
961 struct rio_mport *port = (struct rio_mport *)dev_instance;
962 struct rio_priv *priv = port->priv;
964 dsr = in_be32(&priv->msg_regs->dsr);
966 if (dsr & DOORBELL_DSR_TE) {
967 pr_info("RIO: doorbell reception error\n");
968 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
972 if (dsr & DOORBELL_DSR_QFI) {
973 pr_info("RIO: doorbell queue full\n");
974 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
978 /* XXX Need to check/dispatch until queue empty */
979 if (dsr & DOORBELL_DSR_DIQI) {
981 (u32) priv->dbell_ring.virt +
982 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
983 struct rio_dbell *dbell;
987 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
988 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
990 list_for_each_entry(dbell, &port->dbells, node) {
991 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
992 (dbell->res->end >= DBELL_INF(dmsg))) {
998 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
1002 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1003 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1005 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
1006 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
1014 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1015 * @mport: Master port implementing the inbound doorbell unit
1017 * Initializes doorbell unit hardware and inbound DMA buffer
1018 * ring. Called from fsl_rio_setup(). Returns %0 on success
1019 * or %-ENOMEM on failure.
1021 static int fsl_rio_doorbell_init(struct rio_mport *mport)
1023 struct rio_priv *priv = mport->priv;
1026 /* Map outbound doorbell window immediately after maintenance window */
1027 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1028 RIO_DBELL_WIN_SIZE);
1029 if (!priv->dbell_win) {
1031 "RIO: unable to map outbound doorbell window\n");
1036 /* Initialize inbound doorbells */
1037 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1038 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1039 if (!priv->dbell_ring.virt) {
1040 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1042 iounmap(priv->dbell_win);
1046 /* Point dequeue/enqueue pointers at first entry in ring */
1047 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1048 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1050 /* Clear interrupt status */
1051 out_be32(&priv->msg_regs->dsr, 0x00000091);
1053 /* Hook up doorbell handler */
1054 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1055 "dbell_rx", (void *)mport);
1057 iounmap(priv->dbell_win);
1058 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1059 priv->dbell_ring.virt, priv->dbell_ring.phys);
1061 "MPC85xx RIO: unable to request inbound doorbell irq");
1065 /* Configure doorbells for snooping, 512 entries, and enable */
1066 out_be32(&priv->msg_regs->dmr, 0x00108161);
1073 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1074 * @irq: Linux interrupt number
1075 * @dev_instance: Pointer to interrupt-specific data
1077 * Handles port write interrupts. Parses a list of registered
1078 * port write event handlers and executes a matching event handler.
1081 fsl_rio_port_write_handler(int irq, void *dev_instance)
1084 struct rio_mport *port = (struct rio_mport *)dev_instance;
1085 struct rio_priv *priv = port->priv;
1088 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1089 if (!(epwisr & RIO_EPWISR_PW))
1092 ipwmr = in_be32(&priv->msg_regs->pwmr);
1093 ipwsr = in_be32(&priv->msg_regs->pwsr);
1096 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1097 if (ipwsr & RIO_IPWSR_QF)
1099 if (ipwsr & RIO_IPWSR_TE)
1101 if (ipwsr & RIO_IPWSR_QFI)
1103 if (ipwsr & RIO_IPWSR_PWD)
1105 if (ipwsr & RIO_IPWSR_PWB)
1109 /* Schedule deferred processing if PW was received */
1110 if (ipwsr & RIO_IPWSR_QFI) {
1111 /* Save PW message (if there is room in FIFO),
1112 * otherwise discard it.
1114 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1115 priv->port_write_msg.msg_count++;
1116 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1119 priv->port_write_msg.discard_count++;
1120 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1121 priv->port_write_msg.discard_count);
1123 /* Clear interrupt and issue Clear Queue command. This allows
1124 * another port-write to be received.
1126 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
1127 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1129 schedule_work(&priv->pw_work);
1132 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1133 priv->port_write_msg.err_count++;
1134 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1135 priv->port_write_msg.err_count);
1136 /* Clear Transaction Error: port-write controller should be
1137 * disabled when clearing this error
1139 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1140 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
1141 out_be32(&priv->msg_regs->pwmr, ipwmr);
1144 if (ipwsr & RIO_IPWSR_PWD) {
1145 priv->port_write_msg.discard_count++;
1146 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1147 priv->port_write_msg.discard_count);
1148 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1152 if (epwisr & RIO_EPWISR_PINT) {
1153 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1154 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1155 out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
1161 static void fsl_pw_dpc(struct work_struct *work)
1163 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1164 unsigned long flags;
1165 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1168 * Process port-write messages
1170 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1171 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1173 /* Process one message */
1174 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1178 pr_debug("%s : Port-Write Message:", __func__);
1179 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1181 pr_debug("\n0x%02x: 0x%08x", i*4,
1184 pr_debug(" 0x%08x", msg_buffer[i]);
1189 /* Pass the port-write message to RIO core for processing */
1190 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1191 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1193 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1197 * fsl_rio_pw_enable - enable/disable port-write interface init
1198 * @mport: Master port implementing the port write unit
1199 * @enable: 1=enable; 0=disable port-write message handling
1201 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1203 struct rio_priv *priv = mport->priv;
1206 rval = in_be32(&priv->msg_regs->pwmr);
1209 rval |= RIO_IPWMR_PWE;
1211 rval &= ~RIO_IPWMR_PWE;
1213 out_be32(&priv->msg_regs->pwmr, rval);
1219 * fsl_rio_port_write_init - MPC85xx port write interface init
1220 * @mport: Master port implementing the port write unit
1222 * Initializes port write unit hardware and DMA buffer
1223 * ring. Called from fsl_rio_setup(). Returns %0 on success
1224 * or %-ENOMEM on failure.
1226 static int fsl_rio_port_write_init(struct rio_mport *mport)
1228 struct rio_priv *priv = mport->priv;
1231 /* Following configurations require a disabled port write controller */
1232 out_be32(&priv->msg_regs->pwmr,
1233 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1235 /* Initialize port write */
1236 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1238 &priv->port_write_msg.phys, GFP_KERNEL);
1239 if (!priv->port_write_msg.virt) {
1240 pr_err("RIO: unable allocate port write queue\n");
1244 priv->port_write_msg.err_count = 0;
1245 priv->port_write_msg.discard_count = 0;
1247 /* Point dequeue/enqueue pointers at first entry */
1248 out_be32(&priv->msg_regs->epwqbar, 0);
1249 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1251 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1252 in_be32(&priv->msg_regs->epwqbar),
1253 in_be32(&priv->msg_regs->pwqbar));
1255 /* Clear interrupt status IPWSR */
1256 out_be32(&priv->msg_regs->pwsr,
1257 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1259 /* Configure port write contoller for snooping enable all reporting,
1261 out_be32(&priv->msg_regs->pwmr,
1262 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1265 /* Hook up port-write handler */
1266 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
1267 "port-write", (void *)mport);
1269 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1273 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1274 spin_lock_init(&priv->pw_fifo_lock);
1275 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1276 pr_err("FIFO allocation failed\n");
1281 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1282 in_be32(&priv->msg_regs->pwmr),
1283 in_be32(&priv->msg_regs->pwsr));
1288 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1290 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1291 priv->port_write_msg.virt,
1292 priv->port_write_msg.phys);
1296 static char *cmdline = NULL;
1298 static int fsl_rio_get_hdid(int index)
1300 /* XXX Need to parse multiple entries in some format */
1304 return simple_strtol(cmdline, NULL, 0);
1307 static int fsl_rio_get_cmdline(char *s)
1316 __setup("riohdid=", fsl_rio_get_cmdline);
1318 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1323 switch (ccsr >> 30) {
1334 dev_info(dev, "Hardware port width: %s\n", str);
1336 switch ((ccsr >> 27) & 7) {
1338 str = "Single-lane 0";
1341 str = "Single-lane 2";
1350 dev_info(dev, "Training connection status: %s\n", str);
1353 if (!(ccsr & 0x80000000))
1354 dev_info(dev, "Output port operating in 8-bit mode\n");
1355 if (!(ccsr & 0x08000000))
1356 dev_info(dev, "Input port operating in 8-bit mode\n");
1361 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
1362 * @dev: platform_device pointer
1364 * Initializes MPC85xx RapidIO hardware interface, configures
1365 * master port with system-specific info, and registers the
1366 * master port with the RapidIO subsystem.
1368 int fsl_rio_setup(struct platform_device *dev)
1370 struct rio_ops *ops;
1371 struct rio_mport *port;
1372 struct rio_priv *priv;
1374 const u32 *dt_range, *cell;
1375 struct resource regs;
1378 u64 law_start, law_size;
1381 if (!dev->dev.of_node) {
1382 dev_err(&dev->dev, "Device OF-Node is NULL");
1386 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
1388 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1389 dev->dev.of_node->full_name);
1392 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1393 dev_info(&dev->dev, "Regs: %pR\n", ®s);
1395 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1397 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1398 dev->dev.of_node->full_name);
1402 /* Get node address wide */
1403 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1407 aw = of_n_addr_cells(dev->dev.of_node);
1408 /* Get node size wide */
1409 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1413 sw = of_n_size_cells(dev->dev.of_node);
1414 /* Get parent address wide wide */
1415 paw = of_n_addr_cells(dev->dev.of_node);
1417 law_start = of_read_number(dt_range + aw, paw);
1418 law_size = of_read_number(dt_range + aw + paw, sw);
1420 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1421 law_start, law_size);
1423 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1428 ops->lcread = fsl_local_config_read;
1429 ops->lcwrite = fsl_local_config_write;
1430 ops->cread = fsl_rio_config_read;
1431 ops->cwrite = fsl_rio_config_write;
1432 ops->dsend = fsl_rio_doorbell_send;
1433 ops->pwenable = fsl_rio_pw_enable;
1435 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1443 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1445 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1450 INIT_LIST_HEAD(&port->dbells);
1451 port->iores.start = law_start;
1452 port->iores.end = law_start + law_size - 1;
1453 port->iores.flags = IORESOURCE_MEM;
1454 port->iores.name = "rio_io_win";
1456 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1457 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1458 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1459 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1460 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1461 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1463 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1464 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1465 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1466 strcpy(port->name, "RIO0 mport");
1468 priv->dev = &dev->dev;
1471 port->host_deviceid = fsl_rio_get_hdid(port->id);
1474 rio_register_mport(port);
1476 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1477 rio_regs_win = priv->regs_win;
1479 /* Probe the master port phy type */
1480 ccsr = in_be32(priv->regs_win + RIO_CCSR);
1481 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1482 dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1483 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1484 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1486 /* Checking the port training status */
1487 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1488 dev_err(&dev->dev, "Port is not ready. "
1489 "Try to restart connection...\n");
1490 switch (port->phy_type) {
1491 case RIO_PHY_SERIAL:
1493 out_be32(priv->regs_win + RIO_CCSR, 0);
1495 setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1497 setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1499 case RIO_PHY_PARALLEL:
1501 out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1503 out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1507 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1508 dev_err(&dev->dev, "Port restart failed.\n");
1512 dev_info(&dev->dev, "Port restart success!\n");
1514 fsl_rio_info(&dev->dev, ccsr);
1516 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1517 & RIO_PEF_CTLS) >> 4;
1518 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1519 port->sys_size ? 65536 : 256);
1521 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1522 + RIO_ATMU_REGS_OFFSET);
1523 priv->maint_atmu_regs = priv->atmu_regs + 1;
1524 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1525 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1526 ((port->phy_type == RIO_PHY_SERIAL) ?
1527 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1529 /* Set to receive any dist ID for serial RapidIO controller. */
1530 if (port->phy_type == RIO_PHY_SERIAL)
1531 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1533 /* Configure maintenance transaction window */
1534 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1535 out_be32(&priv->maint_atmu_regs->rowar,
1536 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1538 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1540 /* Configure outbound doorbell window */
1541 out_be32(&priv->dbell_atmu_regs->rowbar,
1542 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1543 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1544 fsl_rio_doorbell_init(port);
1545 fsl_rio_port_write_init(port);
1548 saved_mcheck_exception = ppc_md.machine_check_exception;
1549 ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
1551 /* Ensure that RFXE is set */
1552 mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
1556 iounmap(priv->regs_win);
1566 /* The probe function for RapidIO peer-to-peer network.
1568 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev,
1569 const struct of_device_id *match)
1572 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1573 dev->dev.of_node->full_name);
1575 rc = fsl_rio_setup(dev);
1579 /* Enumerate all registered ports */
1580 rc = rio_init_mports();
1585 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1587 .compatible = "fsl,rapidio-delta",
1592 static struct of_platform_driver fsl_of_rio_rpn_driver = {
1594 .name = "fsl-of-rio",
1595 .owner = THIS_MODULE,
1596 .of_match_table = fsl_of_rio_rpn_ids,
1598 .probe = fsl_of_rio_rpn_probe,
1601 static __init int fsl_of_rio_rpn_init(void)
1603 return of_register_platform_driver(&fsl_of_rio_rpn_driver);
1606 subsys_initcall(fsl_of_rio_rpn_init);