2 * P4080DS Device Tree Source
4 * Copyright 2009 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
43 cpu0: PowerPC,4080@0 {
46 next-level-cache = <&L2_0>;
50 cpu1: PowerPC,4080@1 {
53 next-level-cache = <&L2_1>;
57 cpu2: PowerPC,4080@2 {
60 next-level-cache = <&L2_2>;
64 cpu3: PowerPC,4080@3 {
67 next-level-cache = <&L2_3>;
71 cpu4: PowerPC,4080@4 {
74 next-level-cache = <&L2_4>;
78 cpu5: PowerPC,4080@5 {
81 next-level-cache = <&L2_5>;
85 cpu6: PowerPC,4080@6 {
88 next-level-cache = <&L2_6>;
92 cpu7: PowerPC,4080@7 {
95 next-level-cache = <&L2_7>;
102 device_type = "memory";
106 #address-cells = <1>;
109 compatible = "simple-bus";
110 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
111 reg = <0xf 0xfe000000 0 0x00001000>;
114 compatible = "fsl,corenet-law";
119 memory-controller@8000 {
120 compatible = "fsl,p4080-memory-controller";
121 reg = <0x8000 0x1000>;
122 interrupt-parent = <&mpic>;
123 interrupts = <0x12 2>;
126 memory-controller@9000 {
127 compatible = "fsl,p4080-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupt-parent = <&mpic>;
130 interrupts = <0x12 2>;
134 compatible = "fsl,corenet-cf";
135 reg = <0x18000 0x1000>;
136 fsl,ccf-num-csdids = <32>;
137 fsl,ccf-num-snoopids = <32>;
141 compatible = "fsl,p4080-pamu";
142 reg = <0x20000 0x10000>;
144 interrupt-parent = <&mpic>;
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0x40000 0x40000>;
152 compatible = "chrp,open-pic";
153 device_type = "open-pic";
157 #address-cells = <1>;
159 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
160 reg = <0x100300 0x4>;
161 ranges = <0x0 0x100100 0x200>;
164 compatible = "fsl,p4080-dma-channel",
165 "fsl,eloplus-dma-channel";
168 interrupt-parent = <&mpic>;
172 compatible = "fsl,p4080-dma-channel",
173 "fsl,eloplus-dma-channel";
176 interrupt-parent = <&mpic>;
180 compatible = "fsl,p4080-dma-channel",
181 "fsl,eloplus-dma-channel";
184 interrupt-parent = <&mpic>;
188 compatible = "fsl,p4080-dma-channel",
189 "fsl,eloplus-dma-channel";
192 interrupt-parent = <&mpic>;
198 #address-cells = <1>;
200 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
201 reg = <0x101300 0x4>;
202 ranges = <0x0 0x101100 0x200>;
205 compatible = "fsl,p4080-dma-channel",
206 "fsl,eloplus-dma-channel";
209 interrupt-parent = <&mpic>;
213 compatible = "fsl,p4080-dma-channel",
214 "fsl,eloplus-dma-channel";
217 interrupt-parent = <&mpic>;
221 compatible = "fsl,p4080-dma-channel",
222 "fsl,eloplus-dma-channel";
225 interrupt-parent = <&mpic>;
229 compatible = "fsl,p4080-dma-channel",
230 "fsl,eloplus-dma-channel";
233 interrupt-parent = <&mpic>;
240 #address-cells = <1>;
242 compatible = "fsl,espi";
243 reg = <0x110000 0x1000>;
244 interrupts = <53 0x2>;
245 interrupt-parent = <&mpic>;
246 espi,num-ss-bits = <4>;
250 #address-cells = <1>;
252 compatible = "fsl,espi-flash";
254 linux,modalias = "fsl_m25p80";
255 spi-max-frequency = <40000000>; /* input clock */
258 reg = <0x00000000 0x00100000>;
263 reg = <0x00100000 0x00500000>;
268 reg = <0x00600000 0x00100000>;
272 label = "file system";
273 reg = <0x00700000 0x00900000>;
279 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
280 reg = <0x114000 0x1000>;
282 interrupt-parent = <&mpic>;
287 #address-cells = <1>;
290 compatible = "fsl-i2c";
291 reg = <0x118000 0x100>;
293 interrupt-parent = <&mpic>;
298 #address-cells = <1>;
301 compatible = "fsl-i2c";
302 reg = <0x118100 0x100>;
304 interrupt-parent = <&mpic>;
307 compatible = "at24,24c256";
311 compatible = "at24,24c256";
315 compatible = "dallas,ds3232";
317 interrupts = <0 0x1>;
318 interrupt-parent = <&mpic>;
323 #address-cells = <1>;
326 compatible = "fsl-i2c";
327 reg = <0x119000 0x100>;
329 interrupt-parent = <&mpic>;
334 #address-cells = <1>;
337 compatible = "fsl-i2c";
338 reg = <0x119100 0x100>;
340 interrupt-parent = <&mpic>;
344 serial0: serial@11c500 {
346 device_type = "serial";
347 compatible = "ns16550";
348 reg = <0x11c500 0x100>;
349 clock-frequency = <0>;
351 interrupt-parent = <&mpic>;
354 serial1: serial@11c600 {
356 device_type = "serial";
357 compatible = "ns16550";
358 reg = <0x11c600 0x100>;
359 clock-frequency = <0>;
361 interrupt-parent = <&mpic>;
364 serial2: serial@11d500 {
366 device_type = "serial";
367 compatible = "ns16550";
368 reg = <0x11d500 0x100>;
369 clock-frequency = <0>;
371 interrupt-parent = <&mpic>;
374 serial3: serial@11d600 {
376 device_type = "serial";
377 compatible = "ns16550";
378 reg = <0x11d600 0x100>;
379 clock-frequency = <0>;
381 interrupt-parent = <&mpic>;
385 compatible = "fsl,p4080-gpio";
386 reg = <0x130000 0x1000>;
388 interrupt-parent = <&mpic>;
394 compatible = "fsl,p4080-usb2-mph",
395 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
396 reg = <0x210000 0x1000>;
397 #address-cells = <1>;
399 interrupt-parent = <&mpic>;
400 interrupts = <44 0x2>;
405 compatible = "fsl,p4080-usb2-dr",
406 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
407 reg = <0x211000 0x1000>;
408 #address-cells = <1>;
410 interrupt-parent = <&mpic>;
411 interrupts = <45 0x2>;
417 rapidio0: rapidio@ffe0c0000 {
418 #address-cells = <2>;
420 compatible = "fsl,rapidio-delta";
421 reg = <0xf 0xfe0c0000 0 0x20000>;
422 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
423 interrupt-parent = <&mpic>;
424 /* err_irq bell_outb_irq bell_inb_irq
425 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
426 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
430 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
431 reg = <0xf 0xfe124000 0 0x1000>;
433 #address-cells = <2>;
436 ranges = <0 0 0xf 0xe8000000 0x08000000>;
439 compatible = "cfi-flash";
440 reg = <0 0 0x08000000>;
446 pci0: pcie@ffe200000 {
447 compatible = "fsl,p4080-pcie";
449 #interrupt-cells = <1>;
451 #address-cells = <3>;
452 reg = <0xf 0xfe200000 0 0x1000>;
453 bus-range = <0x0 0xff>;
454 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
455 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
456 clock-frequency = <0x1fca055>;
457 interrupt-parent = <&mpic>;
460 interrupt-map-mask = <0xf800 0 0 7>;
463 0000 0 0 1 &mpic 40 1
471 #address-cells = <3>;
473 ranges = <0x02000000 0 0xe0000000
474 0x02000000 0 0xe0000000
477 0x01000000 0 0x00000000
478 0x01000000 0 0x00000000
483 pci1: pcie@ffe201000 {
484 compatible = "fsl,p4080-pcie";
486 #interrupt-cells = <1>;
488 #address-cells = <3>;
489 reg = <0xf 0xfe201000 0 0x1000>;
490 bus-range = <0 0xff>;
491 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
492 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
493 clock-frequency = <0x1fca055>;
494 interrupt-parent = <&mpic>;
496 interrupt-map-mask = <0xf800 0 0 7>;
499 0000 0 0 1 &mpic 41 1
507 #address-cells = <3>;
509 ranges = <0x02000000 0 0xe0000000
510 0x02000000 0 0xe0000000
513 0x01000000 0 0x00000000
514 0x01000000 0 0x00000000
519 pci2: pcie@ffe202000 {
520 compatible = "fsl,p4080-pcie";
522 #interrupt-cells = <1>;
524 #address-cells = <3>;
525 reg = <0xf 0xfe202000 0 0x1000>;
526 bus-range = <0x0 0xff>;
527 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
528 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
529 clock-frequency = <0x1fca055>;
530 interrupt-parent = <&mpic>;
532 interrupt-map-mask = <0xf800 0 0 7>;
535 0000 0 0 1 &mpic 42 1
537 0000 0 0 3 &mpic 10 1
538 0000 0 0 4 &mpic 11 1
543 #address-cells = <3>;
545 ranges = <0x02000000 0 0xe0000000
546 0x02000000 0 0xe0000000
549 0x01000000 0 0x00000000
550 0x01000000 0 0x00000000