2 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
13 #include <asm/irq_cpu.h>
14 #include <asm/i8259.h>
18 * the first level int-handler will jump here if it is a bonito irq
20 static void bonito_irqdispatch(void)
25 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
26 int_status = BONITO_INTISR;
27 if (int_status & (1 << 10)) {
28 while (int_status & (1 << 10)) {
30 int_status = BONITO_INTISR;
34 /* Get pending sources, masked by current enables */
35 int_status = BONITO_INTISR & BONITO_INTEN;
37 if (int_status != 0) {
38 i = __ffs(int_status);
39 int_status &= ~(1 << i);
40 do_IRQ(BONITO_IRQ_BASE + i);
44 static void i8259_irqdispatch(void)
55 asmlinkage void plat_irq_dispatch(void)
57 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
59 if (pending & CAUSEF_IP7)
60 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
61 else if (pending & CAUSEF_IP5)
63 else if (pending & CAUSEF_IP2)
69 static struct irqaction cascade_irqaction = {
74 void __init arch_init_irq(void)
77 * Clear all of the interrupts while we change the able around a bit.
78 * int-handler is not on bootstrap
80 clear_c0_status(ST0_IM | ST0_BEV);
83 /* most bonito irq should be level triggered */
84 BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
85 BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
89 * Mask out all interrupt by writing "1" to all bit position in
90 * the interrupt reset reg.
94 /* init all controller
95 * 0-15 ------> i8259 interrupt
96 * 16-23 ------> mips cpu interrupt
97 * 32-63 ------> bonito irq
100 /* Sets the first-level interrupt dispatcher. */
105 /* bonito irq at IP2 */
106 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
107 /* 8259 irq at IP5 */
108 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);