2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * Copyright (C) 2001 Ralf Baechle
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
9 * This file define the irq handler for MIPS CPU interrupts.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
25 * Don't even think about using this on SMP. You have been warned.
27 * This file exports one global function:
28 * void mips_cpu_irq_init(int irq_base);
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/kernel.h>
34 #include <asm/irq_cpu.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mipsmtregs.h>
37 #include <asm/system.h>
39 static int mips_cpu_irq_base;
41 static inline void unmask_mips_irq(unsigned int irq)
43 set_c0_status(0x100 << (irq - mips_cpu_irq_base));
47 static inline void mask_mips_irq(unsigned int irq)
49 clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
53 static void mips_cpu_irq_end(unsigned int irq)
55 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
59 static struct irq_chip mips_cpu_irq_controller = {
62 .mask = mask_mips_irq,
63 .mask_ack = mask_mips_irq,
64 .unmask = unmask_mips_irq,
65 .end = mips_cpu_irq_end,
69 * Basically the same as above but taking care of all the MT stuff
72 #define unmask_mips_mt_irq unmask_mips_irq
73 #define mask_mips_mt_irq mask_mips_irq
75 static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
77 unsigned int vpflags = dvpe();
79 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
81 unmask_mips_mt_irq(irq);
87 * While we ack the interrupt interrupts are disabled and thus we don't need
88 * to deal with concurrency issues. Same for mips_cpu_irq_end.
90 static void mips_mt_cpu_irq_ack(unsigned int irq)
92 unsigned int vpflags = dvpe();
93 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
95 mask_mips_mt_irq(irq);
98 #define mips_mt_cpu_irq_end mips_cpu_irq_end
100 static struct irq_chip mips_mt_cpu_irq_controller = {
102 .startup = mips_mt_cpu_irq_startup,
103 .ack = mips_mt_cpu_irq_ack,
104 .mask = mask_mips_mt_irq,
105 .mask_ack = mips_mt_cpu_irq_ack,
106 .unmask = unmask_mips_mt_irq,
107 .end = mips_mt_cpu_irq_end,
110 void __init mips_cpu_irq_init(int irq_base)
114 /* Mask interrupts. */
115 clear_c0_status(ST0_IM);
116 clear_c0_cause(CAUSEF_IP);
119 * Only MT is using the software interrupts currently, so we just
120 * leave them uninitialized for other processors.
123 for (i = irq_base; i < irq_base + 2; i++)
124 set_irq_chip(i, &mips_mt_cpu_irq_controller);
126 for (i = irq_base + 2; i < irq_base + 8; i++)
127 set_irq_chip(i, &mips_cpu_irq_controller);
129 mips_cpu_irq_base = irq_base;