arch/ia64/kernel/ptrace.c

   1 /*
   2  * Kernel support for the ptrace() and syscall tracing interfaces.
   3  *
   4  * Copyright (C) 1999-2005 Hewlett-Packard Co
   5  *      David Mosberger-Tang <davidm@hpl.hp.com>
   6  *
   7  * Derived from the x86 and Alpha versions.
   8  */
   9 #include <linux/config.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/slab.h>
  13 #include <linux/mm.h>
  14 #include <linux/errno.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/smp_lock.h>
  17 #include <linux/user.h>
  18 #include <linux/security.h>
  19 #include <linux/audit.h>
  20 #include <linux/signal.h>
  21
  22 #include <asm/pgtable.h>
  23 #include <asm/processor.h>
  24 #include <asm/ptrace_offsets.h>
  25 #include <asm/rse.h>
  26 #include <asm/system.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/unwind.h>
  29 #ifdef CONFIG_PERFMON
  30 #include <asm/perfmon.h>
  31 #endif
  32
  33 #include "entry.h"
  34
  35 /*
  36  * Bits in the PSR that we allow ptrace() to change:
  37  *      be, up, ac, mfl, mfh (the user mask; five bits total)
  38  *      db (debug breakpoint fault; one bit)
  39  *      id (instruction debug fault disable; one bit)
  40  *      dd (data debug fault disable; one bit)
  41  *      ri (restart instruction; two bits)
  42  *      is (instruction set; one bit)
  43  */
  44 #define IPSR_MASK (IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS      \
  45                    | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
  46
  47 #define MASK(nbits)     ((1UL << (nbits)) - 1)  /* mask with NBITS bits set */
  48 #define PFM_MASK        MASK(38)
  49
  50 #define PTRACE_DEBUG    0
  51
  52 #if PTRACE_DEBUG
  53 # define dprintk(format...)     printk(format)
  54 # define inline
  55 #else
  56 # define dprintk(format...)
  57 #endif
  58
  59 /* Return TRUE if PT was created due to kernel-entry via a system-call.  */
  60
  61 static inline int
  62 in_syscall (struct pt_regs *pt)
  63 {
  64         return (long) pt->cr_ifs >= 0;
  65 }
  66
  67 /*
  68  * Collect the NaT bits for r1-r31 from scratch_unat and return a NaT
  69  * bitset where bit i is set iff the NaT bit of register i is set.
  70  */
  71 unsigned long
  72 ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat)
  73 {
  74 #       define GET_BITS(first, last, unat)                              \
  75         ({                                                              \
  76                 unsigned long bit = ia64_unat_pos(&pt->r##first);       \
  77                 unsigned long nbits = (last - first + 1);               \
  78                 unsigned long mask = MASK(nbits) << first;              \
  79                 unsigned long dist;                                     \
  80                 if (bit < first)                                        \
  81                         dist = 64 + bit - first;                        \
  82                 else                                                    \
  83                         dist = bit - first;                             \
  84                 ia64_rotr(unat, dist) & mask;                           \
  85         })
  86         unsigned long val;
  87
  88         /*
  89          * Registers that are stored consecutively in struct pt_regs
  90          * can be handled in parallel.  If the register order in
  91          * struct_pt_regs changes, this code MUST be updated.
  92          */
  93         val  = GET_BITS( 1,  1, scratch_unat);
  94         val |= GET_BITS( 2,  3, scratch_unat);
  95         val |= GET_BITS(12, 13, scratch_unat);
  96         val |= GET_BITS(14, 14, scratch_unat);
  97         val |= GET_BITS(15, 15, scratch_unat);
  98         val |= GET_BITS( 8, 11, scratch_unat);
  99         val |= GET_BITS(16, 31, scratch_unat);
 100         return val;
 101
 102 #       undef GET_BITS
 103 }
 104
 105 /*
 106  * Set the NaT bits for the scratch registers according to NAT and
 107  * return the resulting unat (assuming the scratch registers are
 108  * stored in PT).
 109  */
 110 unsigned long
 111 ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat)
 112 {
 113 #       define PUT_BITS(first, last, nat)                               \
 114         ({                                                              \
 115                 unsigned long bit = ia64_unat_pos(&pt->r##first);       \
 116                 unsigned long nbits = (last - first + 1);               \
 117                 unsigned long mask = MASK(nbits) << first;              \
 118                 long dist;                                              \
 119                 if (bit < first)                                        \
 120                         dist = 64 + bit - first;                        \
 121                 else                                                    \
 122                         dist = bit - first;                             \
 123                 ia64_rotl(nat & mask, dist);                            \
 124         })
 125         unsigned long scratch_unat;
 126
 127         /*
 128          * Registers that are stored consecutively in struct pt_regs
 129          * can be handled in parallel.  If the register order in
 130          * struct_pt_regs changes, this code MUST be updated.
 131          */
 132         scratch_unat  = PUT_BITS( 1,  1, nat);
 133         scratch_unat |= PUT_BITS( 2,  3, nat);
 134         scratch_unat |= PUT_BITS(12, 13, nat);
 135         scratch_unat |= PUT_BITS(14, 14, nat);
 136         scratch_unat |= PUT_BITS(15, 15, nat);
 137         scratch_unat |= PUT_BITS( 8, 11, nat);
 138         scratch_unat |= PUT_BITS(16, 31, nat);
 139
 140         return scratch_unat;
 141
 142 #       undef PUT_BITS
 143 }
 144
 145 #define IA64_MLX_TEMPLATE       0x2
 146 #define IA64_MOVL_OPCODE        6
 147
 148 void
 149 ia64_increment_ip (struct pt_regs *regs)
 150 {
 151         unsigned long w0, ri = ia64_psr(regs)->ri + 1;
 152
 153         if (ri > 2) {
 154                 ri = 0;
 155                 regs->cr_iip += 16;
 156         } else if (ri == 2) {
 157                 get_user(w0, (char __user *) regs->cr_iip + 0);
 158                 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
 159                         /*
 160                          * rfi'ing to slot 2 of an MLX bundle causes
 161                          * an illegal operation fault.  We don't want
 162                          * that to happen...
 163                          */
 164                         ri = 0;
 165                         regs->cr_iip += 16;
 166                 }
 167         }
 168         ia64_psr(regs)->ri = ri;
 169 }
 170
 171 void
 172 ia64_decrement_ip (struct pt_regs *regs)
 173 {
 174         unsigned long w0, ri = ia64_psr(regs)->ri - 1;
 175
 176         if (ia64_psr(regs)->ri == 0) {
 177                 regs->cr_iip -= 16;
 178                 ri = 2;
 179                 get_user(w0, (char __user *) regs->cr_iip + 0);
 180                 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
 181                         /*
 182                          * rfi'ing to slot 2 of an MLX bundle causes
 183                          * an illegal operation fault.  We don't want
 184                          * that to happen...
 185                          */
 186                         ri = 1;
 187                 }
 188         }
 189         ia64_psr(regs)->ri = ri;
 190 }
 191
 192 /*
 193  * This routine is used to read an rnat bits that are stored on the
 194  * kernel backing store.  Since, in general, the alignment of the user
 195  * and kernel are different, this is not completely trivial.  In
 196  * essence, we need to construct the user RNAT based on up to two
 197  * kernel RNAT values and/or the RNAT value saved in the child's
 198  * pt_regs.
 199  *
 200  * user rbs
 201  *
 202  * +--------+ <-- lowest address
 203  * | slot62 |
 204  * +--------+
 205  * |  rnat  | 0x....1f8
 206  * +--------+
 207  * | slot00 | \
 208  * +--------+ |
 209  * | slot01 | > child_regs->ar_rnat
 210  * +--------+ |
 211  * | slot02 | /                         kernel rbs
 212  * +--------+                           +--------+
 213  *          <- child_regs->ar_bspstore  | slot61 | <-- krbs
 214  * +- - - - +                           +--------+
 215  *                                      | slot62 |
 216  * +- - - - +                           +--------+
 217  *                                      |  rnat  |
 218  * +- - - - +                           +--------+
 219  *   vrnat                              | slot00 |
 220  * +- - - - +                           +--------+
 221  *                                      =        =
 222  *                                      +--------+
 223  *                                      | slot00 | \
 224  *                                      +--------+ |
 225  *                                      | slot01 | > child_stack->ar_rnat
 226  *                                      +--------+ |
 227  *                                      | slot02 | /
 228  *                                      +--------+
 229  *                                                <--- child_stack->ar_bspstore
 230  *
 231  * The way to think of this code is as follows: bit 0 in the user rnat
 232  * corresponds to some bit N (0 <= N <= 62) in one of the kernel rnat
 233  * value.  The kernel rnat value holding this bit is stored in
 234  * variable rnat0.  rnat1 is loaded with the kernel rnat value that
 235  * form the upper bits of the user rnat value.
 236  *
 237  * Boundary cases:
 238  *
 239  * o when reading the rnat "below" the first rnat slot on the kernel
 240  *   backing store, rnat0/rnat1 are set to 0 and the low order bits are
 241  *   merged in from pt->ar_rnat.
 242  *
 243  * o when reading the rnat "above" the last rnat slot on the kernel
 244  *   backing store, rnat0/rnat1 gets its value from sw->ar_rnat.
 245  */
 246 static unsigned long
 247 get_rnat (struct task_struct *task, struct switch_stack *sw,
 248           unsigned long *krbs, unsigned long *urnat_addr,
 249           unsigned long *urbs_end)
 250 {
 251         unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr;
 252         unsigned long umask = 0, mask, m;
 253         unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
 254         long num_regs, nbits;
 255         struct pt_regs *pt;
 256
 257         pt = ia64_task_regs(task);
 258         kbsp = (unsigned long *) sw->ar_bspstore;
 259         ubspstore = (unsigned long *) pt->ar_bspstore;
 260
 261         if (urbs_end < urnat_addr)
 262                 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_end);
 263         else
 264                 nbits = 63;
 265         mask = MASK(nbits);
 266         /*
 267          * First, figure out which bit number slot 0 in user-land maps
 268          * to in the kernel rnat.  Do this by figuring out how many
 269          * register slots we're beyond the user's backingstore and
 270          * then computing the equivalent address in kernel space.
 271          */
 272         num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
 273         slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
 274         shift = ia64_rse_slot_num(slot0_kaddr);
 275         rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
 276         rnat0_kaddr = rnat1_kaddr - 64;
 277
 278         if (ubspstore + 63 > urnat_addr) {
 279                 /* some bits need to be merged in from pt->ar_rnat */
 280                 umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
 281                 urnat = (pt->ar_rnat & umask);
 282                 mask &= ~umask;
 283                 if (!mask)
 284                         return urnat;
 285         }
 286
 287         m = mask << shift;
 288         if (rnat0_kaddr >= kbsp)
 289                 rnat0 = sw->ar_rnat;
 290         else if (rnat0_kaddr > krbs)
 291                 rnat0 = *rnat0_kaddr;
 292         urnat |= (rnat0 & m) >> shift;
 293
 294         m = mask >> (63 - shift);
 295         if (rnat1_kaddr >= kbsp)
 296                 rnat1 = sw->ar_rnat;
 297         else if (rnat1_kaddr > krbs)
 298                 rnat1 = *rnat1_kaddr;
 299         urnat |= (rnat1 & m) << (63 - shift);
 300         return urnat;
 301 }
 302
 303 /*
 304  * The reverse of get_rnat.
 305  */
 306 static void
 307 put_rnat (struct task_struct *task, struct switch_stack *sw,
 308           unsigned long *krbs, unsigned long *urnat_addr, unsigned long urnat,
 309           unsigned long *urbs_end)
 310 {
 311         unsigned long rnat0 = 0, rnat1 = 0, *slot0_kaddr, umask = 0, mask, m;
 312         unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
 313         long num_regs, nbits;
 314         struct pt_regs *pt;
 315         unsigned long cfm, *urbs_kargs;
 316
 317         pt = ia64_task_regs(task);
 318         kbsp = (unsigned long *) sw->ar_bspstore;
 319         ubspstore = (unsigned long *) pt->ar_bspstore;
 320
 321         urbs_kargs = urbs_end;
 322         if (in_syscall(pt)) {
 323                 /*
 324                  * If entered via syscall, don't allow user to set rnat bits
 325                  * for syscall args.
 326                  */
 327                 cfm = pt->cr_ifs;
 328                 urbs_kargs = ia64_rse_skip_regs(urbs_end, -(cfm & 0x7f));
 329         }
 330
 331         if (urbs_kargs >= urnat_addr)
 332                 nbits = 63;
 333         else {
 334                 if ((urnat_addr - 63) >= urbs_kargs)
 335                         return;
 336                 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_kargs);
 337         }
 338         mask = MASK(nbits);
 339
 340         /*
 341          * First, figure out which bit number slot 0 in user-land maps
 342          * to in the kernel rnat.  Do this by figuring out how many
 343          * register slots we're beyond the user's backingstore and
 344          * then computing the equivalent address in kernel space.
 345          */
 346         num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
 347         slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
 348         shift = ia64_rse_slot_num(slot0_kaddr);
 349         rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
 350         rnat0_kaddr = rnat1_kaddr - 64;
 351
 352         if (ubspstore + 63 > urnat_addr) {
 353                 /* some bits need to be place in pt->ar_rnat: */
 354                 umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
 355                 pt->ar_rnat = (pt->ar_rnat & ~umask) | (urnat & umask);
 356                 mask &= ~umask;
 357                 if (!mask)
 358                         return;
 359         }
 360         /*
 361          * Note: Section 11.1 of the EAS guarantees that bit 63 of an
 362          * rnat slot is ignored. so we don't have to clear it here.
 363          */
 364         rnat0 = (urnat << shift);
 365         m = mask << shift;
 366         if (rnat0_kaddr >= kbsp)
 367                 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat0 & m);
 368         else if (rnat0_kaddr > krbs)
 369                 *rnat0_kaddr = ((*rnat0_kaddr & ~m) | (rnat0 & m));
 370
 371         rnat1 = (urnat >> (63 - shift));
 372         m = mask >> (63 - shift);
 373         if (rnat1_kaddr >= kbsp)
 374                 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat1 & m);
 375         else if (rnat1_kaddr > krbs)
 376                 *rnat1_kaddr = ((*rnat1_kaddr & ~m) | (rnat1 & m));
 377 }
 378
 379 static inline int
 380 on_kernel_rbs (unsigned long addr, unsigned long bspstore,
 381                unsigned long urbs_end)
 382 {
 383         unsigned long *rnat_addr = ia64_rse_rnat_addr((unsigned long *)
 384                                                       urbs_end);
 385         return (addr >= bspstore && addr <= (unsigned long) rnat_addr);
 386 }
 387
 388 /*
 389  * Read a word from the user-level backing store of task CHILD.  ADDR
 390  * is the user-level address to read the word from, VAL a pointer to
 391  * the return value, and USER_BSP gives the end of the user-level
 392  * backing store (i.e., it's the address that would be in ar.bsp after
 393  * the user executed a "cover" instruction).
 394  *
 395  * This routine takes care of accessing the kernel register backing
 396  * store for those registers that got spilled there.  It also takes
 397  * care of calculating the appropriate RNaT collection words.
 398  */
 399 long
 400 ia64_peek (struct task_struct *child, struct switch_stack *child_stack,
 401            unsigned long user_rbs_end, unsigned long addr, long *val)
 402 {
 403         unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end, *rnat_addr;
 404         struct pt_regs *child_regs;
 405         size_t copied;
 406         long ret;
 407
 408         urbs_end = (long *) user_rbs_end;
 409         laddr = (unsigned long *) addr;
 410         child_regs = ia64_task_regs(child);
 411         bspstore = (unsigned long *) child_regs->ar_bspstore;
 412         krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
 413         if (on_kernel_rbs(addr, (unsigned long) bspstore,
 414                           (unsigned long) urbs_end))
 415         {
 416                 /*
 417                  * Attempt to read the RBS in an area that's actually
 418                  * on the kernel RBS => read the corresponding bits in
 419                  * the kernel RBS.
 420                  */
 421                 rnat_addr = ia64_rse_rnat_addr(laddr);
 422                 ret = get_rnat(child, child_stack, krbs, rnat_addr, urbs_end);
 423
 424                 if (laddr == rnat_addr) {
 425                         /* return NaT collection word itself */
 426                         *val = ret;
 427                         return 0;
 428                 }
 429
 430                 if (((1UL << ia64_rse_slot_num(laddr)) & ret) != 0) {
 431                         /*
 432                          * It is implementation dependent whether the
 433                          * data portion of a NaT value gets saved on a
 434                          * st8.spill or RSE spill (e.g., see EAS 2.6,
 435                          * 4.4.4.6 Register Spill and Fill).  To get
 436                          * consistent behavior across all possible
 437                          * IA-64 implementations, we return zero in
 438                          * this case.
 439                          */
 440                         *val = 0;
 441                         return 0;
 442                 }
 443
 444                 if (laddr < urbs_end) {
 445                         /*
 446                          * The desired word is on the kernel RBS and
 447                          * is not a NaT.
 448                          */
 449                         regnum = ia64_rse_num_regs(bspstore, laddr);
 450                         *val = *ia64_rse_skip_regs(krbs, regnum);
 451                         return 0;
 452                 }
 453         }
 454         copied = access_process_vm(child, addr, &ret, sizeof(ret), 0);
 455         if (copied != sizeof(ret))
 456                 return -EIO;
 457         *val = ret;
 458         return 0;
 459 }
 460
 461 long
 462 ia64_poke (struct task_struct *child, struct switch_stack *child_stack,
 463            unsigned long user_rbs_end, unsigned long addr, long val)
 464 {
 465         unsigned long *bspstore, *krbs, regnum, *laddr;
 466         unsigned long *urbs_end = (long *) user_rbs_end;
 467         struct pt_regs *child_regs;
 468
 469         laddr = (unsigned long *) addr;
 470         child_regs = ia64_task_regs(child);
 471         bspstore = (unsigned long *) child_regs->ar_bspstore;
 472         krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
 473         if (on_kernel_rbs(addr, (unsigned long) bspstore,
 474                           (unsigned long) urbs_end))
 475         {
 476                 /*
 477                  * Attempt to write the RBS in an area that's actually
 478                  * on the kernel RBS => write the corresponding bits
 479                  * in the kernel RBS.
 480                  */
 481                 if (ia64_rse_is_rnat_slot(laddr))
 482                         put_rnat(child, child_stack, krbs, laddr, val,
 483                                  urbs_end);
 484                 else {
 485                         if (laddr < urbs_end) {
 486                                 regnum = ia64_rse_num_regs(bspstore, laddr);
 487                                 *ia64_rse_skip_regs(krbs, regnum) = val;
 488                         }
 489                 }
 490         } else if (access_process_vm(child, addr, &val, sizeof(val), 1)
 491                    != sizeof(val))
 492                 return -EIO;
 493         return 0;
 494 }
 495
 496 /*
 497  * Calculate the address of the end of the user-level register backing
 498  * store.  This is the address that would have been stored in ar.bsp
 499  * if the user had executed a "cover" instruction right before
 500  * entering the kernel.  If CFMP is not NULL, it is used to return the
 501  * "current frame mask" that was active at the time the kernel was
 502  * entered.
 503  */
 504 unsigned long
 505 ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt,
 506                        unsigned long *cfmp)
 507 {
 508         unsigned long *krbs, *bspstore, cfm = pt->cr_ifs;
 509         long ndirty;
 510
 511         krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
 512         bspstore = (unsigned long *) pt->ar_bspstore;
 513         ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
 514
 515         if (in_syscall(pt))
 516                 ndirty += (cfm & 0x7f);
 517         else
 518                 cfm &= ~(1UL << 63);    /* clear valid bit */
 519
 520         if (cfmp)
 521                 *cfmp = cfm;
 522         return (unsigned long) ia64_rse_skip_regs(bspstore, ndirty);
 523 }
 524
 525 /*
 526  * Synchronize (i.e, write) the RSE backing store living in kernel
 527  * space to the VM of the CHILD task.  SW and PT are the pointers to
 528  * the switch_stack and pt_regs structures, respectively.
 529  * USER_RBS_END is the user-level address at which the backing store
 530  * ends.
 531  */
 532 long
 533 ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
 534                     unsigned long user_rbs_start, unsigned long user_rbs_end)
 535 {
 536         unsigned long addr, val;
 537         long ret;
 538
 539         /* now copy word for word from kernel rbs to user rbs: */
 540         for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
 541                 ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
 542                 if (ret < 0)
 543                         return ret;
 544                 if (access_process_vm(child, addr, &val, sizeof(val), 1)
 545                     != sizeof(val))
 546                         return -EIO;
 547         }
 548         return 0;
 549 }
 550
 551 static inline int
 552 thread_matches (struct task_struct *thread, unsigned long addr)
 553 {
 554         unsigned long thread_rbs_end;
 555         struct pt_regs *thread_regs;
 556
 557         if (ptrace_check_attach(thread, 0) < 0)
 558                 /*
 559                  * If the thread is not in an attachable state, we'll
 560                  * ignore it.  The net effect is that if ADDR happens
 561                  * to overlap with the portion of the thread's
 562                  * register backing store that is currently residing
 563                  * on the thread's kernel stack, then ptrace() may end
 564                  * up accessing a stale value.  But if the thread
 565                  * isn't stopped, that's a problem anyhow, so we're
 566                  * doing as well as we can...
 567                  */
 568                 return 0;
 569
 570         thread_regs = ia64_task_regs(thread);
 571         thread_rbs_end = ia64_get_user_rbs_end(thread, thread_regs, NULL);
 572         if (!on_kernel_rbs(addr, thread_regs->ar_bspstore, thread_rbs_end))
 573                 return 0;
 574
 575         return 1;       /* looks like we've got a winner */
 576 }
 577
 578 /*
 579  * GDB apparently wants to be able to read the register-backing store
 580  * of any thread when attached to a given process.  If we are peeking
 581  * or poking an address that happens to reside in the kernel-backing
 582  * store of another thread, we need to attach to that thread, because
 583  * otherwise we end up accessing stale data.
 584  *
 585  * task_list_lock must be read-locked before calling this routine!
 586  */
 587 static struct task_struct *
 588 find_thread_for_addr (struct task_struct *child, unsigned long addr)
 589 {
 590         struct task_struct *g, *p;
 591         struct mm_struct *mm;
 592         int mm_users;
 593
 594         if (!(mm = get_task_mm(child)))
 595                 return child;
 596
 597         /* -1 because of our get_task_mm(): */
 598         mm_users = atomic_read(&mm->mm_users) - 1;
 599         if (mm_users <= 1)
 600                 goto out;               /* not multi-threaded */
 601
 602         /*
 603          * First, traverse the child's thread-list.  Good for scalability with
 604          * NPTL-threads.
 605          */
 606         p = child;
 607         do {
 608                 if (thread_matches(p, addr)) {
 609                         child = p;
 610                         goto out;
 611                 }
 612                 if (mm_users-- <= 1)
 613                         goto out;
 614         } while ((p = next_thread(p)) != child);
 615
 616         do_each_thread(g, p) {
 617                 if (child->mm != mm)
 618                         continue;
 619
 620                 if (thread_matches(p, addr)) {
 621                         child = p;
 622                         goto out;
 623                 }
 624         } while_each_thread(g, p);
 625   out:
 626         mmput(mm);
 627         return child;
 628 }
 629
 630 /*
 631  * Write f32-f127 back to task->thread.fph if it has been modified.
 632  */
 633 inline void
 634 ia64_flush_fph (struct task_struct *task)
 635 {
 636         struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
 637
 638         /*
 639          * Prevent migrating this task while
 640          * we're fiddling with the FPU state
 641          */
 642         preempt_disable();
 643         if (ia64_is_local_fpu_owner(task) && psr->mfh) {
 644                 psr->mfh = 0;
 645                 task->thread.flags |= IA64_THREAD_FPH_VALID;
 646                 ia64_save_fpu(&task->thread.fph[0]);
 647         }
 648         preempt_enable();
 649 }
 650
 651 /*
 652  * Sync the fph state of the task so that it can be manipulated
 653  * through thread.fph.  If necessary, f32-f127 are written back to
 654  * thread.fph or, if the fph state hasn't been used before, thread.fph
 655  * is cleared to zeroes.  Also, access to f32-f127 is disabled to
 656  * ensure that the task picks up the state from thread.fph when it
 657  * executes again.
 658  */
 659 void
 660 ia64_sync_fph (struct task_struct *task)
 661 {
 662         struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
 663
 664         ia64_flush_fph(task);
 665         if (!(task->thread.flags & IA64_THREAD_FPH_VALID)) {
 666                 task->thread.flags |= IA64_THREAD_FPH_VALID;
 667                 memset(&task->thread.fph, 0, sizeof(task->thread.fph));
 668         }
 669         ia64_drop_fpu(task);
 670         psr->dfh = 1;
 671 }
 672
 673 static int
 674 access_fr (struct unw_frame_info *info, int regnum, int hi,
 675            unsigned long *data, int write_access)
 676 {
 677         struct ia64_fpreg fpval;
 678         int ret;
 679
 680         ret = unw_get_fr(info, regnum, &fpval);
 681         if (ret < 0)
 682                 return ret;
 683
 684         if (write_access) {
 685                 fpval.u.bits[hi] = *data;
 686                 ret = unw_set_fr(info, regnum, fpval);
 687         } else
 688                 *data = fpval.u.bits[hi];
 689         return ret;
 690 }
 691
 692 /*
 693  * Change the machine-state of CHILD such that it will return via the normal
 694  * kernel exit-path, rather than the syscall-exit path.
 695  */
 696 static void
 697 convert_to_non_syscall (struct task_struct *child, struct pt_regs  *pt,
 698                         unsigned long cfm)
 699 {
 700         struct unw_frame_info info, prev_info;
 701         unsigned long ip, sp, pr;
 702
 703         unw_init_from_blocked_task(&info, child);
 704         while (1) {
 705                 prev_info = info;
 706                 if (unw_unwind(&info) < 0)
 707                         return;
 708
 709                 unw_get_sp(&info, &sp);
 710                 if ((long)((unsigned long)child + IA64_STK_OFFSET - sp)
 711                     < IA64_PT_REGS_SIZE) {
 712                         dprintk("ptrace.%s: ran off the top of the kernel "
 713                                 "stack\n", __FUNCTION__);
 714                         return;
 715                 }
 716                 if (unw_get_pr (&prev_info, &pr) < 0) {
 717                         unw_get_rp(&prev_info, &ip);
 718                         dprintk("ptrace.%s: failed to read "
 719                                 "predicate register (ip=0x%lx)\n",
 720                                 __FUNCTION__, ip);
 721                         return;
 722                 }
 723                 if (unw_is_intr_frame(&info)
 724                     && (pr & (1UL << PRED_USER_STACK)))
 725                         break;
 726         }
 727
 728         unw_get_pr(&prev_info, &pr);
 729         pr &= ~(1UL << PRED_SYSCALL);
 730         pr |=  (1UL << PRED_NON_SYSCALL);
 731         unw_set_pr(&prev_info, pr);
 732
 733         pt->cr_ifs = (1UL << 63) | cfm;
 734 }
 735
 736 static int
 737 access_nat_bits (struct task_struct *child, struct pt_regs *pt,
 738                  struct unw_frame_info *info,
 739                  unsigned long *data, int write_access)
 740 {
 741         unsigned long regnum, nat_bits, scratch_unat, dummy = 0;
 742         char nat = 0;
 743
 744         if (write_access) {
 745                 nat_bits = *data;
 746                 scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
 747                 if (unw_set_ar(info, UNW_AR_UNAT, scratch_unat) < 0) {
 748                         dprintk("ptrace: failed to set ar.unat\n");
 749                         return -1;
 750                 }
 751                 for (regnum = 4; regnum <= 7; ++regnum) {
 752                         unw_get_gr(info, regnum, &dummy, &nat);
 753                         unw_set_gr(info, regnum, dummy,
 754                                    (nat_bits >> regnum) & 1);
 755                 }
 756         } else {
 757                 if (unw_get_ar(info, UNW_AR_UNAT, &scratch_unat) < 0) {
 758                         dprintk("ptrace: failed to read ar.unat\n");
 759                         return -1;
 760                 }
 761                 nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
 762                 for (regnum = 4; regnum <= 7; ++regnum) {
 763                         unw_get_gr(info, regnum, &dummy, &nat);
 764                         nat_bits |= (nat != 0) << regnum;
 765                 }
 766                 *data = nat_bits;
 767         }
 768         return 0;
 769 }
 770
 771 static int
 772 access_uarea (struct task_struct *child, unsigned long addr,
 773               unsigned long *data, int write_access)
 774 {
 775         unsigned long *ptr, regnum, urbs_end, rnat_addr, cfm;
 776         struct switch_stack *sw;
 777         struct pt_regs *pt;
 778 #       define pt_reg_addr(pt, reg)     ((void *)                           \
 779                                          ((unsigned long) (pt)              \
 780                                           + offsetof(struct pt_regs, reg)))
 781
 782
 783         pt = ia64_task_regs(child);
 784         sw = (struct switch_stack *) (child->thread.ksp + 16);
 785
 786         if ((addr & 0x7) != 0) {
 787                 dprintk("ptrace: unaligned register address 0x%lx\n", addr);
 788                 return -1;
 789         }
 790
 791         if (addr < PT_F127 + 16) {
 792                 /* accessing fph */
 793                 if (write_access)
 794                         ia64_sync_fph(child);
 795                 else
 796                         ia64_flush_fph(child);
 797                 ptr = (unsigned long *)
 798                         ((unsigned long) &child->thread.fph + addr);
 799         } else if ((addr >= PT_F10) && (addr < PT_F11 + 16)) {
 800                 /* scratch registers untouched by kernel (saved in pt_regs) */
 801                 ptr = pt_reg_addr(pt, f10) + (addr - PT_F10);
 802         } else if (addr >= PT_F12 && addr < PT_F15 + 16) {
 803                 /*
 804                  * Scratch registers untouched by kernel (saved in
 805                  * switch_stack).
 806                  */
 807                 ptr = (unsigned long *) ((long) sw
 808                                          + (addr - PT_NAT_BITS - 32));
 809         } else if (addr < PT_AR_LC + 8) {
 810                 /* preserved state: */
 811                 struct unw_frame_info info;
 812                 char nat = 0;
 813                 int ret;
 814
 815                 unw_init_from_blocked_task(&info, child);
 816                 if (unw_unwind_to_user(&info) < 0)
 817                         return -1;
 818
 819                 switch (addr) {
 820                       case PT_NAT_BITS:
 821                         return access_nat_bits(child, pt, &info,
 822                                                data, write_access);
 823
 824                       case PT_R4: case PT_R5: case PT_R6: case PT_R7:
 825                         if (write_access) {
 826                                 /* read NaT bit first: */
 827                                 unsigned long dummy;
 828
 829                                 ret = unw_get_gr(&info, (addr - PT_R4)/8 + 4,
 830                                                  &dummy, &nat);
 831                                 if (ret < 0)
 832                                         return ret;
 833                         }
 834                         return unw_access_gr(&info, (addr - PT_R4)/8 + 4, data,
 835                                              &nat, write_access);
 836
 837                       case PT_B1: case PT_B2: case PT_B3:
 838                       case PT_B4: case PT_B5:
 839                         return unw_access_br(&info, (addr - PT_B1)/8 + 1, data,
 840                                              write_access);
 841
 842                       case PT_AR_EC:
 843                         return unw_access_ar(&info, UNW_AR_EC, data,
 844                                              write_access);
 845
 846                       case PT_AR_LC:
 847                         return unw_access_ar(&info, UNW_AR_LC, data,
 848                                              write_access);
 849
 850                       default:
 851                         if (addr >= PT_F2 && addr < PT_F5 + 16)
 852                                 return access_fr(&info, (addr - PT_F2)/16 + 2,
 853                                                  (addr & 8) != 0, data,
 854                                                  write_access);
 855                         else if (addr >= PT_F16 && addr < PT_F31 + 16)
 856                                 return access_fr(&info,
 857                                                  (addr - PT_F16)/16 + 16,
 858                                                  (addr & 8) != 0,
 859                                                  data, write_access);
 860                         else {
 861                                 dprintk("ptrace: rejecting access to register "
 862                                         "address 0x%lx\n", addr);
 863                                 return -1;
 864                         }
 865                 }
 866         } else if (addr < PT_F9+16) {
 867                 /* scratch state */
 868                 switch (addr) {
 869                       case PT_AR_BSP:
 870                         /*
 871                          * By convention, we use PT_AR_BSP to refer to
 872                          * the end of the user-level backing store.
 873                          * Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof)
 874                          * to get the real value of ar.bsp at the time
 875                          * the kernel was entered.
 876                          *
 877                          * Furthermore, when changing the contents of
 878                          * PT_AR_BSP (or PT_CFM) we MUST copy any
 879                          * users-level stacked registers that are
 880                          * stored on the kernel stack back to
 881                          * user-space because otherwise, we might end
 882                          * up clobbering kernel stacked registers.
 883                          * Also, if this happens while the task is
 884                          * blocked in a system call, which convert the
 885                          * state such that the non-system-call exit
 886                          * path is used.  This ensures that the proper
 887                          * state will be picked up when resuming
 888                          * execution.  However, it *also* means that
 889                          * once we write PT_AR_BSP/PT_CFM, it won't be
 890                          * possible to modify the syscall arguments of
 891                          * the pending system call any longer.  This
 892                          * shouldn't be an issue because modifying
 893                          * PT_AR_BSP/PT_CFM generally implies that
 894                          * we're either abandoning the pending system
 895                          * call or that we defer it's re-execution
 896                          * (e.g., due to GDB doing an inferior
 897                          * function call).
 898                          */
 899                         urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
 900                         if (write_access) {
 901                                 if (*data != urbs_end) {
 902                                         if (ia64_sync_user_rbs(child, sw,
 903                                                                pt->ar_bspstore,
 904                                                                urbs_end) < 0)
 905                                                 return -1;
 906                                         if (in_syscall(pt))
 907                                                 convert_to_non_syscall(child,
 908                                                                        pt,
 909                                                                        cfm);
 910                                         /*
 911                                          * Simulate user-level write
 912                                          * of ar.bsp:
 913                                          */
 914                                         pt->loadrs = 0;
 915                                         pt->ar_bspstore = *data;
 916                                 }
 917                         } else
 918                                 *data = urbs_end;
 919                         return 0;
 920
 921                       case PT_CFM:
 922                         urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
 923                         if (write_access) {
 924                                 if (((cfm ^ *data) & PFM_MASK) != 0) {
 925                                         if (ia64_sync_user_rbs(child, sw,
 926                                                                pt->ar_bspstore,
 927                                                                urbs_end) < 0)
 928                                                 return -1;
 929                                         if (in_syscall(pt))
 930                                                 convert_to_non_syscall(child,
 931                                                                        pt,
 932                                                                        cfm);
 933                                         pt->cr_ifs = ((pt->cr_ifs & ~PFM_MASK)
 934                                                       | (*data & PFM_MASK));
 935                                 }
 936                         } else
 937                                 *data = cfm;
 938                         return 0;
 939
 940                       case PT_CR_IPSR:
 941                         if (write_access)
 942                                 pt->cr_ipsr = ((*data & IPSR_MASK)
 943                                                | (pt->cr_ipsr & ~IPSR_MASK));
 944                         else
 945                                 *data = (pt->cr_ipsr & IPSR_MASK);
 946                         return 0;
 947
 948                       case PT_AR_RNAT:
 949                         urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
 950                         rnat_addr = (long) ia64_rse_rnat_addr((long *)
 951                                                               urbs_end);
 952                         if (write_access)
 953                                 return ia64_poke(child, sw, urbs_end,
 954                                                  rnat_addr, *data);
 955                         else
 956                                 return ia64_peek(child, sw, urbs_end,
 957                                                  rnat_addr, data);
 958
 959                       case PT_R1:
 960                         ptr = pt_reg_addr(pt, r1);
 961                         break;
 962                       case PT_R2:  case PT_R3:
 963                         ptr = pt_reg_addr(pt, r2) + (addr - PT_R2);
 964                         break;
 965                       case PT_R8:  case PT_R9:  case PT_R10: case PT_R11:
 966                         ptr = pt_reg_addr(pt, r8) + (addr - PT_R8);
 967                         break;
 968                       case PT_R12: case PT_R13:
 969                         ptr = pt_reg_addr(pt, r12) + (addr - PT_R12);
 970                         break;
 971                       case PT_R14:
 972                         ptr = pt_reg_addr(pt, r14);
 973                         break;
 974                       case PT_R15:
 975                         ptr = pt_reg_addr(pt, r15);
 976                         break;
 977                       case PT_R16: case PT_R17: case PT_R18: case PT_R19:
 978                       case PT_R20: case PT_R21: case PT_R22: case PT_R23:
 979                       case PT_R24: case PT_R25: case PT_R26: case PT_R27:
 980                       case PT_R28: case PT_R29: case PT_R30: case PT_R31:
 981                         ptr = pt_reg_addr(pt, r16) + (addr - PT_R16);
 982                         break;
 983                       case PT_B0:
 984                         ptr = pt_reg_addr(pt, b0);
 985                         break;
 986                       case PT_B6:
 987                         ptr = pt_reg_addr(pt, b6);
 988                         break;
 989                       case PT_B7:
 990                         ptr = pt_reg_addr(pt, b7);
 991                         break;
 992                       case PT_F6:  case PT_F6+8: case PT_F7: case PT_F7+8:
 993                       case PT_F8:  case PT_F8+8: case PT_F9: case PT_F9+8:
 994                         ptr = pt_reg_addr(pt, f6) + (addr - PT_F6);
 995                         break;
 996                       case PT_AR_BSPSTORE:
 997                         ptr = pt_reg_addr(pt, ar_bspstore);
 998                         break;
 999                       case PT_AR_RSC:
1000                         ptr = pt_reg_addr(pt, ar_rsc);
1001                         break;
1002                       case PT_AR_UNAT:
1003                         ptr = pt_reg_addr(pt, ar_unat);
1004                         break;
1005                       case PT_AR_PFS:
1006                         ptr = pt_reg_addr(pt, ar_pfs);
1007                         break;
1008                       case PT_AR_CCV:
1009                         ptr = pt_reg_addr(pt, ar_ccv);
1010                         break;
1011                       case PT_AR_FPSR:
1012                         ptr = pt_reg_addr(pt, ar_fpsr);
1013                         break;
1014                       case PT_CR_IIP:
1015                         ptr = pt_reg_addr(pt, cr_iip);
1016                         break;
1017                       case PT_PR:
1018                         ptr = pt_reg_addr(pt, pr);
1019                         break;
1020                         /* scratch register */
1021
1022                       default:
1023                         /* disallow accessing anything else... */
1024                         dprintk("ptrace: rejecting access to register "
1025                                 "address 0x%lx\n", addr);
1026                         return -1;
1027                 }
1028         } else if (addr <= PT_AR_SSD) {
1029                 ptr = pt_reg_addr(pt, ar_csd) + (addr - PT_AR_CSD);
1030         } else {
1031                 /* access debug registers */
1032
1033                 if (addr >= PT_IBR) {
1034                         regnum = (addr - PT_IBR) >> 3;
1035                         ptr = &child->thread.ibr[0];
1036                 } else {
1037                         regnum = (addr - PT_DBR) >> 3;
1038                         ptr = &child->thread.dbr[0];
1039                 }
1040
1041                 if (regnum >= 8) {
1042                         dprintk("ptrace: rejecting access to register "
1043                                 "address 0x%lx\n", addr);
1044                         return -1;
1045                 }
1046 #ifdef CONFIG_PERFMON
1047                 /*
1048                  * Check if debug registers are used by perfmon. This
1049                  * test must be done once we know that we can do the
1050                  * operation, i.e. the arguments are all valid, but
1051                  * before we start modifying the state.
1052                  *
1053                  * Perfmon needs to keep a count of how many processes
1054                  * are trying to modify the debug registers for system
1055                  * wide monitoring sessions.
1056                  *
1057                  * We also include read access here, because they may
1058                  * cause the PMU-installed debug register state
1059                  * (dbr[], ibr[]) to be reset. The two arrays are also
1060                  * used by perfmon, but we do not use
1061                  * IA64_THREAD_DBG_VALID. The registers are restored
1062                  * by the PMU context switch code.
1063                  */
1064                 if (pfm_use_debug_registers(child)) return -1;
1065 #endif
1066
1067                 if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
1068                         child->thread.flags |= IA64_THREAD_DBG_VALID;
1069                         memset(child->thread.dbr, 0,
1070                                sizeof(child->thread.dbr));
1071                         memset(child->thread.ibr, 0,
1072                                sizeof(child->thread.ibr));
1073                 }
1074
1075                 ptr += regnum;
1076
1077                 if ((regnum & 1) && write_access) {
1078                         /* don't let the user set kernel-level breakpoints: */
1079                         *ptr = *data & ~(7UL << 56);
1080                         return 0;
1081                 }
1082         }
1083         if (write_access)
1084                 *ptr = *data;
1085         else
1086                 *data = *ptr;
1087         return 0;
1088 }
1089
1090 static long
1091 ptrace_getregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
1092 {
1093         unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val;
1094         struct unw_frame_info info;
1095         struct ia64_fpreg fpval;
1096         struct switch_stack *sw;
1097         struct pt_regs *pt;
1098         long ret, retval = 0;
1099         char nat = 0;
1100         int i;
1101
1102         if (!access_ok(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs)))
1103                 return -EIO;
1104
1105         pt = ia64_task_regs(child);
1106         sw = (struct switch_stack *) (child->thread.ksp + 16);
1107         unw_init_from_blocked_task(&info, child);
1108         if (unw_unwind_to_user(&info) < 0) {
1109                 return -EIO;
1110         }
1111
1112         if (((unsigned long) ppr & 0x7) != 0) {
1113                 dprintk("ptrace:unaligned register address %p\n", ppr);
1114                 return -EIO;
1115         }
1116
1117         if (access_uarea(child, PT_CR_IPSR, &psr, 0) < 0
1118             || access_uarea(child, PT_AR_EC, &ec, 0) < 0
1119             || access_uarea(child, PT_AR_LC, &lc, 0) < 0
1120             || access_uarea(child, PT_AR_RNAT, &rnat, 0) < 0
1121             || access_uarea(child, PT_AR_BSP, &bsp, 0) < 0
1122             || access_uarea(child, PT_CFM, &cfm, 0)
1123             || access_uarea(child, PT_NAT_BITS, &nat_bits, 0))
1124                 return -EIO;
1125
1126         /* control regs */
1127
1128         retval |= __put_user(pt->cr_iip, &ppr->cr_iip);
1129         retval |= __put_user(psr, &ppr->cr_ipsr);
1130
1131         /* app regs */
1132
1133         retval |= __put_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
1134         retval |= __put_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
1135         retval |= __put_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
1136         retval |= __put_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
1137         retval |= __put_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
1138         retval |= __put_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
1139
1140         retval |= __put_user(ec, &ppr->ar[PT_AUR_EC]);
1141         retval |= __put_user(lc, &ppr->ar[PT_AUR_LC]);
1142         retval |= __put_user(rnat, &ppr->ar[PT_AUR_RNAT]);
1143         retval |= __put_user(bsp, &ppr->ar[PT_AUR_BSP]);
1144         retval |= __put_user(cfm, &ppr->cfm);
1145
1146         /* gr1-gr3 */
1147
1148         retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long));
1149         retval |= __copy_to_user(&ppr->gr[2], &pt->r2, sizeof(long) *2);
1150
1151         /* gr4-gr7 */
1152
1153         for (i = 4; i < 8; i++) {
1154                 if (unw_access_gr(&info, i, &val, &nat, 0) < 0)
1155                         return -EIO;
1156                 retval |= __put_user(val, &ppr->gr[i]);
1157         }
1158
1159         /* gr8-gr11 */
1160
1161         retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4);
1162
1163         /* gr12-gr15 */
1164
1165         retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 2);
1166         retval |= __copy_to_user(&ppr->gr[14], &pt->r14, sizeof(long));
1167         retval |= __copy_to_user(&ppr->gr[15], &pt->r15, sizeof(long));
1168
1169         /* gr16-gr31 */
1170
1171         retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16);
1172
1173         /* b0 */
1174
1175         retval |= __put_user(pt->b0, &ppr->br[0]);
1176
1177         /* b1-b5 */
1178
1179         for (i = 1; i < 6; i++) {
1180                 if (unw_access_br(&info, i, &val, 0) < 0)
1181                         return -EIO;
1182                 __put_user(val, &ppr->br[i]);
1183         }
1184
1185         /* b6-b7 */
1186
1187         retval |= __put_user(pt->b6, &ppr->br[6]);
1188         retval |= __put_user(pt->b7, &ppr->br[7]);
1189
1190         /* fr2-fr5 */
1191
1192         for (i = 2; i < 6; i++) {
1193                 if (unw_get_fr(&info, i, &fpval) < 0)
1194                         return -EIO;
1195                 retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
1196         }
1197
1198         /* fr6-fr11 */
1199
1200         retval |= __copy_to_user(&ppr->fr[6], &pt->f6,
1201                                  sizeof(struct ia64_fpreg) * 6);
1202
1203         /* fp scratch regs(12-15) */
1204
1205         retval |= __copy_to_user(&ppr->fr[12], &sw->f12,
1206                                  sizeof(struct ia64_fpreg) * 4);
1207
1208         /* fr16-fr31 */
1209
1210         for (i = 16; i < 32; i++) {
1211                 if (unw_get_fr(&info, i, &fpval) < 0)
1212                         return -EIO;
1213                 retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
1214         }
1215
1216         /* fph */
1217
1218         ia64_flush_fph(child);
1219         retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph,
1220                                  sizeof(ppr->fr[32]) * 96);
1221
1222         /*  preds */
1223
1224         retval |= __put_user(pt->pr, &ppr->pr);
1225
1226         /* nat bits */
1227
1228         retval |= __put_user(nat_bits, &ppr->nat);
1229
1230         ret = retval ? -EIO : 0;
1231         return ret;
1232 }
1233
1234 static long
1235 ptrace_setregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
1236 {
1237         unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val = 0;
1238         struct unw_frame_info info;
1239         struct switch_stack *sw;
1240         struct ia64_fpreg fpval;
1241         struct pt_regs *pt;
1242         long ret, retval = 0;
1243         int i;
1244
1245         memset(&fpval, 0, sizeof(fpval));
1246
1247         if (!access_ok(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs)))
1248                 return -EIO;
1249
1250         pt = ia64_task_regs(child);
1251         sw = (struct switch_stack *) (child->thread.ksp + 16);
1252         unw_init_from_blocked_task(&info, child);
1253         if (unw_unwind_to_user(&info) < 0) {
1254                 return -EIO;
1255         }
1256
1257         if (((unsigned long) ppr & 0x7) != 0) {
1258                 dprintk("ptrace:unaligned register address %p\n", ppr);
1259                 return -EIO;
1260         }
1261
1262         /* control regs */
1263
1264         retval |= __get_user(pt->cr_iip, &ppr->cr_iip);
1265         retval |= __get_user(psr, &ppr->cr_ipsr);
1266
1267         /* app regs */
1268
1269         retval |= __get_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
1270         retval |= __get_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
1271         retval |= __get_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
1272         retval |= __get_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
1273         retval |= __get_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
1274         retval |= __get_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
1275
1276         retval |= __get_user(ec, &ppr->ar[PT_AUR_EC]);
1277         retval |= __get_user(lc, &ppr->ar[PT_AUR_LC]);
1278         retval |= __get_user(rnat, &ppr->ar[PT_AUR_RNAT]);
1279         retval |= __get_user(bsp, &ppr->ar[PT_AUR_BSP]);
1280         retval |= __get_user(cfm, &ppr->cfm);
1281
1282         /* gr1-gr3 */
1283
1284         retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long));
1285         retval |= __copy_from_user(&pt->r2, &ppr->gr[2], sizeof(long) * 2);
1286
1287         /* gr4-gr7 */
1288
1289         for (i = 4; i < 8; i++) {
1290                 retval |= __get_user(val, &ppr->gr[i]);
1291                 /* NaT bit will be set via PT_NAT_BITS: */
1292                 if (unw_set_gr(&info, i, val, 0) < 0)
1293                         return -EIO;
1294         }
1295
1296         /* gr8-gr11 */
1297
1298         retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4);
1299
1300         /* gr12-gr15 */
1301
1302         retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 2);
1303         retval |= __copy_from_user(&pt->r14, &ppr->gr[14], sizeof(long));
1304         retval |= __copy_from_user(&pt->r15, &ppr->gr[15], sizeof(long));
1305
1306         /* gr16-gr31 */
1307
1308         retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16);
1309
1310         /* b0 */
1311
1312         retval |= __get_user(pt->b0, &ppr->br[0]);
1313
1314         /* b1-b5 */
1315
1316         for (i = 1; i < 6; i++) {
1317                 retval |= __get_user(val, &ppr->br[i]);
1318                 unw_set_br(&info, i, val);
1319         }
1320
1321         /* b6-b7 */
1322
1323         retval |= __get_user(pt->b6, &ppr->br[6]);
1324         retval |= __get_user(pt->b7, &ppr->br[7]);
1325
1326         /* fr2-fr5 */
1327
1328         for (i = 2; i < 6; i++) {
1329                 retval |= __copy_from_user(&fpval, &ppr->fr[i], sizeof(fpval));
1330                 if (unw_set_fr(&info, i, fpval) < 0)
1331                         return -EIO;
1332         }
1333
1334         /* fr6-fr11 */
1335
1336         retval |= __copy_from_user(&pt->f6, &ppr->fr[6],
1337                                    sizeof(ppr->fr[6]) * 6);
1338
1339         /* fp scratch regs(12-15) */
1340
1341         retval |= __copy_from_user(&sw->f12, &ppr->fr[12],
1342                                    sizeof(ppr->fr[12]) * 4);
1343
1344         /* fr16-fr31 */
1345
1346         for (i = 16; i < 32; i++) {
1347                 retval |= __copy_from_user(&fpval, &ppr->fr[i],
1348                                            sizeof(fpval));
1349                 if (unw_set_fr(&info, i, fpval) < 0)
1350                         return -EIO;
1351         }
1352
1353         /* fph */
1354
1355         ia64_sync_fph(child);
1356         retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32],
1357                                    sizeof(ppr->fr[32]) * 96);
1358
1359         /* preds */
1360
1361         retval |= __get_user(pt->pr, &ppr->pr);
1362
1363         /* nat bits */
1364
1365         retval |= __get_user(nat_bits, &ppr->nat);
1366
1367         retval |= access_uarea(child, PT_CR_IPSR, &psr, 1);
1368         retval |= access_uarea(child, PT_AR_EC, &ec, 1);
1369         retval |= access_uarea(child, PT_AR_LC, &lc, 1);
1370         retval |= access_uarea(child, PT_AR_RNAT, &rnat, 1);
1371         retval |= access_uarea(child, PT_AR_BSP, &bsp, 1);
1372         retval |= access_uarea(child, PT_CFM, &cfm, 1);
1373         retval |= access_uarea(child, PT_NAT_BITS, &nat_bits, 1);
1374
1375         ret = retval ? -EIO : 0;
1376         return ret;
1377 }
1378
1379 /*
1380  * Called by kernel/ptrace.c when detaching..
1381  *
1382  * Make sure the single step bit is not set.
1383  */
1384 void
1385 ptrace_disable (struct task_struct *child)
1386 {
1387         struct ia64_psr *child_psr = ia64_psr(ia64_task_regs(child));
1388
1389         /* make sure the single step/taken-branch trap bits are not set: */
1390         child_psr->ss = 0;
1391         child_psr->tb = 0;
1392 }
1393
1394 asmlinkage long
1395 sys_ptrace (long request, pid_t pid, unsigned long addr, unsigned long data)
1396 {
1397         struct pt_regs *pt;
1398         unsigned long urbs_end, peek_or_poke;
1399         struct task_struct *child;
1400         struct switch_stack *sw;
1401         long ret;
1402
1403         lock_kernel();
1404         ret = -EPERM;
1405         if (request == PTRACE_TRACEME) {
1406                 /* are we already being traced? */
1407                 if (current->ptrace & PT_PTRACED)
1408                         goto out;
1409                 ret = security_ptrace(current->parent, current);
1410                 if (ret)
1411                         goto out;
1412                 current->ptrace |= PT_PTRACED;
1413                 ret = 0;
1414                 goto out;
1415         }
1416
1417         peek_or_poke = (request == PTRACE_PEEKTEXT
1418                         || request == PTRACE_PEEKDATA
1419                         || request == PTRACE_POKETEXT
1420                         || request == PTRACE_POKEDATA);
1421         ret = -ESRCH;
1422         read_lock(&tasklist_lock);
1423         {
1424                 child = find_task_by_pid(pid);
1425                 if (child) {
1426                         if (peek_or_poke)
1427                                 child = find_thread_for_addr(child, addr);
1428                         get_task_struct(child);
1429                 }
1430         }
1431         read_unlock(&tasklist_lock);
1432         if (!child)
1433                 goto out;
1434         ret = -EPERM;
1435         if (pid == 1)           /* no messing around with init! */
1436                 goto out_tsk;
1437
1438         if (request == PTRACE_ATTACH) {
1439                 ret = ptrace_attach(child);
1440                 goto out_tsk;
1441         }
1442
1443         ret = ptrace_check_attach(child, request == PTRACE_KILL);
1444         if (ret < 0)
1445                 goto out_tsk;
1446
1447         pt = ia64_task_regs(child);
1448         sw = (struct switch_stack *) (child->thread.ksp + 16);
1449
1450         switch (request) {
1451               case PTRACE_PEEKTEXT:
1452               case PTRACE_PEEKDATA:
1453                 /* read word at location addr */
1454                 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1455                 ret = ia64_peek(child, sw, urbs_end, addr, &data);
1456                 if (ret == 0) {
1457                         ret = data;
1458                         /* ensure "ret" is not mistaken as an error code: */
1459                         force_successful_syscall_return();
1460                 }
1461                 goto out_tsk;
1462
1463               case PTRACE_POKETEXT:
1464               case PTRACE_POKEDATA:
1465                 /* write the word at location addr */
1466                 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1467                 ret = ia64_poke(child, sw, urbs_end, addr, data);
1468                 goto out_tsk;
1469
1470               case PTRACE_PEEKUSR:
1471                 /* read the word at addr in the USER area */
1472                 if (access_uarea(child, addr, &data, 0) < 0) {
1473                         ret = -EIO;
1474                         goto out_tsk;
1475                 }
1476                 ret = data;
1477                 /* ensure "ret" is not mistaken as an error code */
1478                 force_successful_syscall_return();
1479                 goto out_tsk;
1480
1481               case PTRACE_POKEUSR:
1482                 /* write the word at addr in the USER area */
1483                 if (access_uarea(child, addr, &data, 1) < 0) {
1484                         ret = -EIO;
1485                         goto out_tsk;
1486                 }
1487                 ret = 0;
1488                 goto out_tsk;
1489
1490               case PTRACE_OLD_GETSIGINFO:
1491                 /* for backwards-compatibility */
1492                 ret = ptrace_request(child, PTRACE_GETSIGINFO, addr, data);
1493                 goto out_tsk;
1494
1495               case PTRACE_OLD_SETSIGINFO:
1496                 /* for backwards-compatibility */
1497                 ret = ptrace_request(child, PTRACE_SETSIGINFO, addr, data);
1498                 goto out_tsk;
1499
1500               case PTRACE_SYSCALL:
1501                 /* continue and stop at next (return from) syscall */
1502               case PTRACE_CONT:
1503                 /* restart after signal. */
1504                 ret = -EIO;
1505                 if (!valid_signal(data))
1506                         goto out_tsk;
1507                 if (request == PTRACE_SYSCALL)
1508                         set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1509                 else
1510                         clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1511                 child->exit_code = data;
1512
1513                 /*
1514                  * Make sure the single step/taken-branch trap bits
1515                  * are not set:
1516                  */
1517                 ia64_psr(pt)->ss = 0;
1518                 ia64_psr(pt)->tb = 0;
1519
1520                 wake_up_process(child);
1521                 ret = 0;
1522                 goto out_tsk;
1523
1524               case PTRACE_KILL:
1525                 /*
1526                  * Make the child exit.  Best I can do is send it a
1527                  * sigkill.  Perhaps it should be put in the status
1528                  * that it wants to exit.
1529                  */
1530                 if (child->exit_state == EXIT_ZOMBIE)
1531                         /* already dead */
1532                         goto out_tsk;
1533                 child->exit_code = SIGKILL;
1534
1535                 ptrace_disable(child);
1536                 wake_up_process(child);
1537                 ret = 0;
1538                 goto out_tsk;
1539
1540               case PTRACE_SINGLESTEP:
1541                 /* let child execute for one instruction */
1542               case PTRACE_SINGLEBLOCK:
1543                 ret = -EIO;
1544                 if (!valid_signal(data))
1545                         goto out_tsk;
1546
1547                 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1548                 if (request == PTRACE_SINGLESTEP) {
1549                         ia64_psr(pt)->ss = 1;
1550                 } else {
1551                         ia64_psr(pt)->tb = 1;
1552                 }
1553                 child->exit_code = data;
1554
1555                 /* give it a chance to run. */
1556                 wake_up_process(child);
1557                 ret = 0;
1558                 goto out_tsk;
1559
1560               case PTRACE_DETACH:
1561                 /* detach a process that was attached. */
1562                 ret = ptrace_detach(child, data);
1563                 goto out_tsk;
1564
1565               case PTRACE_GETREGS:
1566                 ret = ptrace_getregs(child,
1567                                      (struct pt_all_user_regs __user *) data);
1568                 goto out_tsk;
1569
1570               case PTRACE_SETREGS:
1571                 ret = ptrace_setregs(child,
1572                                      (struct pt_all_user_regs __user *) data);
1573                 goto out_tsk;
1574
1575               default:
1576                 ret = ptrace_request(child, request, addr, data);
1577                 goto out_tsk;
1578         }
1579   out_tsk:
1580         put_task_struct(child);
1581   out:
1582         unlock_kernel();
1583         return ret;
1584 }
1585
1586
1587 void
1588 syscall_trace (void)
1589 {
1590         if (!test_thread_flag(TIF_SYSCALL_TRACE))
1591                 return;
1592         if (!(current->ptrace & PT_PTRACED))
1593                 return;
1594         /*
1595          * The 0x80 provides a way for the tracing parent to
1596          * distinguish between a syscall stop and SIGTRAP delivery.
1597          */
1598         ptrace_notify(SIGTRAP
1599                       | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0));
1600
1601         /*
1602          * This isn't the same as continuing with a signal, but it
1603          * will do for normal use.  strace only continues with a
1604          * signal if the stopping signal is not SIGTRAP.  -brl
1605          */
1606         if (current->exit_code) {
1607                 send_sig(current->exit_code, current, 1);
1608                 current->exit_code = 0;
1609         }
1610 }
1611
1612 /* "asmlinkage" so the input arguments are preserved... */
1613
1614 asmlinkage void
1615 syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
1616                      long arg4, long arg5, long arg6, long arg7,
1617                      struct pt_regs regs)
1618 {
1619         if (test_thread_flag(TIF_SYSCALL_TRACE)
1620             && (current->ptrace & PT_PTRACED))
1621                 syscall_trace();
1622
1623         if (unlikely(current->audit_context)) {
1624                 long syscall;
1625                 int arch;
1626
1627                 if (IS_IA32_PROCESS(&regs)) {
1628                         syscall = regs.r1;
1629                         arch = AUDIT_ARCH_I386;
1630                 } else {
1631                         syscall = regs.r15;
1632                         arch = AUDIT_ARCH_IA64;
1633                 }
1634
1635                 audit_syscall_entry(current, arch, syscall, arg0, arg1, arg2, arg3);
1636         }
1637
1638 }
1639
1640 /* "asmlinkage" so the input arguments are preserved... */
1641
1642 asmlinkage void
1643 syscall_trace_leave (long arg0, long arg1, long arg2, long arg3,
1644                      long arg4, long arg5, long arg6, long arg7,
1645                      struct pt_regs regs)
1646 {
1647         if (unlikely(current->audit_context))
1648                 audit_syscall_exit(current, AUDITSC_RESULT(regs.r10), regs.r8);
1649
1650         if (test_thread_flag(TIF_SYSCALL_TRACE)
1651             && (current->ptrace & PT_PTRACED))
1652                 syscall_trace();
1653 }