arch/blackfin/mach-common/cpufreq.c

   1 /*
   2  * Blackfin core clock scaling
   3  *
   4  * Copyright 2008-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/init.h>
  12 #include <linux/cpufreq.h>
  13 #include <linux/fs.h>
  14 #include <asm/blackfin.h>
  15 #include <asm/time.h>
  16 #include <asm/dpmc.h>
  17
  18 #define CPUFREQ_CPU 0
  19
  20 /* this is the table of CCLK frequencies, in Hz */
  21 /* .index is the entry in the auxillary dpm_state_table[] */
  22 static struct cpufreq_frequency_table bfin_freq_table[] = {
  23         {
  24                 .frequency = CPUFREQ_TABLE_END,
  25                 .index = 0,
  26         },
  27         {
  28                 .frequency = CPUFREQ_TABLE_END,
  29                 .index = 1,
  30         },
  31         {
  32                 .frequency = CPUFREQ_TABLE_END,
  33                 .index = 2,
  34         },
  35         {
  36                 .frequency = CPUFREQ_TABLE_END,
  37                 .index = 0,
  38         },
  39 };
  40
  41 static struct bfin_dpm_state {
  42         unsigned int csel; /* system clock divider */
  43         unsigned int tscale; /* change the divider on the core timer interrupt */
  44 } dpm_state_table[3];
  45
  46 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
  47 /*
  48  * normalized to maximum frequncy offset for CYCLES,
  49  * used in time-ts cycles clock source, but could be used
  50  * somewhere also.
  51  */
  52 unsigned long long __bfin_cycles_off;
  53 unsigned int __bfin_cycles_mod;
  54 #endif
  55
  56 /**************************************************************************/
  57 static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
  58 {
  59
  60         unsigned long csel, min_cclk;
  61         int index;
  62
  63         /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
  64 #if ANOMALY_05000273 || ANOMALY_05000274 || \
  65         (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
  66         min_cclk = sclk * 2;
  67 #else
  68         min_cclk = sclk;
  69 #endif
  70         csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
  71
  72         for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
  73                 bfin_freq_table[index].frequency = cclk >> index;
  74                 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
  75                 dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
  76
  77                 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
  78                                                  bfin_freq_table[index].frequency,
  79                                                  dpm_state_table[index].csel,
  80                                                  dpm_state_table[index].tscale);
  81         }
  82         return;
  83 }
  84
  85 static void bfin_adjust_core_timer(void *info)
  86 {
  87         unsigned int tscale;
  88         unsigned int index = *(unsigned int *)info;
  89
  90         /* we have to adjust the core timer, because it is using cclk */
  91         tscale = dpm_state_table[index].tscale;
  92         bfin_write_TSCALE(tscale);
  93         return;
  94 }
  95
  96 static unsigned int bfin_getfreq_khz(unsigned int cpu)
  97 {
  98         /* Both CoreA/B have the same core clock */
  99         return get_cclk() / 1000;
 100 }
 101
 102
 103 static int bfin_target(struct cpufreq_policy *poli,
 104                         unsigned int target_freq, unsigned int relation)
 105 {
 106         unsigned int index, plldiv, cpu;
 107         unsigned long flags, cclk_hz;
 108         struct cpufreq_freqs freqs;
 109 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 110         cycles_t cycles;
 111 #endif
 112
 113         for_each_online_cpu(cpu) {
 114                 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
 115
 116                 if (!policy)
 117                         continue;
 118
 119                 if (cpufreq_frequency_table_target(policy, bfin_freq_table,
 120                                  target_freq, relation, &index))
 121                         return -EINVAL;
 122
 123                 cclk_hz = bfin_freq_table[index].frequency;
 124
 125                 freqs.old = bfin_getfreq_khz(0);
 126                 freqs.new = cclk_hz;
 127                 freqs.cpu = cpu;
 128
 129                 pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
 130                          cclk_hz, target_freq, freqs.old);
 131
 132                 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 133                 if (cpu == CPUFREQ_CPU) {
 134                         local_irq_save_hw(flags);
 135                         plldiv = (bfin_read_PLL_DIV() & SSEL) |
 136                                                 dpm_state_table[index].csel;
 137                         bfin_write_PLL_DIV(plldiv);
 138                         on_each_cpu(bfin_adjust_core_timer, &index, 1);
 139 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 140                         cycles = get_cycles();
 141                         SSYNC();
 142                         cycles += 10; /* ~10 cycles we lose after get_cycles() */
 143                         __bfin_cycles_off +=
 144                             (cycles << __bfin_cycles_mod) - (cycles << index);
 145                         __bfin_cycles_mod = index;
 146 #endif
 147                         local_irq_restore_hw(flags);
 148                 }
 149                 /* TODO: just test case for cycles clock source, remove later */
 150                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 151         }
 152
 153         pr_debug("cpufreq: done\n");
 154         return 0;
 155 }
 156
 157 static int bfin_verify_speed(struct cpufreq_policy *policy)
 158 {
 159         return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 160 }
 161
 162 static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
 163 {
 164
 165         unsigned long cclk, sclk;
 166
 167         cclk = get_cclk() / 1000;
 168         sclk = get_sclk() / 1000;
 169
 170         if (policy->cpu == CPUFREQ_CPU)
 171                 bfin_init_tables(cclk, sclk);
 172
 173         policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
 174
 175         policy->cur = cclk;
 176         cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
 177         return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
 178 }
 179
 180 static struct freq_attr *bfin_freq_attr[] = {
 181         &cpufreq_freq_attr_scaling_available_freqs,
 182         NULL,
 183 };
 184
 185 static struct cpufreq_driver bfin_driver = {
 186         .verify = bfin_verify_speed,
 187         .target = bfin_target,
 188         .get = bfin_getfreq_khz,
 189         .init = __bfin_cpu_init,
 190         .name = "bfin cpufreq",
 191         .owner = THIS_MODULE,
 192         .attr = bfin_freq_attr,
 193 };
 194
 195 static int __init bfin_cpu_init(void)
 196 {
 197         return cpufreq_register_driver(&bfin_driver);
 198 }
 199
 200 static void __exit bfin_cpu_exit(void)
 201 {
 202         cpufreq_unregister_driver(&bfin_driver);
 203 }
 204
 205 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 206 MODULE_DESCRIPTION("cpufreq driver for Blackfin");
 207 MODULE_LICENSE("GPL");
 208
 209 module_init(bfin_cpu_init);
 210 module_exit(bfin_cpu_exit);