arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27
  28 #include <plat/dma.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/omap_device.h>
  31 #include <linux/pm_runtime.h>
  32
  33 /* XXX These "sideways" includes are a sign that something is wrong */
  34 #include "../mach-omap2/cm2xxx_3xxx.h"
  35 #include "../mach-omap2/cm-regbits-34xx.h"
  36
  37 struct omap_mcbsp **mcbsp_ptr;
  38 int omap_mcbsp_count, omap_mcbsp_cache_size;
  39
  40 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  41 {
  42         if (cpu_class_is_omap1()) {
  43                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  44                 __raw_writew((u16)val, mcbsp->io_base + reg);
  45         } else if (cpu_is_omap2420()) {
  46                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  47                 __raw_writew((u16)val, mcbsp->io_base + reg);
  48         } else {
  49                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  50                 __raw_writel(val, mcbsp->io_base + reg);
  51         }
  52 }
  53
  54 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  55 {
  56         if (cpu_class_is_omap1()) {
  57                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  58                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  59         } else if (cpu_is_omap2420()) {
  60                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  61                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  62         } else {
  63                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  64                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  65         }
  66 }
  67
  68 #ifdef CONFIG_ARCH_OMAP3
  69 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  70 {
  71         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  72 }
  73
  74 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  75 {
  76         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  77 }
  78 #endif
  79
  80 #define MCBSP_READ(mcbsp, reg) \
  81                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  82 #define MCBSP_WRITE(mcbsp, reg, val) \
  83                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  84 #define MCBSP_READ_CACHE(mcbsp, reg) \
  85                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  86
  87 #define MCBSP_ST_READ(mcbsp, reg) \
  88                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  89 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  90                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  91
  92 static void omap_mcbsp_dump_reg(u8 id)
  93 {
  94         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  95
  96         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  97         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  98                         MCBSP_READ(mcbsp, DRR2));
  99         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
 100                         MCBSP_READ(mcbsp, DRR1));
 101         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
 102                         MCBSP_READ(mcbsp, DXR2));
 103         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
 104                         MCBSP_READ(mcbsp, DXR1));
 105         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 106                         MCBSP_READ(mcbsp, SPCR2));
 107         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 108                         MCBSP_READ(mcbsp, SPCR1));
 109         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 110                         MCBSP_READ(mcbsp, RCR2));
 111         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 112                         MCBSP_READ(mcbsp, RCR1));
 113         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 114                         MCBSP_READ(mcbsp, XCR2));
 115         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 116                         MCBSP_READ(mcbsp, XCR1));
 117         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 118                         MCBSP_READ(mcbsp, SRGR2));
 119         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 120                         MCBSP_READ(mcbsp, SRGR1));
 121         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 122                         MCBSP_READ(mcbsp, PCR0));
 123         dev_dbg(mcbsp->dev, "***********************\n");
 124 }
 125
 126 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 127 {
 128         struct omap_mcbsp *mcbsp_tx = dev_id;
 129         u16 irqst_spcr2;
 130
 131         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 132         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 133
 134         if (irqst_spcr2 & XSYNC_ERR) {
 135                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 136                         irqst_spcr2);
 137                 /* Writing zero to XSYNC_ERR clears the IRQ */
 138                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 139         } else {
 140                 complete(&mcbsp_tx->tx_irq_completion);
 141         }
 142
 143         return IRQ_HANDLED;
 144 }
 145
 146 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 147 {
 148         struct omap_mcbsp *mcbsp_rx = dev_id;
 149         u16 irqst_spcr1;
 150
 151         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 152         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 153
 154         if (irqst_spcr1 & RSYNC_ERR) {
 155                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 156                         irqst_spcr1);
 157                 /* Writing zero to RSYNC_ERR clears the IRQ */
 158                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 159         } else {
 160                 complete(&mcbsp_rx->rx_irq_completion);
 161         }
 162
 163         return IRQ_HANDLED;
 164 }
 165
 166 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 167 {
 168         struct omap_mcbsp *mcbsp_dma_tx = data;
 169
 170         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 171                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
 172
 173         /* We can free the channels */
 174         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 175         mcbsp_dma_tx->dma_tx_lch = -1;
 176
 177         complete(&mcbsp_dma_tx->tx_dma_completion);
 178 }
 179
 180 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 181 {
 182         struct omap_mcbsp *mcbsp_dma_rx = data;
 183
 184         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 185                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
 186
 187         /* We can free the channels */
 188         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 189         mcbsp_dma_rx->dma_rx_lch = -1;
 190
 191         complete(&mcbsp_dma_rx->rx_dma_completion);
 192 }
 193
 194 /*
 195  * omap_mcbsp_config simply write a config to the
 196  * appropriate McBSP.
 197  * You either call this function or set the McBSP registers
 198  * by yourself before calling omap_mcbsp_start().
 199  */
 200 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 201 {
 202         struct omap_mcbsp *mcbsp;
 203
 204         if (!omap_mcbsp_check_valid_id(id)) {
 205                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 206                 return;
 207         }
 208         mcbsp = id_to_mcbsp_ptr(id);
 209
 210         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 211                         mcbsp->id, mcbsp->phys_base);
 212
 213         /* We write the given config */
 214         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 215         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 216         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 217         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 218         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 219         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 220         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 221         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 222         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 223         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 224         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 225         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 226                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 227                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 228         }
 229 }
 230 EXPORT_SYMBOL(omap_mcbsp_config);
 231
 232 #ifdef CONFIG_ARCH_OMAP3
 233 static struct omap_device *find_omap_device_by_dev(struct device *dev)
 234 {
 235         struct platform_device *pdev = container_of(dev,
 236                                         struct platform_device, dev);
 237         return container_of(pdev, struct omap_device, pdev);
 238 }
 239
 240 static void omap_st_on(struct omap_mcbsp *mcbsp)
 241 {
 242         unsigned int w;
 243         struct omap_device *od;
 244
 245         od = find_omap_device_by_dev(mcbsp->dev);
 246
 247         /*
 248          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 249          * are enabled or sidetones start sounding ugly.
 250          */
 251         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 252         w &= ~(1 << (mcbsp->id - 2));
 253         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 254
 255         /* Enable McBSP Sidetone */
 256         w = MCBSP_READ(mcbsp, SSELCR);
 257         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 258
 259         /* Enable Sidetone from Sidetone Core */
 260         w = MCBSP_ST_READ(mcbsp, SSELCR);
 261         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 262 }
 263
 264 static void omap_st_off(struct omap_mcbsp *mcbsp)
 265 {
 266         unsigned int w;
 267         struct omap_device *od;
 268
 269         od = find_omap_device_by_dev(mcbsp->dev);
 270
 271         w = MCBSP_ST_READ(mcbsp, SSELCR);
 272         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 273
 274         w = MCBSP_READ(mcbsp, SSELCR);
 275         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 276
 277         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 278         w |= 1 << (mcbsp->id - 2);
 279         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 280 }
 281
 282 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 283 {
 284         u16 val, i;
 285         struct omap_device *od;
 286
 287         od = find_omap_device_by_dev(mcbsp->dev);
 288
 289         val = MCBSP_ST_READ(mcbsp, SSELCR);
 290
 291         if (val & ST_COEFFWREN)
 292                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 293
 294         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 295
 296         for (i = 0; i < 128; i++)
 297                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 298
 299         i = 0;
 300
 301         val = MCBSP_ST_READ(mcbsp, SSELCR);
 302         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 303                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 304
 305         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 306
 307         if (i == 1000)
 308                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 309 }
 310
 311 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 312 {
 313         u16 w;
 314         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 315         struct omap_device *od;
 316
 317         od = find_omap_device_by_dev(mcbsp->dev);
 318
 319         w = MCBSP_ST_READ(mcbsp, SSELCR);
 320
 321         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 322                       ST_CH1GAIN(st_data->ch1gain));
 323 }
 324
 325 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 326 {
 327         struct omap_mcbsp *mcbsp;
 328         struct omap_mcbsp_st_data *st_data;
 329         int ret = 0;
 330
 331         if (!omap_mcbsp_check_valid_id(id)) {
 332                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 333                 return -ENODEV;
 334         }
 335
 336         mcbsp = id_to_mcbsp_ptr(id);
 337         st_data = mcbsp->st_data;
 338
 339         if (!st_data)
 340                 return -ENOENT;
 341
 342         spin_lock_irq(&mcbsp->lock);
 343         if (channel == 0)
 344                 st_data->ch0gain = chgain;
 345         else if (channel == 1)
 346                 st_data->ch1gain = chgain;
 347         else
 348                 ret = -EINVAL;
 349
 350         if (st_data->enabled)
 351                 omap_st_chgain(mcbsp);
 352         spin_unlock_irq(&mcbsp->lock);
 353
 354         return ret;
 355 }
 356 EXPORT_SYMBOL(omap_st_set_chgain);
 357
 358 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 359 {
 360         struct omap_mcbsp *mcbsp;
 361         struct omap_mcbsp_st_data *st_data;
 362         int ret = 0;
 363
 364         if (!omap_mcbsp_check_valid_id(id)) {
 365                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 366                 return -ENODEV;
 367         }
 368
 369         mcbsp = id_to_mcbsp_ptr(id);
 370         st_data = mcbsp->st_data;
 371
 372         if (!st_data)
 373                 return -ENOENT;
 374
 375         spin_lock_irq(&mcbsp->lock);
 376         if (channel == 0)
 377                 *chgain = st_data->ch0gain;
 378         else if (channel == 1)
 379                 *chgain = st_data->ch1gain;
 380         else
 381                 ret = -EINVAL;
 382         spin_unlock_irq(&mcbsp->lock);
 383
 384         return ret;
 385 }
 386 EXPORT_SYMBOL(omap_st_get_chgain);
 387
 388 static int omap_st_start(struct omap_mcbsp *mcbsp)
 389 {
 390         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 391
 392         if (st_data && st_data->enabled && !st_data->running) {
 393                 omap_st_fir_write(mcbsp, st_data->taps);
 394                 omap_st_chgain(mcbsp);
 395
 396                 if (!mcbsp->free) {
 397                         omap_st_on(mcbsp);
 398                         st_data->running = 1;
 399                 }
 400         }
 401
 402         return 0;
 403 }
 404
 405 int omap_st_enable(unsigned int id)
 406 {
 407         struct omap_mcbsp *mcbsp;
 408         struct omap_mcbsp_st_data *st_data;
 409
 410         if (!omap_mcbsp_check_valid_id(id)) {
 411                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 412                 return -ENODEV;
 413         }
 414
 415         mcbsp = id_to_mcbsp_ptr(id);
 416         st_data = mcbsp->st_data;
 417
 418         if (!st_data)
 419                 return -ENODEV;
 420
 421         spin_lock_irq(&mcbsp->lock);
 422         st_data->enabled = 1;
 423         omap_st_start(mcbsp);
 424         spin_unlock_irq(&mcbsp->lock);
 425
 426         return 0;
 427 }
 428 EXPORT_SYMBOL(omap_st_enable);
 429
 430 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 431 {
 432         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 433
 434         if (st_data && st_data->running) {
 435                 if (!mcbsp->free) {
 436                         omap_st_off(mcbsp);
 437                         st_data->running = 0;
 438                 }
 439         }
 440
 441         return 0;
 442 }
 443
 444 int omap_st_disable(unsigned int id)
 445 {
 446         struct omap_mcbsp *mcbsp;
 447         struct omap_mcbsp_st_data *st_data;
 448         int ret = 0;
 449
 450         if (!omap_mcbsp_check_valid_id(id)) {
 451                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 452                 return -ENODEV;
 453         }
 454
 455         mcbsp = id_to_mcbsp_ptr(id);
 456         st_data = mcbsp->st_data;
 457
 458         if (!st_data)
 459                 return -ENODEV;
 460
 461         spin_lock_irq(&mcbsp->lock);
 462         omap_st_stop(mcbsp);
 463         st_data->enabled = 0;
 464         spin_unlock_irq(&mcbsp->lock);
 465
 466         return ret;
 467 }
 468 EXPORT_SYMBOL(omap_st_disable);
 469
 470 int omap_st_is_enabled(unsigned int id)
 471 {
 472         struct omap_mcbsp *mcbsp;
 473         struct omap_mcbsp_st_data *st_data;
 474
 475         if (!omap_mcbsp_check_valid_id(id)) {
 476                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 477                 return -ENODEV;
 478         }
 479
 480         mcbsp = id_to_mcbsp_ptr(id);
 481         st_data = mcbsp->st_data;
 482
 483         if (!st_data)
 484                 return -ENODEV;
 485
 486
 487         return st_data->enabled;
 488 }
 489 EXPORT_SYMBOL(omap_st_is_enabled);
 490
 491 /*
 492  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 493  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 494  * for the THRSH2 register.
 495  */
 496 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 497 {
 498         struct omap_mcbsp *mcbsp;
 499
 500         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 501                 return;
 502
 503         if (!omap_mcbsp_check_valid_id(id)) {
 504                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 505                 return;
 506         }
 507         mcbsp = id_to_mcbsp_ptr(id);
 508
 509         if (threshold && threshold <= mcbsp->max_tx_thres)
 510                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 511 }
 512 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 513
 514 /*
 515  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 516  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 517  * for the THRSH1 register.
 518  */
 519 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 520 {
 521         struct omap_mcbsp *mcbsp;
 522
 523         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 524                 return;
 525
 526         if (!omap_mcbsp_check_valid_id(id)) {
 527                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 528                 return;
 529         }
 530         mcbsp = id_to_mcbsp_ptr(id);
 531
 532         if (threshold && threshold <= mcbsp->max_rx_thres)
 533                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 534 }
 535 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 536
 537 /*
 538  * omap_mcbsp_get_max_tx_thres just return the current configured
 539  * maximum threshold for transmission
 540  */
 541 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 542 {
 543         struct omap_mcbsp *mcbsp;
 544
 545         if (!omap_mcbsp_check_valid_id(id)) {
 546                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 547                 return -ENODEV;
 548         }
 549         mcbsp = id_to_mcbsp_ptr(id);
 550
 551         return mcbsp->max_tx_thres;
 552 }
 553 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 554
 555 /*
 556  * omap_mcbsp_get_max_rx_thres just return the current configured
 557  * maximum threshold for reception
 558  */
 559 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 560 {
 561         struct omap_mcbsp *mcbsp;
 562
 563         if (!omap_mcbsp_check_valid_id(id)) {
 564                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 565                 return -ENODEV;
 566         }
 567         mcbsp = id_to_mcbsp_ptr(id);
 568
 569         return mcbsp->max_rx_thres;
 570 }
 571 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 572
 573 u16 omap_mcbsp_get_fifo_size(unsigned int id)
 574 {
 575         struct omap_mcbsp *mcbsp;
 576
 577         if (!omap_mcbsp_check_valid_id(id)) {
 578                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 579                 return -ENODEV;
 580         }
 581         mcbsp = id_to_mcbsp_ptr(id);
 582
 583         return mcbsp->pdata->buffer_size;
 584 }
 585 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
 586
 587 /*
 588  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 589  */
 590 u16 omap_mcbsp_get_tx_delay(unsigned int id)
 591 {
 592         struct omap_mcbsp *mcbsp;
 593         u16 buffstat;
 594
 595         if (!omap_mcbsp_check_valid_id(id)) {
 596                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 597                 return -ENODEV;
 598         }
 599         mcbsp = id_to_mcbsp_ptr(id);
 600
 601         /* Returns the number of free locations in the buffer */
 602         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 603
 604         /* Number of slots are different in McBSP ports */
 605         return mcbsp->pdata->buffer_size - buffstat;
 606 }
 607 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
 608
 609 /*
 610  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 611  * to reach the threshold value (when the DMA will be triggered to read it)
 612  */
 613 u16 omap_mcbsp_get_rx_delay(unsigned int id)
 614 {
 615         struct omap_mcbsp *mcbsp;
 616         u16 buffstat, threshold;
 617
 618         if (!omap_mcbsp_check_valid_id(id)) {
 619                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 620                 return -ENODEV;
 621         }
 622         mcbsp = id_to_mcbsp_ptr(id);
 623
 624         /* Returns the number of used locations in the buffer */
 625         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 626         /* RX threshold */
 627         threshold = MCBSP_READ(mcbsp, THRSH1);
 628
 629         /* Return the number of location till we reach the threshold limit */
 630         if (threshold <= buffstat)
 631                 return 0;
 632         else
 633                 return threshold - buffstat;
 634 }
 635 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
 636
 637 /*
 638  * omap_mcbsp_get_dma_op_mode just return the current configured
 639  * operating mode for the mcbsp channel
 640  */
 641 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 642 {
 643         struct omap_mcbsp *mcbsp;
 644         int dma_op_mode;
 645
 646         if (!omap_mcbsp_check_valid_id(id)) {
 647                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 648                 return -ENODEV;
 649         }
 650         mcbsp = id_to_mcbsp_ptr(id);
 651
 652         dma_op_mode = mcbsp->dma_op_mode;
 653
 654         return dma_op_mode;
 655 }
 656 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 657
 658 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 659 {
 660         struct omap_device *od;
 661
 662         od = find_omap_device_by_dev(mcbsp->dev);
 663         /*
 664          * Enable wakup behavior, smart idle and all wakeups
 665          * REVISIT: some wakeups may be unnecessary
 666          */
 667         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 668                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 669         }
 670 }
 671
 672 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 673 {
 674         struct omap_device *od;
 675
 676         od = find_omap_device_by_dev(mcbsp->dev);
 677
 678         /*
 679          * Disable wakup behavior, smart idle and all wakeups
 680          */
 681         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 682                 /*
 683                  * HW bug workaround - If no_idle mode is taken, we need to
 684                  * go to smart_idle before going to always_idle, or the
 685                  * device will not hit retention anymore.
 686                  */
 687
 688                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 689         }
 690 }
 691 #else
 692 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 693 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 694 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 695 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 696 #endif
 697
 698 /*
 699  * We can choose between IRQ based or polled IO.
 700  * This needs to be called before omap_mcbsp_request().
 701  */
 702 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 703 {
 704         struct omap_mcbsp *mcbsp;
 705
 706         if (!omap_mcbsp_check_valid_id(id)) {
 707                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 708                 return -ENODEV;
 709         }
 710         mcbsp = id_to_mcbsp_ptr(id);
 711
 712         spin_lock(&mcbsp->lock);
 713
 714         if (!mcbsp->free) {
 715                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 716                         mcbsp->id);
 717                 spin_unlock(&mcbsp->lock);
 718                 return -EINVAL;
 719         }
 720
 721         mcbsp->io_type = io_type;
 722
 723         spin_unlock(&mcbsp->lock);
 724
 725         return 0;
 726 }
 727 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 728
 729 int omap_mcbsp_request(unsigned int id)
 730 {
 731         struct omap_mcbsp *mcbsp;
 732         void *reg_cache;
 733         int err;
 734
 735         if (!omap_mcbsp_check_valid_id(id)) {
 736                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 737                 return -ENODEV;
 738         }
 739         mcbsp = id_to_mcbsp_ptr(id);
 740
 741         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 742         if (!reg_cache) {
 743                 return -ENOMEM;
 744         }
 745
 746         spin_lock(&mcbsp->lock);
 747         if (!mcbsp->free) {
 748                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 749                         mcbsp->id);
 750                 err = -EBUSY;
 751                 goto err_kfree;
 752         }
 753
 754         mcbsp->free = false;
 755         mcbsp->reg_cache = reg_cache;
 756         spin_unlock(&mcbsp->lock);
 757
 758         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 759                 mcbsp->pdata->ops->request(id);
 760
 761         pm_runtime_get_sync(mcbsp->dev);
 762
 763         /* Do procedure specific to omap34xx arch, if applicable */
 764         omap34xx_mcbsp_request(mcbsp);
 765
 766         /*
 767          * Make sure that transmitter, receiver and sample-rate generator are
 768          * not running before activating IRQs.
 769          */
 770         MCBSP_WRITE(mcbsp, SPCR1, 0);
 771         MCBSP_WRITE(mcbsp, SPCR2, 0);
 772
 773         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 774                 /* We need to get IRQs here */
 775                 init_completion(&mcbsp->tx_irq_completion);
 776                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 777                                         0, "McBSP", (void *)mcbsp);
 778                 if (err != 0) {
 779                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 780                                         "for McBSP%d\n", mcbsp->tx_irq,
 781                                         mcbsp->id);
 782                         goto err_clk_disable;
 783                 }
 784
 785                 if (mcbsp->rx_irq) {
 786                         init_completion(&mcbsp->rx_irq_completion);
 787                         err = request_irq(mcbsp->rx_irq,
 788                                         omap_mcbsp_rx_irq_handler,
 789                                         0, "McBSP", (void *)mcbsp);
 790                         if (err != 0) {
 791                                 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 792                                                 "for McBSP%d\n", mcbsp->rx_irq,
 793                                                 mcbsp->id);
 794                                 goto err_free_irq;
 795                         }
 796                 }
 797         }
 798
 799         return 0;
 800 err_free_irq:
 801         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 802 err_clk_disable:
 803         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 804                 mcbsp->pdata->ops->free(id);
 805
 806         /* Do procedure specific to omap34xx arch, if applicable */
 807         omap34xx_mcbsp_free(mcbsp);
 808
 809         pm_runtime_put_sync(mcbsp->dev);
 810
 811         spin_lock(&mcbsp->lock);
 812         mcbsp->free = true;
 813         mcbsp->reg_cache = NULL;
 814 err_kfree:
 815         spin_unlock(&mcbsp->lock);
 816         kfree(reg_cache);
 817
 818         return err;
 819 }
 820 EXPORT_SYMBOL(omap_mcbsp_request);
 821
 822 void omap_mcbsp_free(unsigned int id)
 823 {
 824         struct omap_mcbsp *mcbsp;
 825         void *reg_cache;
 826
 827         if (!omap_mcbsp_check_valid_id(id)) {
 828                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 829                 return;
 830         }
 831         mcbsp = id_to_mcbsp_ptr(id);
 832
 833         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 834                 mcbsp->pdata->ops->free(id);
 835
 836         /* Do procedure specific to omap34xx arch, if applicable */
 837         omap34xx_mcbsp_free(mcbsp);
 838
 839         pm_runtime_put_sync(mcbsp->dev);
 840
 841         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 842                 /* Free IRQs */
 843                 if (mcbsp->rx_irq)
 844                         free_irq(mcbsp->rx_irq, (void *)mcbsp);
 845                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 846         }
 847
 848         reg_cache = mcbsp->reg_cache;
 849
 850         spin_lock(&mcbsp->lock);
 851         if (mcbsp->free)
 852                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 853         else
 854                 mcbsp->free = true;
 855         mcbsp->reg_cache = NULL;
 856         spin_unlock(&mcbsp->lock);
 857
 858         if (reg_cache)
 859                 kfree(reg_cache);
 860 }
 861 EXPORT_SYMBOL(omap_mcbsp_free);
 862
 863 /*
 864  * Here we start the McBSP, by enabling transmitter, receiver or both.
 865  * If no transmitter or receiver is active prior calling, then sample-rate
 866  * generator and frame sync are started.
 867  */
 868 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 869 {
 870         struct omap_mcbsp *mcbsp;
 871         int enable_srg = 0;
 872         u16 w;
 873
 874         if (!omap_mcbsp_check_valid_id(id)) {
 875                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 876                 return;
 877         }
 878         mcbsp = id_to_mcbsp_ptr(id);
 879
 880         if (cpu_is_omap34xx())
 881                 omap_st_start(mcbsp);
 882
 883         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
 884         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 885
 886         /* Only enable SRG, if McBSP is master */
 887         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 888         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 889                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 890                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 891
 892         if (enable_srg) {
 893                 /* Start the sample generator */
 894                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 895                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 896         }
 897
 898         /* Enable transmitter and receiver */
 899         tx &= 1;
 900         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 901         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 902
 903         rx &= 1;
 904         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 905         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 906
 907         /*
 908          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 909          * REVISIT: 100us may give enough time for two CLKSRG, however
 910          * due to some unknown PM related, clock gating etc. reason it
 911          * is now at 500us.
 912          */
 913         udelay(500);
 914
 915         if (enable_srg) {
 916                 /* Start frame sync */
 917                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 918                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 919         }
 920
 921         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 922                 /* Release the transmitter and receiver */
 923                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 924                 w &= ~(tx ? XDISABLE : 0);
 925                 MCBSP_WRITE(mcbsp, XCCR, w);
 926                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 927                 w &= ~(rx ? RDISABLE : 0);
 928                 MCBSP_WRITE(mcbsp, RCCR, w);
 929         }
 930
 931         /* Dump McBSP Regs */
 932         omap_mcbsp_dump_reg(id);
 933 }
 934 EXPORT_SYMBOL(omap_mcbsp_start);
 935
 936 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 937 {
 938         struct omap_mcbsp *mcbsp;
 939         int idle;
 940         u16 w;
 941
 942         if (!omap_mcbsp_check_valid_id(id)) {
 943                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 944                 return;
 945         }
 946
 947         mcbsp = id_to_mcbsp_ptr(id);
 948
 949         /* Reset transmitter */
 950         tx &= 1;
 951         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 952                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 953                 w |= (tx ? XDISABLE : 0);
 954                 MCBSP_WRITE(mcbsp, XCCR, w);
 955         }
 956         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 957         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 958
 959         /* Reset receiver */
 960         rx &= 1;
 961         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 962                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 963                 w |= (rx ? RDISABLE : 0);
 964                 MCBSP_WRITE(mcbsp, RCCR, w);
 965         }
 966         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 967         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 968
 969         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 970                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 971
 972         if (idle) {
 973                 /* Reset the sample rate generator */
 974                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 975                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 976         }
 977
 978         if (cpu_is_omap34xx())
 979                 omap_st_stop(mcbsp);
 980 }
 981 EXPORT_SYMBOL(omap_mcbsp_stop);
 982
 983 /* polled mcbsp i/o operations */
 984 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 985 {
 986         struct omap_mcbsp *mcbsp;
 987
 988         if (!omap_mcbsp_check_valid_id(id)) {
 989                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 990                 return -ENODEV;
 991         }
 992
 993         mcbsp = id_to_mcbsp_ptr(id);
 994
 995         MCBSP_WRITE(mcbsp, DXR1, buf);
 996         /* if frame sync error - clear the error */
 997         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
 998                 /* clear error */
 999                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1000                 /* resend */
1001                 return -1;
1002         } else {
1003                 /* wait for transmit confirmation */
1004                 int attemps = 0;
1005                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1006                         if (attemps++ > 1000) {
1007                                 MCBSP_WRITE(mcbsp, SPCR2,
1008                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1009                                                 (~XRST));
1010                                 udelay(10);
1011                                 MCBSP_WRITE(mcbsp, SPCR2,
1012                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1013                                                 (XRST));
1014                                 udelay(10);
1015                                 dev_err(mcbsp->dev, "Could not write to"
1016                                         " McBSP%d Register\n", mcbsp->id);
1017                                 return -2;
1018                         }
1019                 }
1020         }
1021
1022         return 0;
1023 }
1024 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1025
1026 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1027 {
1028         struct omap_mcbsp *mcbsp;
1029
1030         if (!omap_mcbsp_check_valid_id(id)) {
1031                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1032                 return -ENODEV;
1033         }
1034         mcbsp = id_to_mcbsp_ptr(id);
1035
1036         /* if frame sync error - clear the error */
1037         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1038                 /* clear error */
1039                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1040                 /* resend */
1041                 return -1;
1042         } else {
1043                 /* wait for recieve confirmation */
1044                 int attemps = 0;
1045                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1046                         if (attemps++ > 1000) {
1047                                 MCBSP_WRITE(mcbsp, SPCR1,
1048                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1049                                                 (~RRST));
1050                                 udelay(10);
1051                                 MCBSP_WRITE(mcbsp, SPCR1,
1052                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1053                                                 (RRST));
1054                                 udelay(10);
1055                                 dev_err(mcbsp->dev, "Could not read from"
1056                                         " McBSP%d Register\n", mcbsp->id);
1057                                 return -2;
1058                         }
1059                 }
1060         }
1061         *buf = MCBSP_READ(mcbsp, DRR1);
1062
1063         return 0;
1064 }
1065 EXPORT_SYMBOL(omap_mcbsp_pollread);
1066
1067 /*
1068  * IRQ based word transmission.
1069  */
1070 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1071 {
1072         struct omap_mcbsp *mcbsp;
1073         omap_mcbsp_word_length word_length;
1074
1075         if (!omap_mcbsp_check_valid_id(id)) {
1076                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1077                 return;
1078         }
1079
1080         mcbsp = id_to_mcbsp_ptr(id);
1081         word_length = mcbsp->tx_word_length;
1082
1083         wait_for_completion(&mcbsp->tx_irq_completion);
1084
1085         if (word_length > OMAP_MCBSP_WORD_16)
1086                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1087         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1088 }
1089 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1090
1091 u32 omap_mcbsp_recv_word(unsigned int id)
1092 {
1093         struct omap_mcbsp *mcbsp;
1094         u16 word_lsb, word_msb = 0;
1095         omap_mcbsp_word_length word_length;
1096
1097         if (!omap_mcbsp_check_valid_id(id)) {
1098                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1099                 return -ENODEV;
1100         }
1101         mcbsp = id_to_mcbsp_ptr(id);
1102
1103         word_length = mcbsp->rx_word_length;
1104
1105         wait_for_completion(&mcbsp->rx_irq_completion);
1106
1107         if (word_length > OMAP_MCBSP_WORD_16)
1108                 word_msb = MCBSP_READ(mcbsp, DRR2);
1109         word_lsb = MCBSP_READ(mcbsp, DRR1);
1110
1111         return (word_lsb | (word_msb << 16));
1112 }
1113 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1114
1115 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1116 {
1117         struct omap_mcbsp *mcbsp;
1118         omap_mcbsp_word_length tx_word_length;
1119         omap_mcbsp_word_length rx_word_length;
1120         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1121
1122         if (!omap_mcbsp_check_valid_id(id)) {
1123                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1124                 return -ENODEV;
1125         }
1126         mcbsp = id_to_mcbsp_ptr(id);
1127         tx_word_length = mcbsp->tx_word_length;
1128         rx_word_length = mcbsp->rx_word_length;
1129
1130         if (tx_word_length != rx_word_length)
1131                 return -EINVAL;
1132
1133         /* First we wait for the transmitter to be ready */
1134         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1135         while (!(spcr2 & XRDY)) {
1136                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1137                 if (attempts++ > 1000) {
1138                         /* We must reset the transmitter */
1139                         MCBSP_WRITE(mcbsp, SPCR2,
1140                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1141                         udelay(10);
1142                         MCBSP_WRITE(mcbsp, SPCR2,
1143                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1144                         udelay(10);
1145                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1146                                 "ready\n", mcbsp->id);
1147                         return -EAGAIN;
1148                 }
1149         }
1150
1151         /* Now we can push the data */
1152         if (tx_word_length > OMAP_MCBSP_WORD_16)
1153                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1154         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1155
1156         /* We wait for the receiver to be ready */
1157         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1158         while (!(spcr1 & RRDY)) {
1159                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1160                 if (attempts++ > 1000) {
1161                         /* We must reset the receiver */
1162                         MCBSP_WRITE(mcbsp, SPCR1,
1163                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1164                         udelay(10);
1165                         MCBSP_WRITE(mcbsp, SPCR1,
1166                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1167                         udelay(10);
1168                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1169                                 "ready\n", mcbsp->id);
1170                         return -EAGAIN;
1171                 }
1172         }
1173
1174         /* Receiver is ready, let's read the dummy data */
1175         if (rx_word_length > OMAP_MCBSP_WORD_16)
1176                 word_msb = MCBSP_READ(mcbsp, DRR2);
1177         word_lsb = MCBSP_READ(mcbsp, DRR1);
1178
1179         return 0;
1180 }
1181 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1182
1183 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1184 {
1185         struct omap_mcbsp *mcbsp;
1186         u32 clock_word = 0;
1187         omap_mcbsp_word_length tx_word_length;
1188         omap_mcbsp_word_length rx_word_length;
1189         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1190
1191         if (!omap_mcbsp_check_valid_id(id)) {
1192                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1193                 return -ENODEV;
1194         }
1195
1196         mcbsp = id_to_mcbsp_ptr(id);
1197
1198         tx_word_length = mcbsp->tx_word_length;
1199         rx_word_length = mcbsp->rx_word_length;
1200
1201         if (tx_word_length != rx_word_length)
1202                 return -EINVAL;
1203
1204         /* First we wait for the transmitter to be ready */
1205         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1206         while (!(spcr2 & XRDY)) {
1207                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1208                 if (attempts++ > 1000) {
1209                         /* We must reset the transmitter */
1210                         MCBSP_WRITE(mcbsp, SPCR2,
1211                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1212                         udelay(10);
1213                         MCBSP_WRITE(mcbsp, SPCR2,
1214                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1215                         udelay(10);
1216                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1217                                 "ready\n", mcbsp->id);
1218                         return -EAGAIN;
1219                 }
1220         }
1221
1222         /* We first need to enable the bus clock */
1223         if (tx_word_length > OMAP_MCBSP_WORD_16)
1224                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1225         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1226
1227         /* We wait for the receiver to be ready */
1228         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1229         while (!(spcr1 & RRDY)) {
1230                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1231                 if (attempts++ > 1000) {
1232                         /* We must reset the receiver */
1233                         MCBSP_WRITE(mcbsp, SPCR1,
1234                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1235                         udelay(10);
1236                         MCBSP_WRITE(mcbsp, SPCR1,
1237                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1238                         udelay(10);
1239                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1240                                 "ready\n", mcbsp->id);
1241                         return -EAGAIN;
1242                 }
1243         }
1244
1245         /* Receiver is ready, there is something for us */
1246         if (rx_word_length > OMAP_MCBSP_WORD_16)
1247                 word_msb = MCBSP_READ(mcbsp, DRR2);
1248         word_lsb = MCBSP_READ(mcbsp, DRR1);
1249
1250         word[0] = (word_lsb | (word_msb << 16));
1251
1252         return 0;
1253 }
1254 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1255
1256 /*
1257  * Simple DMA based buffer rx/tx routines.
1258  * Nothing fancy, just a single buffer tx/rx through DMA.
1259  * The DMA resources are released once the transfer is done.
1260  * For anything fancier, you should use your own customized DMA
1261  * routines and callbacks.
1262  */
1263 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1264                                 unsigned int length)
1265 {
1266         struct omap_mcbsp *mcbsp;
1267         int dma_tx_ch;
1268         int src_port = 0;
1269         int dest_port = 0;
1270         int sync_dev = 0;
1271
1272         if (!omap_mcbsp_check_valid_id(id)) {
1273                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1274                 return -ENODEV;
1275         }
1276         mcbsp = id_to_mcbsp_ptr(id);
1277
1278         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1279                                 omap_mcbsp_tx_dma_callback,
1280                                 mcbsp,
1281                                 &dma_tx_ch)) {
1282                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1283                                 "McBSP%d TX. Trying IRQ based TX\n",
1284                                 mcbsp->id);
1285                 return -EAGAIN;
1286         }
1287         mcbsp->dma_tx_lch = dma_tx_ch;
1288
1289         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1290                 dma_tx_ch);
1291
1292         init_completion(&mcbsp->tx_dma_completion);
1293
1294         if (cpu_class_is_omap1()) {
1295                 src_port = OMAP_DMA_PORT_TIPB;
1296                 dest_port = OMAP_DMA_PORT_EMIFF;
1297         }
1298         if (cpu_class_is_omap2())
1299                 sync_dev = mcbsp->dma_tx_sync;
1300
1301         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1302                                      OMAP_DMA_DATA_TYPE_S16,
1303                                      length >> 1, 1,
1304                                      OMAP_DMA_SYNC_ELEMENT,
1305          sync_dev, 0);
1306
1307         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1308                                  src_port,
1309                                  OMAP_DMA_AMODE_CONSTANT,
1310                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1311                                  0, 0);
1312
1313         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1314                                 dest_port,
1315                                 OMAP_DMA_AMODE_POST_INC,
1316                                 buffer,
1317                                 0, 0);
1318
1319         omap_start_dma(mcbsp->dma_tx_lch);
1320         wait_for_completion(&mcbsp->tx_dma_completion);
1321
1322         return 0;
1323 }
1324 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1325
1326 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1327                                 unsigned int length)
1328 {
1329         struct omap_mcbsp *mcbsp;
1330         int dma_rx_ch;
1331         int src_port = 0;
1332         int dest_port = 0;
1333         int sync_dev = 0;
1334
1335         if (!omap_mcbsp_check_valid_id(id)) {
1336                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1337                 return -ENODEV;
1338         }
1339         mcbsp = id_to_mcbsp_ptr(id);
1340
1341         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1342                                 omap_mcbsp_rx_dma_callback,
1343                                 mcbsp,
1344                                 &dma_rx_ch)) {
1345                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1346                                 "McBSP%d RX. Trying IRQ based RX\n",
1347                                 mcbsp->id);
1348                 return -EAGAIN;
1349         }
1350         mcbsp->dma_rx_lch = dma_rx_ch;
1351
1352         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1353                 dma_rx_ch);
1354
1355         init_completion(&mcbsp->rx_dma_completion);
1356
1357         if (cpu_class_is_omap1()) {
1358                 src_port = OMAP_DMA_PORT_TIPB;
1359                 dest_port = OMAP_DMA_PORT_EMIFF;
1360         }
1361         if (cpu_class_is_omap2())
1362                 sync_dev = mcbsp->dma_rx_sync;
1363
1364         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1365                                         OMAP_DMA_DATA_TYPE_S16,
1366                                         length >> 1, 1,
1367                                         OMAP_DMA_SYNC_ELEMENT,
1368                                         sync_dev, 0);
1369
1370         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1371                                 src_port,
1372                                 OMAP_DMA_AMODE_CONSTANT,
1373                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1374                                 0, 0);
1375
1376         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1377                                         dest_port,
1378                                         OMAP_DMA_AMODE_POST_INC,
1379                                         buffer,
1380                                         0, 0);
1381
1382         omap_start_dma(mcbsp->dma_rx_lch);
1383         wait_for_completion(&mcbsp->rx_dma_completion);
1384
1385         return 0;
1386 }
1387 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1388
1389 /*
1390  * SPI wrapper.
1391  * Since SPI setup is much simpler than the generic McBSP one,
1392  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1393  * Once this is done, you can call omap_mcbsp_start().
1394  */
1395 void omap_mcbsp_set_spi_mode(unsigned int id,
1396                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1397 {
1398         struct omap_mcbsp *mcbsp;
1399         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1400
1401         if (!omap_mcbsp_check_valid_id(id)) {
1402                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1403                 return;
1404         }
1405         mcbsp = id_to_mcbsp_ptr(id);
1406
1407         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1408
1409         /* SPI has only one frame */
1410         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1411         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1412
1413         /* Clock stop mode */
1414         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1415                 mcbsp_cfg.spcr1 |= (1 << 12);
1416         else
1417                 mcbsp_cfg.spcr1 |= (3 << 11);
1418
1419         /* Set clock parities */
1420         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1421                 mcbsp_cfg.pcr0 |= CLKRP;
1422         else
1423                 mcbsp_cfg.pcr0 &= ~CLKRP;
1424
1425         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1426                 mcbsp_cfg.pcr0 &= ~CLKXP;
1427         else
1428                 mcbsp_cfg.pcr0 |= CLKXP;
1429
1430         /* Set SCLKME to 0 and CLKSM to 1 */
1431         mcbsp_cfg.pcr0 &= ~SCLKME;
1432         mcbsp_cfg.srgr2 |= CLKSM;
1433
1434         /* Set FSXP */
1435         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1436                 mcbsp_cfg.pcr0 &= ~FSXP;
1437         else
1438                 mcbsp_cfg.pcr0 |= FSXP;
1439
1440         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1441                 mcbsp_cfg.pcr0 |= CLKXM;
1442                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1443                 mcbsp_cfg.pcr0 |= FSXM;
1444                 mcbsp_cfg.srgr2 &= ~FSGM;
1445                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1446                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1447         } else {
1448                 mcbsp_cfg.pcr0 &= ~CLKXM;
1449                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1450                 mcbsp_cfg.pcr0 &= ~FSXM;
1451                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1452                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1453         }
1454
1455         mcbsp_cfg.xcr2 &= ~XPHASE;
1456         mcbsp_cfg.rcr2 &= ~RPHASE;
1457
1458         omap_mcbsp_config(id, &mcbsp_cfg);
1459 }
1460 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1461
1462 #ifdef CONFIG_ARCH_OMAP3
1463 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1464 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1465 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1466 static ssize_t prop##_show(struct device *dev,                          \
1467                         struct device_attribute *attr, char *buf)       \
1468 {                                                                       \
1469         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1470                                                                         \
1471         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1472 }                                                                       \
1473                                                                         \
1474 static ssize_t prop##_store(struct device *dev,                         \
1475                                 struct device_attribute *attr,          \
1476                                 const char *buf, size_t size)           \
1477 {                                                                       \
1478         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1479         unsigned long val;                                              \
1480         int status;                                                     \
1481                                                                         \
1482         status = strict_strtoul(buf, 0, &val);                          \
1483         if (status)                                                     \
1484                 return status;                                          \
1485                                                                         \
1486         if (!valid_threshold(mcbsp, val))                               \
1487                 return -EDOM;                                           \
1488                                                                         \
1489         mcbsp->prop = val;                                              \
1490         return size;                                                    \
1491 }                                                                       \
1492                                                                         \
1493 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1494
1495 THRESHOLD_PROP_BUILDER(max_tx_thres);
1496 THRESHOLD_PROP_BUILDER(max_rx_thres);
1497
1498 static const char *dma_op_modes[] = {
1499         "element", "threshold", "frame",
1500 };
1501
1502 static ssize_t dma_op_mode_show(struct device *dev,
1503                         struct device_attribute *attr, char *buf)
1504 {
1505         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1506         int dma_op_mode, i = 0;
1507         ssize_t len = 0;
1508         const char * const *s;
1509
1510         dma_op_mode = mcbsp->dma_op_mode;
1511
1512         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1513                 if (dma_op_mode == i)
1514                         len += sprintf(buf + len, "[%s] ", *s);
1515                 else
1516                         len += sprintf(buf + len, "%s ", *s);
1517         }
1518         len += sprintf(buf + len, "\n");
1519
1520         return len;
1521 }
1522
1523 static ssize_t dma_op_mode_store(struct device *dev,
1524                                 struct device_attribute *attr,
1525                                 const char *buf, size_t size)
1526 {
1527         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1528         const char * const *s;
1529         int i = 0;
1530
1531         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1532                 if (sysfs_streq(buf, *s))
1533                         break;
1534
1535         if (i == ARRAY_SIZE(dma_op_modes))
1536                 return -EINVAL;
1537
1538         spin_lock_irq(&mcbsp->lock);
1539         if (!mcbsp->free) {
1540                 size = -EBUSY;
1541                 goto unlock;
1542         }
1543         mcbsp->dma_op_mode = i;
1544
1545 unlock:
1546         spin_unlock_irq(&mcbsp->lock);
1547
1548         return size;
1549 }
1550
1551 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1552
1553 static ssize_t st_taps_show(struct device *dev,
1554                             struct device_attribute *attr, char *buf)
1555 {
1556         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1557         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1558         ssize_t status = 0;
1559         int i;
1560
1561         spin_lock_irq(&mcbsp->lock);
1562         for (i = 0; i < st_data->nr_taps; i++)
1563                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1564                                   st_data->taps[i]);
1565         if (i)
1566                 status += sprintf(&buf[status], "\n");
1567         spin_unlock_irq(&mcbsp->lock);
1568
1569         return status;
1570 }
1571
1572 static ssize_t st_taps_store(struct device *dev,
1573                              struct device_attribute *attr,
1574                              const char *buf, size_t size)
1575 {
1576         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1577         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1578         int val, tmp, status, i = 0;
1579
1580         spin_lock_irq(&mcbsp->lock);
1581         memset(st_data->taps, 0, sizeof(st_data->taps));
1582         st_data->nr_taps = 0;
1583
1584         do {
1585                 status = sscanf(buf, "%d%n", &val, &tmp);
1586                 if (status < 0 || status == 0) {
1587                         size = -EINVAL;
1588                         goto out;
1589                 }
1590                 if (val < -32768 || val > 32767) {
1591                         size = -EINVAL;
1592                         goto out;
1593                 }
1594                 st_data->taps[i++] = val;
1595                 buf += tmp;
1596                 if (*buf != ',')
1597                         break;
1598                 buf++;
1599         } while (1);
1600
1601         st_data->nr_taps = i;
1602
1603 out:
1604         spin_unlock_irq(&mcbsp->lock);
1605
1606         return size;
1607 }
1608
1609 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1610
1611 static const struct attribute *additional_attrs[] = {
1612         &dev_attr_max_tx_thres.attr,
1613         &dev_attr_max_rx_thres.attr,
1614         &dev_attr_dma_op_mode.attr,
1615         NULL,
1616 };
1617
1618 static const struct attribute_group additional_attr_group = {
1619         .attrs = (struct attribute **)additional_attrs,
1620 };
1621
1622 static inline int __devinit omap_additional_add(struct device *dev)
1623 {
1624         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1625 }
1626
1627 static inline void __devexit omap_additional_remove(struct device *dev)
1628 {
1629         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1630 }
1631
1632 static const struct attribute *sidetone_attrs[] = {
1633         &dev_attr_st_taps.attr,
1634         NULL,
1635 };
1636
1637 static const struct attribute_group sidetone_attr_group = {
1638         .attrs = (struct attribute **)sidetone_attrs,
1639 };
1640
1641 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1642 {
1643         struct platform_device *pdev;
1644         struct resource *res;
1645         struct omap_mcbsp_st_data *st_data;
1646         int err;
1647
1648         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1649         if (!st_data) {
1650                 err = -ENOMEM;
1651                 goto err1;
1652         }
1653
1654         pdev = container_of(mcbsp->dev, struct platform_device, dev);
1655
1656         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1657         st_data->io_base_st = ioremap(res->start, resource_size(res));
1658         if (!st_data->io_base_st) {
1659                 err = -ENOMEM;
1660                 goto err2;
1661         }
1662
1663         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1664         if (err)
1665                 goto err3;
1666
1667         mcbsp->st_data = st_data;
1668         return 0;
1669
1670 err3:
1671         iounmap(st_data->io_base_st);
1672 err2:
1673         kfree(st_data);
1674 err1:
1675         return err;
1676
1677 }
1678
1679 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1680 {
1681         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1682
1683         if (st_data) {
1684                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1685                 iounmap(st_data->io_base_st);
1686                 kfree(st_data);
1687         }
1688 }
1689
1690 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1691 {
1692         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1693         if (cpu_is_omap34xx()) {
1694                 /*
1695                  * Initially configure the maximum thresholds to a safe value.
1696                  * The McBSP FIFO usage with these values should not go under
1697                  * 16 locations.
1698                  * If the whole FIFO without safety buffer is used, than there
1699                  * is a possibility that the DMA will be not able to push the
1700                  * new data on time, causing channel shifts in runtime.
1701                  */
1702                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1703                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1704                 /*
1705                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1706                  * for mcbsp2 instances.
1707                  */
1708                 if (omap_additional_add(mcbsp->dev))
1709                         dev_warn(mcbsp->dev,
1710                                 "Unable to create additional controls\n");
1711
1712                 if (mcbsp->id == 2 || mcbsp->id == 3)
1713                         if (omap_st_add(mcbsp))
1714                                 dev_warn(mcbsp->dev,
1715                                  "Unable to create sidetone controls\n");
1716
1717         } else {
1718                 mcbsp->max_tx_thres = -EINVAL;
1719                 mcbsp->max_rx_thres = -EINVAL;
1720         }
1721 }
1722
1723 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1724 {
1725         if (cpu_is_omap34xx()) {
1726                 omap_additional_remove(mcbsp->dev);
1727
1728                 if (mcbsp->id == 2 || mcbsp->id == 3)
1729                         omap_st_remove(mcbsp);
1730         }
1731 }
1732 #else
1733 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1734 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1735 #endif /* CONFIG_ARCH_OMAP3 */
1736
1737 /*
1738  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1739  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1740  */
1741 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1742 {
1743         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1744         struct omap_mcbsp *mcbsp;
1745         int id = pdev->id - 1;
1746         struct resource *res;
1747         int ret = 0;
1748
1749         if (!pdata) {
1750                 dev_err(&pdev->dev, "McBSP device initialized without"
1751                                 "platform data\n");
1752                 ret = -EINVAL;
1753                 goto exit;
1754         }
1755
1756         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1757
1758         if (id >= omap_mcbsp_count) {
1759                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1760                 ret = -EINVAL;
1761                 goto exit;
1762         }
1763
1764         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1765         if (!mcbsp) {
1766                 ret = -ENOMEM;
1767                 goto exit;
1768         }
1769
1770         spin_lock_init(&mcbsp->lock);
1771         mcbsp->id = id + 1;
1772         mcbsp->free = true;
1773         mcbsp->dma_tx_lch = -1;
1774         mcbsp->dma_rx_lch = -1;
1775
1776         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1777         if (!res) {
1778                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1779                 if (!res) {
1780                         dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1781                                         "resource\n", __func__, pdev->id);
1782                         ret = -ENOMEM;
1783                         goto exit;
1784                 }
1785         }
1786         mcbsp->phys_base = res->start;
1787         omap_mcbsp_cache_size = resource_size(res);
1788         mcbsp->io_base = ioremap(res->start, resource_size(res));
1789         if (!mcbsp->io_base) {
1790                 ret = -ENOMEM;
1791                 goto err_ioremap;
1792         }
1793
1794         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1795         if (!res)
1796                 mcbsp->phys_dma_base = mcbsp->phys_base;
1797         else
1798                 mcbsp->phys_dma_base = res->start;
1799
1800         /* Default I/O is IRQ based */
1801         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1802
1803         mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1804         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1805
1806         /* From OMAP4 there will be a single irq line */
1807         if (mcbsp->tx_irq == -ENXIO)
1808                 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1809
1810         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1811         if (!res) {
1812                 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1813                                         __func__, pdev->id);
1814                 ret = -ENODEV;
1815                 goto err_res;
1816         }
1817         mcbsp->dma_rx_sync = res->start;
1818
1819         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1820         if (!res) {
1821                 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1822                                         __func__, pdev->id);
1823                 ret = -ENODEV;
1824                 goto err_res;
1825         }
1826         mcbsp->dma_tx_sync = res->start;
1827
1828         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1829         if (IS_ERR(mcbsp->fclk)) {
1830                 ret = PTR_ERR(mcbsp->fclk);
1831                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1832                 goto err_res;
1833         }
1834
1835         mcbsp->pdata = pdata;
1836         mcbsp->dev = &pdev->dev;
1837         mcbsp_ptr[id] = mcbsp;
1838         platform_set_drvdata(pdev, mcbsp);
1839         pm_runtime_enable(mcbsp->dev);
1840
1841         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1842         omap34xx_device_init(mcbsp);
1843
1844         return 0;
1845
1846 err_res:
1847         iounmap(mcbsp->io_base);
1848 err_ioremap:
1849         kfree(mcbsp);
1850 exit:
1851         return ret;
1852 }
1853
1854 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1855 {
1856         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1857
1858         platform_set_drvdata(pdev, NULL);
1859         if (mcbsp) {
1860
1861                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1862                                 mcbsp->pdata->ops->free)
1863                         mcbsp->pdata->ops->free(mcbsp->id);
1864
1865                 omap34xx_device_exit(mcbsp);
1866
1867                 clk_put(mcbsp->fclk);
1868
1869                 iounmap(mcbsp->io_base);
1870                 kfree(mcbsp);
1871         }
1872
1873         return 0;
1874 }
1875
1876 static struct platform_driver omap_mcbsp_driver = {
1877         .probe          = omap_mcbsp_probe,
1878         .remove         = __devexit_p(omap_mcbsp_remove),
1879         .driver         = {
1880                 .name   = "omap-mcbsp",
1881         },
1882 };
1883
1884 int __init omap_mcbsp_init(void)
1885 {
1886         /* Register the McBSP driver */
1887         return platform_driver_register(&omap_mcbsp_driver);
1888 }