1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/sysdev.h>
20 #include <linux/serial_core.h>
21 #include <linux/platform_device.h>
22 #include <linux/dm9000.h>
23 #include <linux/ata_platform.h>
25 #include <net/ax88796.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
31 #include <asm/arch/bast-map.h>
32 #include <asm/arch/bast-irq.h>
33 #include <asm/arch/bast-cpld.h>
35 #include <asm/hardware.h>
38 #include <asm/mach-types.h>
40 //#include <asm/debug-ll.h>
41 #include <asm/plat-s3c/regs-serial.h>
42 #include <asm/arch/regs-gpio.h>
43 #include <asm/arch/regs-mem.h>
44 #include <asm/arch/regs-lcd.h>
46 #include <asm/plat-s3c/nand.h>
47 #include <asm/plat-s3c/iic.h>
48 #include <asm/arch/fb.h>
50 #include <linux/mtd/mtd.h>
51 #include <linux/mtd/nand.h>
52 #include <linux/mtd/nand_ecc.h>
53 #include <linux/mtd/partitions.h>
55 #include <linux/serial_8250.h>
57 #include <asm/plat-s3c24xx/clock.h>
58 #include <asm/plat-s3c24xx/devs.h>
59 #include <asm/plat-s3c24xx/cpu.h>
61 #include "usb-simtec.h"
62 #include "nor-simtec.h"
64 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
66 /* macros for virtual address mods for the io space entries */
67 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
68 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
69 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
70 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
72 /* macros to modify the physical addresses for io space */
74 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
75 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
76 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
77 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
79 static struct map_desc bast_iodesc[] __initdata = {
82 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
83 .pfn = PA_CS2(BAST_PA_ISAIO),
87 .virtual = (u32)S3C24XX_VA_ISA_WORD,
88 .pfn = PA_CS3(BAST_PA_ISAIO),
92 /* bast CPLD control registers, and external interrupt controls */
94 .virtual = (u32)BAST_VA_CTRL1,
95 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
99 .virtual = (u32)BAST_VA_CTRL2,
100 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
104 .virtual = (u32)BAST_VA_CTRL3,
105 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
109 .virtual = (u32)BAST_VA_CTRL4,
110 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
116 .virtual = (u32)BAST_VA_PC104_IRQREQ,
117 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
121 .virtual = (u32)BAST_VA_PC104_IRQRAW,
122 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
126 .virtual = (u32)BAST_VA_PC104_IRQMASK,
127 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
132 /* peripheral space... one for each of fast/slow/byte/16bit */
133 /* note, ide is only decoded in word space, even though some registers
137 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
138 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
139 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
142 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
143 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
144 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
147 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
148 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
149 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
152 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
153 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
154 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
157 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
158 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
159 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
161 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
177 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
184 .clocks = bast_serial_clocks,
185 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
193 .clocks = bast_serial_clocks,
194 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
196 /* port 2 is not actually used */
203 .clocks = bast_serial_clocks,
204 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
208 /* NAND Flash on BAST board */
211 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
213 /* ensure that an nRESET is not generated on resume. */
214 s3c2410_gpio_setpin(S3C2410_GPA21, 1);
215 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
220 static int bast_pm_resume(struct sys_device *sd)
222 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
227 #define bast_pm_suspend NULL
228 #define bast_pm_resume NULL
231 static struct sysdev_class bast_pm_sysclass = {
233 .suspend = bast_pm_suspend,
234 .resume = bast_pm_resume,
237 static struct sys_device bast_pm_sysdev = {
238 .cls = &bast_pm_sysclass,
241 static int smartmedia_map[] = { 0 };
242 static int chip0_map[] = { 1 };
243 static int chip1_map[] = { 2 };
244 static int chip2_map[] = { 3 };
246 static struct mtd_partition bast_default_nand_part[] = {
248 .name = "Boot Agent",
254 .size = SZ_4M - SZ_16K,
260 .size = MTDPART_SIZ_FULL,
264 /* the bast has 4 selectable slots for nand-flash, the three
265 * on-board chip areas, as well as the external SmartMedia
268 * Note, there is no current hot-plug support for the SmartMedia
272 static struct s3c2410_nand_set bast_nand_sets[] = {
274 .name = "SmartMedia",
276 .nr_map = smartmedia_map,
277 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
278 .partitions = bast_default_nand_part,
284 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
285 .partitions = bast_default_nand_part,
291 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
292 .partitions = bast_default_nand_part,
298 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
299 .partitions = bast_default_nand_part,
303 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
307 slot = set->nr_map[slot] & 3;
309 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
310 slot, set, set->nr_map);
312 tmp = __raw_readb(BAST_VA_CTRL2);
313 tmp &= BAST_CPLD_CTLR2_IDERST;
315 tmp |= BAST_CPLD_CTRL2_WNAND;
317 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
319 __raw_writeb(tmp, BAST_VA_CTRL2);
322 static struct s3c2410_platform_nand bast_nand_info = {
326 .nr_sets = ARRAY_SIZE(bast_nand_sets),
327 .sets = bast_nand_sets,
328 .select_chip = bast_nand_select,
333 static struct resource bast_dm9k_resource[] = {
335 .start = S3C2410_CS5 + BAST_PA_DM9000,
336 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
337 .flags = IORESOURCE_MEM,
340 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
341 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
342 .flags = IORESOURCE_MEM,
347 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
352 /* for the moment we limit ourselves to 16bit IO until some
353 * better IO routines can be written and tested
356 static struct dm9000_plat_data bast_dm9k_platdata = {
357 .flags = DM9000_PLATF_16BITONLY,
360 static struct platform_device bast_device_dm9k = {
363 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
364 .resource = bast_dm9k_resource,
366 .platform_data = &bast_dm9k_platdata,
372 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
373 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
374 #define SERIAL_CLK (1843200)
376 static struct plat_serial8250_port bast_sio_data[] = {
378 .mapbase = SERIAL_BASE + 0x2f8,
379 .irq = IRQ_PCSERIAL1,
380 .flags = SERIAL_FLAGS,
383 .uartclk = SERIAL_CLK,
386 .mapbase = SERIAL_BASE + 0x3f8,
387 .irq = IRQ_PCSERIAL2,
388 .flags = SERIAL_FLAGS,
391 .uartclk = SERIAL_CLK,
396 static struct platform_device bast_sio = {
397 .name = "serial8250",
398 .id = PLAT8250_DEV_PLATFORM,
400 .platform_data = &bast_sio_data,
404 /* we have devices on the bus which cannot work much over the
405 * standard 100KHz i2c bus frequency
408 static struct s3c2410_platform_i2c bast_i2c_info = {
411 .bus_freq = 100*1000,
412 .max_freq = 130*1000,
415 /* Asix AX88796 10/100 ethernet controller */
417 static struct ax_plat_data bast_asix_platdata = {
418 .flags = AXFLG_MAC_FROMDEV,
424 static struct resource bast_asix_resource[] = {
426 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
427 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
428 .flags = IORESOURCE_MEM,
431 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
432 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
433 .flags = IORESOURCE_MEM,
438 .flags = IORESOURCE_IRQ
442 static struct platform_device bast_device_asix = {
445 .num_resources = ARRAY_SIZE(bast_asix_resource),
446 .resource = bast_asix_resource,
448 .platform_data = &bast_asix_platdata
452 /* Asix AX88796 10/100 ethernet controller parallel port */
454 static struct resource bast_asixpp_resource[] = {
456 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
457 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
458 .flags = IORESOURCE_MEM,
462 static struct platform_device bast_device_axpp = {
463 .name = "ax88796-pp",
465 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
466 .resource = bast_asixpp_resource,
469 /* LCD/VGA controller */
471 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
473 .type = S3C2410_LCDCON1_TFT,
488 .lcdcon5 = 0x00014b02,
491 .type = S3C2410_LCDCON1_TFT,
506 .lcdcon5 = 0x00014b02,
509 .type = S3C2410_LCDCON1_TFT,
524 .lcdcon5 = 0x00014b02,
528 /* LCD/VGA controller */
530 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
532 .displays = bast_lcd_info,
533 .num_displays = ARRAY_SIZE(bast_lcd_info),
534 .default_display = 1,
538 /* Standard BAST devices */
540 static struct platform_device *bast_devices[] __initdata = {
553 static struct clk *bast_clocks[] = {
561 static void __init bast_map_io(void)
563 /* initialise the clocks */
565 s3c24xx_dclk0.parent = &clk_upll;
566 s3c24xx_dclk0.rate = 12*1000*1000;
568 s3c24xx_dclk1.parent = &clk_upll;
569 s3c24xx_dclk1.rate = 24*1000*1000;
571 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
572 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
574 s3c24xx_uclk.parent = &s3c24xx_clkout1;
576 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
578 s3c_device_nand.dev.platform_data = &bast_nand_info;
579 s3c_device_i2c.dev.platform_data = &bast_i2c_info;
581 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
582 s3c24xx_init_clocks(0);
583 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
588 static void __init bast_init(void)
590 sysdev_class_register(&bast_pm_sysclass);
591 sysdev_register(&bast_pm_sysdev);
593 s3c24xx_fb_set_platdata(&bast_fb_info);
594 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
599 MACHINE_START(BAST, "Simtec-BAST")
600 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
601 .phys_io = S3C2410_PA_UART,
602 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
603 .boot_params = S3C2410_SDRAM_PA + 0x100,
604 .map_io = bast_map_io,
605 .init_irq = s3c24xx_init_irq,
606 .init_machine = bast_init,
607 .timer = &s3c24xx_timer,