arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm1_44xx.h"
  31 #include "cm2_44xx.h"
  32 #include "prm44xx.h"
  33 #include "prm-regbits-44xx.h"
  34 #include "wd_timer.h"
  35
  36 /* Base offset for all OMAP4 interrupts external to MPUSS */
  37 #define OMAP44XX_IRQ_GIC_START  32
  38
  39 /* Base offset for all OMAP4 dma requests */
  40 #define OMAP44XX_DMA_REQ_START  1
  41
  42 /* Backward references (IPs with Bus Master capability) */
  43 static struct omap_hwmod omap44xx_aess_hwmod;
  44 static struct omap_hwmod omap44xx_dma_system_hwmod;
  45 static struct omap_hwmod omap44xx_dmm_hwmod;
  46 static struct omap_hwmod omap44xx_dsp_hwmod;
  47 static struct omap_hwmod omap44xx_dss_hwmod;
  48 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  49 static struct omap_hwmod omap44xx_hsi_hwmod;
  50 static struct omap_hwmod omap44xx_ipu_hwmod;
  51 static struct omap_hwmod omap44xx_iss_hwmod;
  52 static struct omap_hwmod omap44xx_iva_hwmod;
  53 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  54 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  55 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  56 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  57 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  58 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  59 static struct omap_hwmod omap44xx_l4_per_hwmod;
  60 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  61 static struct omap_hwmod omap44xx_mmc1_hwmod;
  62 static struct omap_hwmod omap44xx_mmc2_hwmod;
  63 static struct omap_hwmod omap44xx_mpu_hwmod;
  64 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  65 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  66
  67 /*
  68  * Interconnects omap_hwmod structures
  69  * hwmods that compose the global OMAP interconnect
  70  */
  71
  72 /*
  73  * 'dmm' class
  74  * instance(s): dmm
  75  */
  76 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  77         .name   = "dmm",
  78 };
  79
  80 /* dmm interface data */
  81 /* l3_main_1 -> dmm */
  82 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  83         .master         = &omap44xx_l3_main_1_hwmod,
  84         .slave          = &omap44xx_dmm_hwmod,
  85         .clk            = "l3_div_ck",
  86         .user           = OCP_USER_SDMA,
  87 };
  88
  89 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  90         {
  91                 .pa_start       = 0x4e000000,
  92                 .pa_end         = 0x4e0007ff,
  93                 .flags          = ADDR_TYPE_RT
  94         },
  95 };
  96
  97 /* mpu -> dmm */
  98 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  99         .master         = &omap44xx_mpu_hwmod,
 100         .slave          = &omap44xx_dmm_hwmod,
 101         .clk            = "l3_div_ck",
 102         .addr           = omap44xx_dmm_addrs,
 103         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
 104         .user           = OCP_USER_MPU,
 105 };
 106
 107 /* dmm slave ports */
 108 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 109         &omap44xx_l3_main_1__dmm,
 110         &omap44xx_mpu__dmm,
 111 };
 112
 113 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 114         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 115 };
 116
 117 static struct omap_hwmod omap44xx_dmm_hwmod = {
 118         .name           = "dmm",
 119         .class          = &omap44xx_dmm_hwmod_class,
 120         .slaves         = omap44xx_dmm_slaves,
 121         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 122         .mpu_irqs       = omap44xx_dmm_irqs,
 123         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 124         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 125 };
 126
 127 /*
 128  * 'emif_fw' class
 129  * instance(s): emif_fw
 130  */
 131 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 132         .name   = "emif_fw",
 133 };
 134
 135 /* emif_fw interface data */
 136 /* dmm -> emif_fw */
 137 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 138         .master         = &omap44xx_dmm_hwmod,
 139         .slave          = &omap44xx_emif_fw_hwmod,
 140         .clk            = "l3_div_ck",
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 145         {
 146                 .pa_start       = 0x4a20c000,
 147                 .pa_end         = 0x4a20c0ff,
 148                 .flags          = ADDR_TYPE_RT
 149         },
 150 };
 151
 152 /* l4_cfg -> emif_fw */
 153 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 154         .master         = &omap44xx_l4_cfg_hwmod,
 155         .slave          = &omap44xx_emif_fw_hwmod,
 156         .clk            = "l4_div_ck",
 157         .addr           = omap44xx_emif_fw_addrs,
 158         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 159         .user           = OCP_USER_MPU,
 160 };
 161
 162 /* emif_fw slave ports */
 163 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 164         &omap44xx_dmm__emif_fw,
 165         &omap44xx_l4_cfg__emif_fw,
 166 };
 167
 168 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 169         .name           = "emif_fw",
 170         .class          = &omap44xx_emif_fw_hwmod_class,
 171         .slaves         = omap44xx_emif_fw_slaves,
 172         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 173         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 174 };
 175
 176 /*
 177  * 'l3' class
 178  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 179  */
 180 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 181         .name   = "l3",
 182 };
 183
 184 /* l3_instr interface data */
 185 /* iva -> l3_instr */
 186 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 187         .master         = &omap44xx_iva_hwmod,
 188         .slave          = &omap44xx_l3_instr_hwmod,
 189         .clk            = "l3_div_ck",
 190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 191 };
 192
 193 /* l3_main_3 -> l3_instr */
 194 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 195         .master         = &omap44xx_l3_main_3_hwmod,
 196         .slave          = &omap44xx_l3_instr_hwmod,
 197         .clk            = "l3_div_ck",
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199 };
 200
 201 /* l3_instr slave ports */
 202 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 203         &omap44xx_iva__l3_instr,
 204         &omap44xx_l3_main_3__l3_instr,
 205 };
 206
 207 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 208         .name           = "l3_instr",
 209         .class          = &omap44xx_l3_hwmod_class,
 210         .slaves         = omap44xx_l3_instr_slaves,
 211         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 212         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 213 };
 214
 215 /* l3_main_1 interface data */
 216 /* dsp -> l3_main_1 */
 217 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 218         .master         = &omap44xx_dsp_hwmod,
 219         .slave          = &omap44xx_l3_main_1_hwmod,
 220         .clk            = "l3_div_ck",
 221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 222 };
 223
 224 /* dss -> l3_main_1 */
 225 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 226         .master         = &omap44xx_dss_hwmod,
 227         .slave          = &omap44xx_l3_main_1_hwmod,
 228         .clk            = "l3_div_ck",
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* l3_main_2 -> l3_main_1 */
 233 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 234         .master         = &omap44xx_l3_main_2_hwmod,
 235         .slave          = &omap44xx_l3_main_1_hwmod,
 236         .clk            = "l3_div_ck",
 237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 238 };
 239
 240 /* l4_cfg -> l3_main_1 */
 241 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 242         .master         = &omap44xx_l4_cfg_hwmod,
 243         .slave          = &omap44xx_l3_main_1_hwmod,
 244         .clk            = "l4_div_ck",
 245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 246 };
 247
 248 /* mmc1 -> l3_main_1 */
 249 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 250         .master         = &omap44xx_mmc1_hwmod,
 251         .slave          = &omap44xx_l3_main_1_hwmod,
 252         .clk            = "l3_div_ck",
 253         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 254 };
 255
 256 /* mmc2 -> l3_main_1 */
 257 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 258         .master         = &omap44xx_mmc2_hwmod,
 259         .slave          = &omap44xx_l3_main_1_hwmod,
 260         .clk            = "l3_div_ck",
 261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 262 };
 263
 264 /* mpu -> l3_main_1 */
 265 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 266         .master         = &omap44xx_mpu_hwmod,
 267         .slave          = &omap44xx_l3_main_1_hwmod,
 268         .clk            = "l3_div_ck",
 269         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 270 };
 271
 272 /* l3_main_1 slave ports */
 273 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 274         &omap44xx_dsp__l3_main_1,
 275         &omap44xx_dss__l3_main_1,
 276         &omap44xx_l3_main_2__l3_main_1,
 277         &omap44xx_l4_cfg__l3_main_1,
 278         &omap44xx_mmc1__l3_main_1,
 279         &omap44xx_mmc2__l3_main_1,
 280         &omap44xx_mpu__l3_main_1,
 281 };
 282
 283 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 284         .name           = "l3_main_1",
 285         .class          = &omap44xx_l3_hwmod_class,
 286         .slaves         = omap44xx_l3_main_1_slaves,
 287         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 288         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 289 };
 290
 291 /* l3_main_2 interface data */
 292 /* dma_system -> l3_main_2 */
 293 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 294         .master         = &omap44xx_dma_system_hwmod,
 295         .slave          = &omap44xx_l3_main_2_hwmod,
 296         .clk            = "l3_div_ck",
 297         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 298 };
 299
 300 /* hsi -> l3_main_2 */
 301 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 302         .master         = &omap44xx_hsi_hwmod,
 303         .slave          = &omap44xx_l3_main_2_hwmod,
 304         .clk            = "l3_div_ck",
 305         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 306 };
 307
 308 /* ipu -> l3_main_2 */
 309 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 310         .master         = &omap44xx_ipu_hwmod,
 311         .slave          = &omap44xx_l3_main_2_hwmod,
 312         .clk            = "l3_div_ck",
 313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 314 };
 315
 316 /* iss -> l3_main_2 */
 317 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 318         .master         = &omap44xx_iss_hwmod,
 319         .slave          = &omap44xx_l3_main_2_hwmod,
 320         .clk            = "l3_div_ck",
 321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 322 };
 323
 324 /* iva -> l3_main_2 */
 325 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 326         .master         = &omap44xx_iva_hwmod,
 327         .slave          = &omap44xx_l3_main_2_hwmod,
 328         .clk            = "l3_div_ck",
 329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 330 };
 331
 332 /* l3_main_1 -> l3_main_2 */
 333 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 334         .master         = &omap44xx_l3_main_1_hwmod,
 335         .slave          = &omap44xx_l3_main_2_hwmod,
 336         .clk            = "l3_div_ck",
 337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 338 };
 339
 340 /* l4_cfg -> l3_main_2 */
 341 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 342         .master         = &omap44xx_l4_cfg_hwmod,
 343         .slave          = &omap44xx_l3_main_2_hwmod,
 344         .clk            = "l4_div_ck",
 345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 346 };
 347
 348 /* usb_otg_hs -> l3_main_2 */
 349 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 350         .master         = &omap44xx_usb_otg_hs_hwmod,
 351         .slave          = &omap44xx_l3_main_2_hwmod,
 352         .clk            = "l3_div_ck",
 353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 354 };
 355
 356 /* l3_main_2 slave ports */
 357 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 358         &omap44xx_dma_system__l3_main_2,
 359         &omap44xx_hsi__l3_main_2,
 360         &omap44xx_ipu__l3_main_2,
 361         &omap44xx_iss__l3_main_2,
 362         &omap44xx_iva__l3_main_2,
 363         &omap44xx_l3_main_1__l3_main_2,
 364         &omap44xx_l4_cfg__l3_main_2,
 365         &omap44xx_usb_otg_hs__l3_main_2,
 366 };
 367
 368 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 369         .name           = "l3_main_2",
 370         .class          = &omap44xx_l3_hwmod_class,
 371         .slaves         = omap44xx_l3_main_2_slaves,
 372         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 373         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 374 };
 375
 376 /* l3_main_3 interface data */
 377 /* l3_main_1 -> l3_main_3 */
 378 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 379         .master         = &omap44xx_l3_main_1_hwmod,
 380         .slave          = &omap44xx_l3_main_3_hwmod,
 381         .clk            = "l3_div_ck",
 382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 383 };
 384
 385 /* l3_main_2 -> l3_main_3 */
 386 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 387         .master         = &omap44xx_l3_main_2_hwmod,
 388         .slave          = &omap44xx_l3_main_3_hwmod,
 389         .clk            = "l3_div_ck",
 390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 391 };
 392
 393 /* l4_cfg -> l3_main_3 */
 394 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 395         .master         = &omap44xx_l4_cfg_hwmod,
 396         .slave          = &omap44xx_l3_main_3_hwmod,
 397         .clk            = "l4_div_ck",
 398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 399 };
 400
 401 /* l3_main_3 slave ports */
 402 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 403         &omap44xx_l3_main_1__l3_main_3,
 404         &omap44xx_l3_main_2__l3_main_3,
 405         &omap44xx_l4_cfg__l3_main_3,
 406 };
 407
 408 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 409         .name           = "l3_main_3",
 410         .class          = &omap44xx_l3_hwmod_class,
 411         .slaves         = omap44xx_l3_main_3_slaves,
 412         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 413         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 414 };
 415
 416 /*
 417  * 'l4' class
 418  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 419  */
 420 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 421         .name   = "l4",
 422 };
 423
 424 /* l4_abe interface data */
 425 /* aess -> l4_abe */
 426 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 427         .master         = &omap44xx_aess_hwmod,
 428         .slave          = &omap44xx_l4_abe_hwmod,
 429         .clk            = "ocp_abe_iclk",
 430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 431 };
 432
 433 /* dsp -> l4_abe */
 434 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 435         .master         = &omap44xx_dsp_hwmod,
 436         .slave          = &omap44xx_l4_abe_hwmod,
 437         .clk            = "ocp_abe_iclk",
 438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 439 };
 440
 441 /* l3_main_1 -> l4_abe */
 442 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 443         .master         = &omap44xx_l3_main_1_hwmod,
 444         .slave          = &omap44xx_l4_abe_hwmod,
 445         .clk            = "l3_div_ck",
 446         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 447 };
 448
 449 /* mpu -> l4_abe */
 450 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 451         .master         = &omap44xx_mpu_hwmod,
 452         .slave          = &omap44xx_l4_abe_hwmod,
 453         .clk            = "ocp_abe_iclk",
 454         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 455 };
 456
 457 /* l4_abe slave ports */
 458 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 459         &omap44xx_aess__l4_abe,
 460         &omap44xx_dsp__l4_abe,
 461         &omap44xx_l3_main_1__l4_abe,
 462         &omap44xx_mpu__l4_abe,
 463 };
 464
 465 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 466         .name           = "l4_abe",
 467         .class          = &omap44xx_l4_hwmod_class,
 468         .slaves         = omap44xx_l4_abe_slaves,
 469         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 470         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 471 };
 472
 473 /* l4_cfg interface data */
 474 /* l3_main_1 -> l4_cfg */
 475 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 476         .master         = &omap44xx_l3_main_1_hwmod,
 477         .slave          = &omap44xx_l4_cfg_hwmod,
 478         .clk            = "l3_div_ck",
 479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 480 };
 481
 482 /* l4_cfg slave ports */
 483 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 484         &omap44xx_l3_main_1__l4_cfg,
 485 };
 486
 487 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 488         .name           = "l4_cfg",
 489         .class          = &omap44xx_l4_hwmod_class,
 490         .slaves         = omap44xx_l4_cfg_slaves,
 491         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 493 };
 494
 495 /* l4_per interface data */
 496 /* l3_main_2 -> l4_per */
 497 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 498         .master         = &omap44xx_l3_main_2_hwmod,
 499         .slave          = &omap44xx_l4_per_hwmod,
 500         .clk            = "l3_div_ck",
 501         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 502 };
 503
 504 /* l4_per slave ports */
 505 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 506         &omap44xx_l3_main_2__l4_per,
 507 };
 508
 509 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 510         .name           = "l4_per",
 511         .class          = &omap44xx_l4_hwmod_class,
 512         .slaves         = omap44xx_l4_per_slaves,
 513         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 514         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 515 };
 516
 517 /* l4_wkup interface data */
 518 /* l4_cfg -> l4_wkup */
 519 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 520         .master         = &omap44xx_l4_cfg_hwmod,
 521         .slave          = &omap44xx_l4_wkup_hwmod,
 522         .clk            = "l4_div_ck",
 523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 524 };
 525
 526 /* l4_wkup slave ports */
 527 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 528         &omap44xx_l4_cfg__l4_wkup,
 529 };
 530
 531 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 532         .name           = "l4_wkup",
 533         .class          = &omap44xx_l4_hwmod_class,
 534         .slaves         = omap44xx_l4_wkup_slaves,
 535         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 536         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 537 };
 538
 539 /*
 540  * 'mpu_bus' class
 541  * instance(s): mpu_private
 542  */
 543 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 544         .name   = "mpu_bus",
 545 };
 546
 547 /* mpu_private interface data */
 548 /* mpu -> mpu_private */
 549 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 550         .master         = &omap44xx_mpu_hwmod,
 551         .slave          = &omap44xx_mpu_private_hwmod,
 552         .clk            = "l3_div_ck",
 553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 554 };
 555
 556 /* mpu_private slave ports */
 557 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 558         &omap44xx_mpu__mpu_private,
 559 };
 560
 561 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 562         .name           = "mpu_private",
 563         .class          = &omap44xx_mpu_bus_hwmod_class,
 564         .slaves         = omap44xx_mpu_private_slaves,
 565         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 566         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 567 };
 568
 569 /*
 570  * Modules omap_hwmod structures
 571  *
 572  * The following IPs are excluded for the moment because:
 573  * - They do not need an explicit SW control using omap_hwmod API.
 574  * - They still need to be validated with the driver
 575  *   properly adapted to omap_hwmod / omap_device
 576  *
 577  *  c2c
 578  *  c2c_target_fw
 579  *  cm_core
 580  *  cm_core_aon
 581  *  ctrl_module_core
 582  *  ctrl_module_pad_core
 583  *  ctrl_module_pad_wkup
 584  *  ctrl_module_wkup
 585  *  debugss
 586  *  efuse_ctrl_cust
 587  *  efuse_ctrl_std
 588  *  elm
 589  *  emif1
 590  *  emif2
 591  *  fdif
 592  *  gpmc
 593  *  gpu
 594  *  hdq1w
 595  *  hsi
 596  *  ocmc_ram
 597  *  ocp2scp_usb_phy
 598  *  ocp_wp_noc
 599  *  prcm_mpu
 600  *  prm
 601  *  scrm
 602  *  sl2if
 603  *  slimbus1
 604  *  slimbus2
 605  *  usb_host_fs
 606  *  usb_host_hs
 607  *  usb_phy_cm
 608  *  usb_tll_hs
 609  *  usim
 610  */
 611
 612 /*
 613  * 'aess' class
 614  * audio engine sub system
 615  */
 616
 617 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 618         .rev_offs       = 0x0000,
 619         .sysc_offs      = 0x0010,
 620         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 621         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 622                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 623         .sysc_fields    = &omap_hwmod_sysc_type2,
 624 };
 625
 626 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 627         .name   = "aess",
 628         .sysc   = &omap44xx_aess_sysc,
 629 };
 630
 631 /* aess */
 632 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 633         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 634 };
 635
 636 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 637         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 638         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 639         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 640         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 641         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 642         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 643         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 644         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 645 };
 646
 647 /* aess master ports */
 648 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 649         &omap44xx_aess__l4_abe,
 650 };
 651
 652 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 653         {
 654                 .pa_start       = 0x401f1000,
 655                 .pa_end         = 0x401f13ff,
 656                 .flags          = ADDR_TYPE_RT
 657         },
 658 };
 659
 660 /* l4_abe -> aess */
 661 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 662         .master         = &omap44xx_l4_abe_hwmod,
 663         .slave          = &omap44xx_aess_hwmod,
 664         .clk            = "ocp_abe_iclk",
 665         .addr           = omap44xx_aess_addrs,
 666         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
 667         .user           = OCP_USER_MPU,
 668 };
 669
 670 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 671         {
 672                 .pa_start       = 0x490f1000,
 673                 .pa_end         = 0x490f13ff,
 674                 .flags          = ADDR_TYPE_RT
 675         },
 676 };
 677
 678 /* l4_abe -> aess (dma) */
 679 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 680         .master         = &omap44xx_l4_abe_hwmod,
 681         .slave          = &omap44xx_aess_hwmod,
 682         .clk            = "ocp_abe_iclk",
 683         .addr           = omap44xx_aess_dma_addrs,
 684         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
 685         .user           = OCP_USER_SDMA,
 686 };
 687
 688 /* aess slave ports */
 689 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 690         &omap44xx_l4_abe__aess,
 691         &omap44xx_l4_abe__aess_dma,
 692 };
 693
 694 static struct omap_hwmod omap44xx_aess_hwmod = {
 695         .name           = "aess",
 696         .class          = &omap44xx_aess_hwmod_class,
 697         .mpu_irqs       = omap44xx_aess_irqs,
 698         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
 699         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 700         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
 701         .main_clk       = "aess_fck",
 702         .prcm           = {
 703                 .omap4 = {
 704                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 705                 },
 706         },
 707         .slaves         = omap44xx_aess_slaves,
 708         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 709         .masters        = omap44xx_aess_masters,
 710         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 711         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 712 };
 713
 714 /*
 715  * 'bandgap' class
 716  * bangap reference for ldo regulators
 717  */
 718
 719 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 720         .name   = "bandgap",
 721 };
 722
 723 /* bandgap */
 724 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 725         { .role = "fclk", .clk = "bandgap_fclk" },
 726 };
 727
 728 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 729         .name           = "bandgap",
 730         .class          = &omap44xx_bandgap_hwmod_class,
 731         .prcm           = {
 732                 .omap4 = {
 733                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 734                 },
 735         },
 736         .opt_clks       = bandgap_opt_clks,
 737         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 738         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 739 };
 740
 741 /*
 742  * 'counter' class
 743  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 744  */
 745
 746 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 747         .rev_offs       = 0x0000,
 748         .sysc_offs      = 0x0004,
 749         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 750         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 751                            SIDLE_SMART_WKUP),
 752         .sysc_fields    = &omap_hwmod_sysc_type1,
 753 };
 754
 755 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 756         .name   = "counter",
 757         .sysc   = &omap44xx_counter_sysc,
 758 };
 759
 760 /* counter_32k */
 761 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 762 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 763         {
 764                 .pa_start       = 0x4a304000,
 765                 .pa_end         = 0x4a30401f,
 766                 .flags          = ADDR_TYPE_RT
 767         },
 768 };
 769
 770 /* l4_wkup -> counter_32k */
 771 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 772         .master         = &omap44xx_l4_wkup_hwmod,
 773         .slave          = &omap44xx_counter_32k_hwmod,
 774         .clk            = "l4_wkup_clk_mux_ck",
 775         .addr           = omap44xx_counter_32k_addrs,
 776         .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
 777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 778 };
 779
 780 /* counter_32k slave ports */
 781 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 782         &omap44xx_l4_wkup__counter_32k,
 783 };
 784
 785 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 786         .name           = "counter_32k",
 787         .class          = &omap44xx_counter_hwmod_class,
 788         .flags          = HWMOD_SWSUP_SIDLE,
 789         .main_clk       = "sys_32k_ck",
 790         .prcm           = {
 791                 .omap4 = {
 792                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 793                 },
 794         },
 795         .slaves         = omap44xx_counter_32k_slaves,
 796         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 797         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 798 };
 799
 800 /*
 801  * 'dma' class
 802  * dma controller for data exchange between memory to memory (i.e. internal or
 803  * external memory) and gp peripherals to memory or memory to gp peripherals
 804  */
 805
 806 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 807         .rev_offs       = 0x0000,
 808         .sysc_offs      = 0x002c,
 809         .syss_offs      = 0x0028,
 810         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 811                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 812                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 813                            SYSS_HAS_RESET_STATUS),
 814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 815                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 816         .sysc_fields    = &omap_hwmod_sysc_type1,
 817 };
 818
 819 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 820         .name   = "dma",
 821         .sysc   = &omap44xx_dma_sysc,
 822 };
 823
 824 /* dma dev_attr */
 825 static struct omap_dma_dev_attr dma_dev_attr = {
 826         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 827                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 828         .lch_count      = 32,
 829 };
 830
 831 /* dma_system */
 832 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 833         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 834         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 835         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 836         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 837 };
 838
 839 /* dma_system master ports */
 840 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 841         &omap44xx_dma_system__l3_main_2,
 842 };
 843
 844 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 845         {
 846                 .pa_start       = 0x4a056000,
 847                 .pa_end         = 0x4a0560ff,
 848                 .flags          = ADDR_TYPE_RT
 849         },
 850 };
 851
 852 /* l4_cfg -> dma_system */
 853 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 854         .master         = &omap44xx_l4_cfg_hwmod,
 855         .slave          = &omap44xx_dma_system_hwmod,
 856         .clk            = "l4_div_ck",
 857         .addr           = omap44xx_dma_system_addrs,
 858         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
 859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 860 };
 861
 862 /* dma_system slave ports */
 863 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 864         &omap44xx_l4_cfg__dma_system,
 865 };
 866
 867 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 868         .name           = "dma_system",
 869         .class          = &omap44xx_dma_hwmod_class,
 870         .mpu_irqs       = omap44xx_dma_system_irqs,
 871         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
 872         .main_clk       = "l3_div_ck",
 873         .prcm = {
 874                 .omap4 = {
 875                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 876                 },
 877         },
 878         .dev_attr       = &dma_dev_attr,
 879         .slaves         = omap44xx_dma_system_slaves,
 880         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 881         .masters        = omap44xx_dma_system_masters,
 882         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 883         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 884 };
 885
 886 /*
 887  * 'dmic' class
 888  * digital microphone controller
 889  */
 890
 891 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 892         .rev_offs       = 0x0000,
 893         .sysc_offs      = 0x0010,
 894         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 895                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 896         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 897                            SIDLE_SMART_WKUP),
 898         .sysc_fields    = &omap_hwmod_sysc_type2,
 899 };
 900
 901 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 902         .name   = "dmic",
 903         .sysc   = &omap44xx_dmic_sysc,
 904 };
 905
 906 /* dmic */
 907 static struct omap_hwmod omap44xx_dmic_hwmod;
 908 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 909         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 910 };
 911
 912 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 913         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 914 };
 915
 916 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 917         {
 918                 .pa_start       = 0x4012e000,
 919                 .pa_end         = 0x4012e07f,
 920                 .flags          = ADDR_TYPE_RT
 921         },
 922 };
 923
 924 /* l4_abe -> dmic */
 925 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 926         .master         = &omap44xx_l4_abe_hwmod,
 927         .slave          = &omap44xx_dmic_hwmod,
 928         .clk            = "ocp_abe_iclk",
 929         .addr           = omap44xx_dmic_addrs,
 930         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
 931         .user           = OCP_USER_MPU,
 932 };
 933
 934 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 935         {
 936                 .pa_start       = 0x4902e000,
 937                 .pa_end         = 0x4902e07f,
 938                 .flags          = ADDR_TYPE_RT
 939         },
 940 };
 941
 942 /* l4_abe -> dmic (dma) */
 943 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 944         .master         = &omap44xx_l4_abe_hwmod,
 945         .slave          = &omap44xx_dmic_hwmod,
 946         .clk            = "ocp_abe_iclk",
 947         .addr           = omap44xx_dmic_dma_addrs,
 948         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
 949         .user           = OCP_USER_SDMA,
 950 };
 951
 952 /* dmic slave ports */
 953 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 954         &omap44xx_l4_abe__dmic,
 955         &omap44xx_l4_abe__dmic_dma,
 956 };
 957
 958 static struct omap_hwmod omap44xx_dmic_hwmod = {
 959         .name           = "dmic",
 960         .class          = &omap44xx_dmic_hwmod_class,
 961         .mpu_irqs       = omap44xx_dmic_irqs,
 962         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
 963         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 964         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
 965         .main_clk       = "dmic_fck",
 966         .prcm           = {
 967                 .omap4 = {
 968                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 969                 },
 970         },
 971         .slaves         = omap44xx_dmic_slaves,
 972         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
 973         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 974 };
 975
 976 /*
 977  * 'dsp' class
 978  * dsp sub-system
 979  */
 980
 981 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 982         .name   = "dsp",
 983 };
 984
 985 /* dsp */
 986 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 987         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 988 };
 989
 990 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 991         { .name = "mmu_cache", .rst_shift = 1 },
 992 };
 993
 994 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 995         { .name = "dsp", .rst_shift = 0 },
 996 };
 997
 998 /* dsp -> iva */
 999 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1000         .master         = &omap44xx_dsp_hwmod,
1001         .slave          = &omap44xx_iva_hwmod,
1002         .clk            = "dpll_iva_m5x2_ck",
1003 };
1004
1005 /* dsp master ports */
1006 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1007         &omap44xx_dsp__l3_main_1,
1008         &omap44xx_dsp__l4_abe,
1009         &omap44xx_dsp__iva,
1010 };
1011
1012 /* l4_cfg -> dsp */
1013 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1014         .master         = &omap44xx_l4_cfg_hwmod,
1015         .slave          = &omap44xx_dsp_hwmod,
1016         .clk            = "l4_div_ck",
1017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1018 };
1019
1020 /* dsp slave ports */
1021 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1022         &omap44xx_l4_cfg__dsp,
1023 };
1024
1025 /* Pseudo hwmod for reset control purpose only */
1026 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1027         .name           = "dsp_c0",
1028         .class          = &omap44xx_dsp_hwmod_class,
1029         .flags          = HWMOD_INIT_NO_RESET,
1030         .rst_lines      = omap44xx_dsp_c0_resets,
1031         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1032         .prcm = {
1033                 .omap4 = {
1034                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1035                 },
1036         },
1037         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1038 };
1039
1040 static struct omap_hwmod omap44xx_dsp_hwmod = {
1041         .name           = "dsp",
1042         .class          = &omap44xx_dsp_hwmod_class,
1043         .mpu_irqs       = omap44xx_dsp_irqs,
1044         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
1045         .rst_lines      = omap44xx_dsp_resets,
1046         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1047         .main_clk       = "dsp_fck",
1048         .prcm = {
1049                 .omap4 = {
1050                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1051                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1052                 },
1053         },
1054         .slaves         = omap44xx_dsp_slaves,
1055         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1056         .masters        = omap44xx_dsp_masters,
1057         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1059 };
1060
1061 /*
1062  * 'dss' class
1063  * display sub-system
1064  */
1065
1066 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1067         .rev_offs       = 0x0000,
1068         .syss_offs      = 0x0014,
1069         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1070 };
1071
1072 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1073         .name   = "dss",
1074         .sysc   = &omap44xx_dss_sysc,
1075 };
1076
1077 /* dss */
1078 /* dss master ports */
1079 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1080         &omap44xx_dss__l3_main_1,
1081 };
1082
1083 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1084         {
1085                 .pa_start       = 0x58000000,
1086                 .pa_end         = 0x5800007f,
1087                 .flags          = ADDR_TYPE_RT
1088         },
1089 };
1090
1091 /* l3_main_2 -> dss */
1092 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1093         .master         = &omap44xx_l3_main_2_hwmod,
1094         .slave          = &omap44xx_dss_hwmod,
1095         .clk            = "l3_div_ck",
1096         .addr           = omap44xx_dss_dma_addrs,
1097         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1098         .user           = OCP_USER_SDMA,
1099 };
1100
1101 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1102         {
1103                 .pa_start       = 0x48040000,
1104                 .pa_end         = 0x4804007f,
1105                 .flags          = ADDR_TYPE_RT
1106         },
1107 };
1108
1109 /* l4_per -> dss */
1110 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1111         .master         = &omap44xx_l4_per_hwmod,
1112         .slave          = &omap44xx_dss_hwmod,
1113         .clk            = "l4_div_ck",
1114         .addr           = omap44xx_dss_addrs,
1115         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
1116         .user           = OCP_USER_MPU,
1117 };
1118
1119 /* dss slave ports */
1120 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1121         &omap44xx_l3_main_2__dss,
1122         &omap44xx_l4_per__dss,
1123 };
1124
1125 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1126         { .role = "sys_clk", .clk = "dss_sys_clk" },
1127         { .role = "tv_clk", .clk = "dss_tv_clk" },
1128         { .role = "dss_clk", .clk = "dss_dss_clk" },
1129         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1130 };
1131
1132 static struct omap_hwmod omap44xx_dss_hwmod = {
1133         .name           = "dss_core",
1134         .class          = &omap44xx_dss_hwmod_class,
1135         .main_clk       = "dss_fck",
1136         .prcm = {
1137                 .omap4 = {
1138                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1139                 },
1140         },
1141         .opt_clks       = dss_opt_clks,
1142         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1143         .slaves         = omap44xx_dss_slaves,
1144         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1145         .masters        = omap44xx_dss_masters,
1146         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1147         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1148 };
1149
1150 /*
1151  * 'dispc' class
1152  * display controller
1153  */
1154
1155 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1156         .rev_offs       = 0x0000,
1157         .sysc_offs      = 0x0010,
1158         .syss_offs      = 0x0014,
1159         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1160                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1161                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1162                            SYSS_HAS_RESET_STATUS),
1163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1164                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1165         .sysc_fields    = &omap_hwmod_sysc_type1,
1166 };
1167
1168 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1169         .name   = "dispc",
1170         .sysc   = &omap44xx_dispc_sysc,
1171 };
1172
1173 /* dss_dispc */
1174 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1175 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1176         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1177 };
1178
1179 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1180         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1181 };
1182
1183 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1184         {
1185                 .pa_start       = 0x58001000,
1186                 .pa_end         = 0x58001fff,
1187                 .flags          = ADDR_TYPE_RT
1188         },
1189 };
1190
1191 /* l3_main_2 -> dss_dispc */
1192 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1193         .master         = &omap44xx_l3_main_2_hwmod,
1194         .slave          = &omap44xx_dss_dispc_hwmod,
1195         .clk            = "l3_div_ck",
1196         .addr           = omap44xx_dss_dispc_dma_addrs,
1197         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1198         .user           = OCP_USER_SDMA,
1199 };
1200
1201 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1202         {
1203                 .pa_start       = 0x48041000,
1204                 .pa_end         = 0x48041fff,
1205                 .flags          = ADDR_TYPE_RT
1206         },
1207 };
1208
1209 /* l4_per -> dss_dispc */
1210 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1211         .master         = &omap44xx_l4_per_hwmod,
1212         .slave          = &omap44xx_dss_dispc_hwmod,
1213         .clk            = "l4_div_ck",
1214         .addr           = omap44xx_dss_dispc_addrs,
1215         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1216         .user           = OCP_USER_MPU,
1217 };
1218
1219 /* dss_dispc slave ports */
1220 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1221         &omap44xx_l3_main_2__dss_dispc,
1222         &omap44xx_l4_per__dss_dispc,
1223 };
1224
1225 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1226         .name           = "dss_dispc",
1227         .class          = &omap44xx_dispc_hwmod_class,
1228         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1229         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1230         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1231         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1232         .main_clk       = "dss_fck",
1233         .prcm = {
1234                 .omap4 = {
1235                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1236                 },
1237         },
1238         .slaves         = omap44xx_dss_dispc_slaves,
1239         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1240         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1241 };
1242
1243 /*
1244  * 'dsi' class
1245  * display serial interface controller
1246  */
1247
1248 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1249         .rev_offs       = 0x0000,
1250         .sysc_offs      = 0x0010,
1251         .syss_offs      = 0x0014,
1252         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1253                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1254                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1255         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1256         .sysc_fields    = &omap_hwmod_sysc_type1,
1257 };
1258
1259 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1260         .name   = "dsi",
1261         .sysc   = &omap44xx_dsi_sysc,
1262 };
1263
1264 /* dss_dsi1 */
1265 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1266 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1267         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1268 };
1269
1270 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1271         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1272 };
1273
1274 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1275         {
1276                 .pa_start       = 0x58004000,
1277                 .pa_end         = 0x580041ff,
1278                 .flags          = ADDR_TYPE_RT
1279         },
1280 };
1281
1282 /* l3_main_2 -> dss_dsi1 */
1283 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1284         .master         = &omap44xx_l3_main_2_hwmod,
1285         .slave          = &omap44xx_dss_dsi1_hwmod,
1286         .clk            = "l3_div_ck",
1287         .addr           = omap44xx_dss_dsi1_dma_addrs,
1288         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1289         .user           = OCP_USER_SDMA,
1290 };
1291
1292 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1293         {
1294                 .pa_start       = 0x48044000,
1295                 .pa_end         = 0x480441ff,
1296                 .flags          = ADDR_TYPE_RT
1297         },
1298 };
1299
1300 /* l4_per -> dss_dsi1 */
1301 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1302         .master         = &omap44xx_l4_per_hwmod,
1303         .slave          = &omap44xx_dss_dsi1_hwmod,
1304         .clk            = "l4_div_ck",
1305         .addr           = omap44xx_dss_dsi1_addrs,
1306         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1307         .user           = OCP_USER_MPU,
1308 };
1309
1310 /* dss_dsi1 slave ports */
1311 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1312         &omap44xx_l3_main_2__dss_dsi1,
1313         &omap44xx_l4_per__dss_dsi1,
1314 };
1315
1316 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1317         .name           = "dss_dsi1",
1318         .class          = &omap44xx_dsi_hwmod_class,
1319         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1320         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1321         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1322         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1323         .main_clk       = "dss_fck",
1324         .prcm = {
1325                 .omap4 = {
1326                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1327                 },
1328         },
1329         .slaves         = omap44xx_dss_dsi1_slaves,
1330         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1331         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1332 };
1333
1334 /* dss_dsi2 */
1335 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1336 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1337         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1338 };
1339
1340 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1341         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1342 };
1343
1344 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1345         {
1346                 .pa_start       = 0x58005000,
1347                 .pa_end         = 0x580051ff,
1348                 .flags          = ADDR_TYPE_RT
1349         },
1350 };
1351
1352 /* l3_main_2 -> dss_dsi2 */
1353 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1354         .master         = &omap44xx_l3_main_2_hwmod,
1355         .slave          = &omap44xx_dss_dsi2_hwmod,
1356         .clk            = "l3_div_ck",
1357         .addr           = omap44xx_dss_dsi2_dma_addrs,
1358         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1359         .user           = OCP_USER_SDMA,
1360 };
1361
1362 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1363         {
1364                 .pa_start       = 0x48045000,
1365                 .pa_end         = 0x480451ff,
1366                 .flags          = ADDR_TYPE_RT
1367         },
1368 };
1369
1370 /* l4_per -> dss_dsi2 */
1371 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1372         .master         = &omap44xx_l4_per_hwmod,
1373         .slave          = &omap44xx_dss_dsi2_hwmod,
1374         .clk            = "l4_div_ck",
1375         .addr           = omap44xx_dss_dsi2_addrs,
1376         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1377         .user           = OCP_USER_MPU,
1378 };
1379
1380 /* dss_dsi2 slave ports */
1381 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1382         &omap44xx_l3_main_2__dss_dsi2,
1383         &omap44xx_l4_per__dss_dsi2,
1384 };
1385
1386 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1387         .name           = "dss_dsi2",
1388         .class          = &omap44xx_dsi_hwmod_class,
1389         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1390         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1391         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1392         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1393         .main_clk       = "dss_fck",
1394         .prcm = {
1395                 .omap4 = {
1396                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1397                 },
1398         },
1399         .slaves         = omap44xx_dss_dsi2_slaves,
1400         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1401         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1402 };
1403
1404 /*
1405  * 'hdmi' class
1406  * hdmi controller
1407  */
1408
1409 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1410         .rev_offs       = 0x0000,
1411         .sysc_offs      = 0x0010,
1412         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1413                            SYSC_HAS_SOFTRESET),
1414         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1415                            SIDLE_SMART_WKUP),
1416         .sysc_fields    = &omap_hwmod_sysc_type2,
1417 };
1418
1419 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1420         .name   = "hdmi",
1421         .sysc   = &omap44xx_hdmi_sysc,
1422 };
1423
1424 /* dss_hdmi */
1425 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1426 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1427         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1428 };
1429
1430 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1431         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1432 };
1433
1434 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1435         {
1436                 .pa_start       = 0x58006000,
1437                 .pa_end         = 0x58006fff,
1438                 .flags          = ADDR_TYPE_RT
1439         },
1440 };
1441
1442 /* l3_main_2 -> dss_hdmi */
1443 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1444         .master         = &omap44xx_l3_main_2_hwmod,
1445         .slave          = &omap44xx_dss_hdmi_hwmod,
1446         .clk            = "l3_div_ck",
1447         .addr           = omap44xx_dss_hdmi_dma_addrs,
1448         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1449         .user           = OCP_USER_SDMA,
1450 };
1451
1452 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1453         {
1454                 .pa_start       = 0x48046000,
1455                 .pa_end         = 0x48046fff,
1456                 .flags          = ADDR_TYPE_RT
1457         },
1458 };
1459
1460 /* l4_per -> dss_hdmi */
1461 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1462         .master         = &omap44xx_l4_per_hwmod,
1463         .slave          = &omap44xx_dss_hdmi_hwmod,
1464         .clk            = "l4_div_ck",
1465         .addr           = omap44xx_dss_hdmi_addrs,
1466         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1467         .user           = OCP_USER_MPU,
1468 };
1469
1470 /* dss_hdmi slave ports */
1471 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1472         &omap44xx_l3_main_2__dss_hdmi,
1473         &omap44xx_l4_per__dss_hdmi,
1474 };
1475
1476 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1477         .name           = "dss_hdmi",
1478         .class          = &omap44xx_hdmi_hwmod_class,
1479         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1480         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1481         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1482         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1483         .main_clk       = "dss_fck",
1484         .prcm = {
1485                 .omap4 = {
1486                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1487                 },
1488         },
1489         .slaves         = omap44xx_dss_hdmi_slaves,
1490         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1491         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1492 };
1493
1494 /*
1495  * 'rfbi' class
1496  * remote frame buffer interface
1497  */
1498
1499 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1500         .rev_offs       = 0x0000,
1501         .sysc_offs      = 0x0010,
1502         .syss_offs      = 0x0014,
1503         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1504                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1505         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1506         .sysc_fields    = &omap_hwmod_sysc_type1,
1507 };
1508
1509 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1510         .name   = "rfbi",
1511         .sysc   = &omap44xx_rfbi_sysc,
1512 };
1513
1514 /* dss_rfbi */
1515 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1516 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1517         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1518 };
1519
1520 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1521         {
1522                 .pa_start       = 0x58002000,
1523                 .pa_end         = 0x580020ff,
1524                 .flags          = ADDR_TYPE_RT
1525         },
1526 };
1527
1528 /* l3_main_2 -> dss_rfbi */
1529 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1530         .master         = &omap44xx_l3_main_2_hwmod,
1531         .slave          = &omap44xx_dss_rfbi_hwmod,
1532         .clk            = "l3_div_ck",
1533         .addr           = omap44xx_dss_rfbi_dma_addrs,
1534         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1535         .user           = OCP_USER_SDMA,
1536 };
1537
1538 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1539         {
1540                 .pa_start       = 0x48042000,
1541                 .pa_end         = 0x480420ff,
1542                 .flags          = ADDR_TYPE_RT
1543         },
1544 };
1545
1546 /* l4_per -> dss_rfbi */
1547 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1548         .master         = &omap44xx_l4_per_hwmod,
1549         .slave          = &omap44xx_dss_rfbi_hwmod,
1550         .clk            = "l4_div_ck",
1551         .addr           = omap44xx_dss_rfbi_addrs,
1552         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1553         .user           = OCP_USER_MPU,
1554 };
1555
1556 /* dss_rfbi slave ports */
1557 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1558         &omap44xx_l3_main_2__dss_rfbi,
1559         &omap44xx_l4_per__dss_rfbi,
1560 };
1561
1562 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1563         .name           = "dss_rfbi",
1564         .class          = &omap44xx_rfbi_hwmod_class,
1565         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1566         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1567         .main_clk       = "dss_fck",
1568         .prcm = {
1569                 .omap4 = {
1570                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1571                 },
1572         },
1573         .slaves         = omap44xx_dss_rfbi_slaves,
1574         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1575         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1576 };
1577
1578 /*
1579  * 'venc' class
1580  * video encoder
1581  */
1582
1583 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1584         .name   = "venc",
1585 };
1586
1587 /* dss_venc */
1588 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1589 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1590         {
1591                 .pa_start       = 0x58003000,
1592                 .pa_end         = 0x580030ff,
1593                 .flags          = ADDR_TYPE_RT
1594         },
1595 };
1596
1597 /* l3_main_2 -> dss_venc */
1598 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1599         .master         = &omap44xx_l3_main_2_hwmod,
1600         .slave          = &omap44xx_dss_venc_hwmod,
1601         .clk            = "l3_div_ck",
1602         .addr           = omap44xx_dss_venc_dma_addrs,
1603         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1604         .user           = OCP_USER_SDMA,
1605 };
1606
1607 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1608         {
1609                 .pa_start       = 0x48043000,
1610                 .pa_end         = 0x480430ff,
1611                 .flags          = ADDR_TYPE_RT
1612         },
1613 };
1614
1615 /* l4_per -> dss_venc */
1616 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1617         .master         = &omap44xx_l4_per_hwmod,
1618         .slave          = &omap44xx_dss_venc_hwmod,
1619         .clk            = "l4_div_ck",
1620         .addr           = omap44xx_dss_venc_addrs,
1621         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1622         .user           = OCP_USER_MPU,
1623 };
1624
1625 /* dss_venc slave ports */
1626 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1627         &omap44xx_l3_main_2__dss_venc,
1628         &omap44xx_l4_per__dss_venc,
1629 };
1630
1631 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1632         .name           = "dss_venc",
1633         .class          = &omap44xx_venc_hwmod_class,
1634         .main_clk       = "dss_fck",
1635         .prcm = {
1636                 .omap4 = {
1637                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1638                 },
1639         },
1640         .slaves         = omap44xx_dss_venc_slaves,
1641         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1642         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1643 };
1644
1645 /*
1646  * 'gpio' class
1647  * general purpose io module
1648  */
1649
1650 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1651         .rev_offs       = 0x0000,
1652         .sysc_offs      = 0x0010,
1653         .syss_offs      = 0x0114,
1654         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1655                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1656                            SYSS_HAS_RESET_STATUS),
1657         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1658                            SIDLE_SMART_WKUP),
1659         .sysc_fields    = &omap_hwmod_sysc_type1,
1660 };
1661
1662 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1663         .name   = "gpio",
1664         .sysc   = &omap44xx_gpio_sysc,
1665         .rev    = 2,
1666 };
1667
1668 /* gpio dev_attr */
1669 static struct omap_gpio_dev_attr gpio_dev_attr = {
1670         .bank_width     = 32,
1671         .dbck_flag      = true,
1672 };
1673
1674 /* gpio1 */
1675 static struct omap_hwmod omap44xx_gpio1_hwmod;
1676 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1677         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1678 };
1679
1680 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1681         {
1682                 .pa_start       = 0x4a310000,
1683                 .pa_end         = 0x4a3101ff,
1684                 .flags          = ADDR_TYPE_RT
1685         },
1686 };
1687
1688 /* l4_wkup -> gpio1 */
1689 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1690         .master         = &omap44xx_l4_wkup_hwmod,
1691         .slave          = &omap44xx_gpio1_hwmod,
1692         .clk            = "l4_wkup_clk_mux_ck",
1693         .addr           = omap44xx_gpio1_addrs,
1694         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1696 };
1697
1698 /* gpio1 slave ports */
1699 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1700         &omap44xx_l4_wkup__gpio1,
1701 };
1702
1703 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1704         { .role = "dbclk", .clk = "gpio1_dbclk" },
1705 };
1706
1707 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1708         .name           = "gpio1",
1709         .class          = &omap44xx_gpio_hwmod_class,
1710         .mpu_irqs       = omap44xx_gpio1_irqs,
1711         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1712         .main_clk       = "gpio1_ick",
1713         .prcm = {
1714                 .omap4 = {
1715                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1716                 },
1717         },
1718         .opt_clks       = gpio1_opt_clks,
1719         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1720         .dev_attr       = &gpio_dev_attr,
1721         .slaves         = omap44xx_gpio1_slaves,
1722         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1723         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1724 };
1725
1726 /* gpio2 */
1727 static struct omap_hwmod omap44xx_gpio2_hwmod;
1728 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1729         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1730 };
1731
1732 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1733         {
1734                 .pa_start       = 0x48055000,
1735                 .pa_end         = 0x480551ff,
1736                 .flags          = ADDR_TYPE_RT
1737         },
1738 };
1739
1740 /* l4_per -> gpio2 */
1741 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1742         .master         = &omap44xx_l4_per_hwmod,
1743         .slave          = &omap44xx_gpio2_hwmod,
1744         .clk            = "l4_div_ck",
1745         .addr           = omap44xx_gpio2_addrs,
1746         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1748 };
1749
1750 /* gpio2 slave ports */
1751 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1752         &omap44xx_l4_per__gpio2,
1753 };
1754
1755 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1756         { .role = "dbclk", .clk = "gpio2_dbclk" },
1757 };
1758
1759 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1760         .name           = "gpio2",
1761         .class          = &omap44xx_gpio_hwmod_class,
1762         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1763         .mpu_irqs       = omap44xx_gpio2_irqs,
1764         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1765         .main_clk       = "gpio2_ick",
1766         .prcm = {
1767                 .omap4 = {
1768                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1769                 },
1770         },
1771         .opt_clks       = gpio2_opt_clks,
1772         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1773         .dev_attr       = &gpio_dev_attr,
1774         .slaves         = omap44xx_gpio2_slaves,
1775         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1776         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1777 };
1778
1779 /* gpio3 */
1780 static struct omap_hwmod omap44xx_gpio3_hwmod;
1781 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1782         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1783 };
1784
1785 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1786         {
1787                 .pa_start       = 0x48057000,
1788                 .pa_end         = 0x480571ff,
1789                 .flags          = ADDR_TYPE_RT
1790         },
1791 };
1792
1793 /* l4_per -> gpio3 */
1794 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1795         .master         = &omap44xx_l4_per_hwmod,
1796         .slave          = &omap44xx_gpio3_hwmod,
1797         .clk            = "l4_div_ck",
1798         .addr           = omap44xx_gpio3_addrs,
1799         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1801 };
1802
1803 /* gpio3 slave ports */
1804 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1805         &omap44xx_l4_per__gpio3,
1806 };
1807
1808 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1809         { .role = "dbclk", .clk = "gpio3_dbclk" },
1810 };
1811
1812 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1813         .name           = "gpio3",
1814         .class          = &omap44xx_gpio_hwmod_class,
1815         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1816         .mpu_irqs       = omap44xx_gpio3_irqs,
1817         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1818         .main_clk       = "gpio3_ick",
1819         .prcm = {
1820                 .omap4 = {
1821                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1822                 },
1823         },
1824         .opt_clks       = gpio3_opt_clks,
1825         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1826         .dev_attr       = &gpio_dev_attr,
1827         .slaves         = omap44xx_gpio3_slaves,
1828         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1829         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1830 };
1831
1832 /* gpio4 */
1833 static struct omap_hwmod omap44xx_gpio4_hwmod;
1834 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1835         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1836 };
1837
1838 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1839         {
1840                 .pa_start       = 0x48059000,
1841                 .pa_end         = 0x480591ff,
1842                 .flags          = ADDR_TYPE_RT
1843         },
1844 };
1845
1846 /* l4_per -> gpio4 */
1847 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1848         .master         = &omap44xx_l4_per_hwmod,
1849         .slave          = &omap44xx_gpio4_hwmod,
1850         .clk            = "l4_div_ck",
1851         .addr           = omap44xx_gpio4_addrs,
1852         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1854 };
1855
1856 /* gpio4 slave ports */
1857 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1858         &omap44xx_l4_per__gpio4,
1859 };
1860
1861 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1862         { .role = "dbclk", .clk = "gpio4_dbclk" },
1863 };
1864
1865 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1866         .name           = "gpio4",
1867         .class          = &omap44xx_gpio_hwmod_class,
1868         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1869         .mpu_irqs       = omap44xx_gpio4_irqs,
1870         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1871         .main_clk       = "gpio4_ick",
1872         .prcm = {
1873                 .omap4 = {
1874                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1875                 },
1876         },
1877         .opt_clks       = gpio4_opt_clks,
1878         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1879         .dev_attr       = &gpio_dev_attr,
1880         .slaves         = omap44xx_gpio4_slaves,
1881         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1882         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1883 };
1884
1885 /* gpio5 */
1886 static struct omap_hwmod omap44xx_gpio5_hwmod;
1887 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1888         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1889 };
1890
1891 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1892         {
1893                 .pa_start       = 0x4805b000,
1894                 .pa_end         = 0x4805b1ff,
1895                 .flags          = ADDR_TYPE_RT
1896         },
1897 };
1898
1899 /* l4_per -> gpio5 */
1900 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1901         .master         = &omap44xx_l4_per_hwmod,
1902         .slave          = &omap44xx_gpio5_hwmod,
1903         .clk            = "l4_div_ck",
1904         .addr           = omap44xx_gpio5_addrs,
1905         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1907 };
1908
1909 /* gpio5 slave ports */
1910 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1911         &omap44xx_l4_per__gpio5,
1912 };
1913
1914 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1915         { .role = "dbclk", .clk = "gpio5_dbclk" },
1916 };
1917
1918 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1919         .name           = "gpio5",
1920         .class          = &omap44xx_gpio_hwmod_class,
1921         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1922         .mpu_irqs       = omap44xx_gpio5_irqs,
1923         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1924         .main_clk       = "gpio5_ick",
1925         .prcm = {
1926                 .omap4 = {
1927                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1928                 },
1929         },
1930         .opt_clks       = gpio5_opt_clks,
1931         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1932         .dev_attr       = &gpio_dev_attr,
1933         .slaves         = omap44xx_gpio5_slaves,
1934         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1935         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1936 };
1937
1938 /* gpio6 */
1939 static struct omap_hwmod omap44xx_gpio6_hwmod;
1940 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1941         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1942 };
1943
1944 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1945         {
1946                 .pa_start       = 0x4805d000,
1947                 .pa_end         = 0x4805d1ff,
1948                 .flags          = ADDR_TYPE_RT
1949         },
1950 };
1951
1952 /* l4_per -> gpio6 */
1953 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1954         .master         = &omap44xx_l4_per_hwmod,
1955         .slave          = &omap44xx_gpio6_hwmod,
1956         .clk            = "l4_div_ck",
1957         .addr           = omap44xx_gpio6_addrs,
1958         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1960 };
1961
1962 /* gpio6 slave ports */
1963 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1964         &omap44xx_l4_per__gpio6,
1965 };
1966
1967 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1968         { .role = "dbclk", .clk = "gpio6_dbclk" },
1969 };
1970
1971 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1972         .name           = "gpio6",
1973         .class          = &omap44xx_gpio_hwmod_class,
1974         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1975         .mpu_irqs       = omap44xx_gpio6_irqs,
1976         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1977         .main_clk       = "gpio6_ick",
1978         .prcm = {
1979                 .omap4 = {
1980                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1981                 },
1982         },
1983         .opt_clks       = gpio6_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1985         .dev_attr       = &gpio_dev_attr,
1986         .slaves         = omap44xx_gpio6_slaves,
1987         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1988         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1989 };
1990
1991 /*
1992  * 'hsi' class
1993  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1994  * serial if)
1995  */
1996
1997 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1998         .rev_offs       = 0x0000,
1999         .sysc_offs      = 0x0010,
2000         .syss_offs      = 0x0014,
2001         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2002                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2003                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2004         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2005                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2006                            MSTANDBY_SMART),
2007         .sysc_fields    = &omap_hwmod_sysc_type1,
2008 };
2009
2010 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2011         .name   = "hsi",
2012         .sysc   = &omap44xx_hsi_sysc,
2013 };
2014
2015 /* hsi */
2016 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2017         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2018         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2019         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2020 };
2021
2022 /* hsi master ports */
2023 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2024         &omap44xx_hsi__l3_main_2,
2025 };
2026
2027 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2028         {
2029                 .pa_start       = 0x4a058000,
2030                 .pa_end         = 0x4a05bfff,
2031                 .flags          = ADDR_TYPE_RT
2032         },
2033 };
2034
2035 /* l4_cfg -> hsi */
2036 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2037         .master         = &omap44xx_l4_cfg_hwmod,
2038         .slave          = &omap44xx_hsi_hwmod,
2039         .clk            = "l4_div_ck",
2040         .addr           = omap44xx_hsi_addrs,
2041         .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
2042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2043 };
2044
2045 /* hsi slave ports */
2046 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2047         &omap44xx_l4_cfg__hsi,
2048 };
2049
2050 static struct omap_hwmod omap44xx_hsi_hwmod = {
2051         .name           = "hsi",
2052         .class          = &omap44xx_hsi_hwmod_class,
2053         .mpu_irqs       = omap44xx_hsi_irqs,
2054         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
2055         .main_clk       = "hsi_fck",
2056         .prcm           = {
2057                 .omap4 = {
2058                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2059                 },
2060         },
2061         .slaves         = omap44xx_hsi_slaves,
2062         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2063         .masters        = omap44xx_hsi_masters,
2064         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2065         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2066 };
2067
2068 /*
2069  * 'i2c' class
2070  * multimaster high-speed i2c controller
2071  */
2072
2073 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2074         .sysc_offs      = 0x0010,
2075         .syss_offs      = 0x0090,
2076         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2077                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2078                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2079         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2080                            SIDLE_SMART_WKUP),
2081         .sysc_fields    = &omap_hwmod_sysc_type1,
2082 };
2083
2084 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2085         .name   = "i2c",
2086         .sysc   = &omap44xx_i2c_sysc,
2087 };
2088
2089 /* i2c1 */
2090 static struct omap_hwmod omap44xx_i2c1_hwmod;
2091 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2092         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2093 };
2094
2095 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2096         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2097         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2098 };
2099
2100 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2101         {
2102                 .pa_start       = 0x48070000,
2103                 .pa_end         = 0x480700ff,
2104                 .flags          = ADDR_TYPE_RT
2105         },
2106 };
2107
2108 /* l4_per -> i2c1 */
2109 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2110         .master         = &omap44xx_l4_per_hwmod,
2111         .slave          = &omap44xx_i2c1_hwmod,
2112         .clk            = "l4_div_ck",
2113         .addr           = omap44xx_i2c1_addrs,
2114         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
2115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2116 };
2117
2118 /* i2c1 slave ports */
2119 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2120         &omap44xx_l4_per__i2c1,
2121 };
2122
2123 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2124         .name           = "i2c1",
2125         .class          = &omap44xx_i2c_hwmod_class,
2126         .flags          = HWMOD_INIT_NO_RESET,
2127         .mpu_irqs       = omap44xx_i2c1_irqs,
2128         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
2129         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2130         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2131         .main_clk       = "i2c1_fck",
2132         .prcm = {
2133                 .omap4 = {
2134                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2135                 },
2136         },
2137         .slaves         = omap44xx_i2c1_slaves,
2138         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2139         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2140 };
2141
2142 /* i2c2 */
2143 static struct omap_hwmod omap44xx_i2c2_hwmod;
2144 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2145         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2146 };
2147
2148 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2149         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2150         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2151 };
2152
2153 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2154         {
2155                 .pa_start       = 0x48072000,
2156                 .pa_end         = 0x480720ff,
2157                 .flags          = ADDR_TYPE_RT
2158         },
2159 };
2160
2161 /* l4_per -> i2c2 */
2162 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2163         .master         = &omap44xx_l4_per_hwmod,
2164         .slave          = &omap44xx_i2c2_hwmod,
2165         .clk            = "l4_div_ck",
2166         .addr           = omap44xx_i2c2_addrs,
2167         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
2168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2169 };
2170
2171 /* i2c2 slave ports */
2172 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2173         &omap44xx_l4_per__i2c2,
2174 };
2175
2176 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2177         .name           = "i2c2",
2178         .class          = &omap44xx_i2c_hwmod_class,
2179         .flags          = HWMOD_INIT_NO_RESET,
2180         .mpu_irqs       = omap44xx_i2c2_irqs,
2181         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
2182         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2183         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2184         .main_clk       = "i2c2_fck",
2185         .prcm = {
2186                 .omap4 = {
2187                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2188                 },
2189         },
2190         .slaves         = omap44xx_i2c2_slaves,
2191         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2193 };
2194
2195 /* i2c3 */
2196 static struct omap_hwmod omap44xx_i2c3_hwmod;
2197 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2198         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2199 };
2200
2201 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2202         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2203         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2204 };
2205
2206 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2207         {
2208                 .pa_start       = 0x48060000,
2209                 .pa_end         = 0x480600ff,
2210                 .flags          = ADDR_TYPE_RT
2211         },
2212 };
2213
2214 /* l4_per -> i2c3 */
2215 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2216         .master         = &omap44xx_l4_per_hwmod,
2217         .slave          = &omap44xx_i2c3_hwmod,
2218         .clk            = "l4_div_ck",
2219         .addr           = omap44xx_i2c3_addrs,
2220         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
2221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2222 };
2223
2224 /* i2c3 slave ports */
2225 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2226         &omap44xx_l4_per__i2c3,
2227 };
2228
2229 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2230         .name           = "i2c3",
2231         .class          = &omap44xx_i2c_hwmod_class,
2232         .flags          = HWMOD_INIT_NO_RESET,
2233         .mpu_irqs       = omap44xx_i2c3_irqs,
2234         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
2235         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2236         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2237         .main_clk       = "i2c3_fck",
2238         .prcm = {
2239                 .omap4 = {
2240                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2241                 },
2242         },
2243         .slaves         = omap44xx_i2c3_slaves,
2244         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2245         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2246 };
2247
2248 /* i2c4 */
2249 static struct omap_hwmod omap44xx_i2c4_hwmod;
2250 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2251         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2252 };
2253
2254 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2255         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2256         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2257 };
2258
2259 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2260         {
2261                 .pa_start       = 0x48350000,
2262                 .pa_end         = 0x483500ff,
2263                 .flags          = ADDR_TYPE_RT
2264         },
2265 };
2266
2267 /* l4_per -> i2c4 */
2268 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2269         .master         = &omap44xx_l4_per_hwmod,
2270         .slave          = &omap44xx_i2c4_hwmod,
2271         .clk            = "l4_div_ck",
2272         .addr           = omap44xx_i2c4_addrs,
2273         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276
2277 /* i2c4 slave ports */
2278 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2279         &omap44xx_l4_per__i2c4,
2280 };
2281
2282 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2283         .name           = "i2c4",
2284         .class          = &omap44xx_i2c_hwmod_class,
2285         .flags          = HWMOD_INIT_NO_RESET,
2286         .mpu_irqs       = omap44xx_i2c4_irqs,
2287         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
2288         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2289         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2290         .main_clk       = "i2c4_fck",
2291         .prcm = {
2292                 .omap4 = {
2293                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2294                 },
2295         },
2296         .slaves         = omap44xx_i2c4_slaves,
2297         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2298         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2299 };
2300
2301 /*
2302  * 'ipu' class
2303  * imaging processor unit
2304  */
2305
2306 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2307         .name   = "ipu",
2308 };
2309
2310 /* ipu */
2311 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2312         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2313 };
2314
2315 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2316         { .name = "cpu0", .rst_shift = 0 },
2317 };
2318
2319 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2320         { .name = "cpu1", .rst_shift = 1 },
2321 };
2322
2323 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2324         { .name = "mmu_cache", .rst_shift = 2 },
2325 };
2326
2327 /* ipu master ports */
2328 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2329         &omap44xx_ipu__l3_main_2,
2330 };
2331
2332 /* l3_main_2 -> ipu */
2333 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2334         .master         = &omap44xx_l3_main_2_hwmod,
2335         .slave          = &omap44xx_ipu_hwmod,
2336         .clk            = "l3_div_ck",
2337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2338 };
2339
2340 /* ipu slave ports */
2341 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2342         &omap44xx_l3_main_2__ipu,
2343 };
2344
2345 /* Pseudo hwmod for reset control purpose only */
2346 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2347         .name           = "ipu_c0",
2348         .class          = &omap44xx_ipu_hwmod_class,
2349         .flags          = HWMOD_INIT_NO_RESET,
2350         .rst_lines      = omap44xx_ipu_c0_resets,
2351         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2352         .prcm           = {
2353                 .omap4 = {
2354                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2355                 },
2356         },
2357         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2358 };
2359
2360 /* Pseudo hwmod for reset control purpose only */
2361 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2362         .name           = "ipu_c1",
2363         .class          = &omap44xx_ipu_hwmod_class,
2364         .flags          = HWMOD_INIT_NO_RESET,
2365         .rst_lines      = omap44xx_ipu_c1_resets,
2366         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2367         .prcm           = {
2368                 .omap4 = {
2369                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2370                 },
2371         },
2372         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2373 };
2374
2375 static struct omap_hwmod omap44xx_ipu_hwmod = {
2376         .name           = "ipu",
2377         .class          = &omap44xx_ipu_hwmod_class,
2378         .mpu_irqs       = omap44xx_ipu_irqs,
2379         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
2380         .rst_lines      = omap44xx_ipu_resets,
2381         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2382         .main_clk       = "ipu_fck",
2383         .prcm           = {
2384                 .omap4 = {
2385                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2386                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2387                 },
2388         },
2389         .slaves         = omap44xx_ipu_slaves,
2390         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2391         .masters        = omap44xx_ipu_masters,
2392         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2393         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2394 };
2395
2396 /*
2397  * 'iss' class
2398  * external images sensor pixel data processor
2399  */
2400
2401 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2402         .rev_offs       = 0x0000,
2403         .sysc_offs      = 0x0010,
2404         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2405                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2407                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2408                            MSTANDBY_SMART),
2409         .sysc_fields    = &omap_hwmod_sysc_type2,
2410 };
2411
2412 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2413         .name   = "iss",
2414         .sysc   = &omap44xx_iss_sysc,
2415 };
2416
2417 /* iss */
2418 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2419         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2420 };
2421
2422 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2423         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2424         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2425         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2426         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2427 };
2428
2429 /* iss master ports */
2430 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2431         &omap44xx_iss__l3_main_2,
2432 };
2433
2434 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2435         {
2436                 .pa_start       = 0x52000000,
2437                 .pa_end         = 0x520000ff,
2438                 .flags          = ADDR_TYPE_RT
2439         },
2440 };
2441
2442 /* l3_main_2 -> iss */
2443 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2444         .master         = &omap44xx_l3_main_2_hwmod,
2445         .slave          = &omap44xx_iss_hwmod,
2446         .clk            = "l3_div_ck",
2447         .addr           = omap44xx_iss_addrs,
2448         .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
2449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2450 };
2451
2452 /* iss slave ports */
2453 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2454         &omap44xx_l3_main_2__iss,
2455 };
2456
2457 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2458         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2459 };
2460
2461 static struct omap_hwmod omap44xx_iss_hwmod = {
2462         .name           = "iss",
2463         .class          = &omap44xx_iss_hwmod_class,
2464         .mpu_irqs       = omap44xx_iss_irqs,
2465         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
2466         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2467         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2468         .main_clk       = "iss_fck",
2469         .prcm           = {
2470                 .omap4 = {
2471                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2472                 },
2473         },
2474         .opt_clks       = iss_opt_clks,
2475         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2476         .slaves         = omap44xx_iss_slaves,
2477         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2478         .masters        = omap44xx_iss_masters,
2479         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2480         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2481 };
2482
2483 /*
2484  * 'iva' class
2485  * multi-standard video encoder/decoder hardware accelerator
2486  */
2487
2488 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2489         .name   = "iva",
2490 };
2491
2492 /* iva */
2493 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2494         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2495         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2496         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2497 };
2498
2499 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2500         { .name = "logic", .rst_shift = 2 },
2501 };
2502
2503 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2504         { .name = "seq0", .rst_shift = 0 },
2505 };
2506
2507 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2508         { .name = "seq1", .rst_shift = 1 },
2509 };
2510
2511 /* iva master ports */
2512 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2513         &omap44xx_iva__l3_main_2,
2514         &omap44xx_iva__l3_instr,
2515 };
2516
2517 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2518         {
2519                 .pa_start       = 0x5a000000,
2520                 .pa_end         = 0x5a07ffff,
2521                 .flags          = ADDR_TYPE_RT
2522         },
2523 };
2524
2525 /* l3_main_2 -> iva */
2526 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2527         .master         = &omap44xx_l3_main_2_hwmod,
2528         .slave          = &omap44xx_iva_hwmod,
2529         .clk            = "l3_div_ck",
2530         .addr           = omap44xx_iva_addrs,
2531         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
2532         .user           = OCP_USER_MPU,
2533 };
2534
2535 /* iva slave ports */
2536 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2537         &omap44xx_dsp__iva,
2538         &omap44xx_l3_main_2__iva,
2539 };
2540
2541 /* Pseudo hwmod for reset control purpose only */
2542 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2543         .name           = "iva_seq0",
2544         .class          = &omap44xx_iva_hwmod_class,
2545         .flags          = HWMOD_INIT_NO_RESET,
2546         .rst_lines      = omap44xx_iva_seq0_resets,
2547         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2548         .prcm = {
2549                 .omap4 = {
2550                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2551                 },
2552         },
2553         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2554 };
2555
2556 /* Pseudo hwmod for reset control purpose only */
2557 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2558         .name           = "iva_seq1",
2559         .class          = &omap44xx_iva_hwmod_class,
2560         .flags          = HWMOD_INIT_NO_RESET,
2561         .rst_lines      = omap44xx_iva_seq1_resets,
2562         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2563         .prcm = {
2564                 .omap4 = {
2565                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2566                 },
2567         },
2568         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2569 };
2570
2571 static struct omap_hwmod omap44xx_iva_hwmod = {
2572         .name           = "iva",
2573         .class          = &omap44xx_iva_hwmod_class,
2574         .mpu_irqs       = omap44xx_iva_irqs,
2575         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
2576         .rst_lines      = omap44xx_iva_resets,
2577         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2578         .main_clk       = "iva_fck",
2579         .prcm = {
2580                 .omap4 = {
2581                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2582                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2583                 },
2584         },
2585         .slaves         = omap44xx_iva_slaves,
2586         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2587         .masters        = omap44xx_iva_masters,
2588         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2589         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2590 };
2591
2592 /*
2593  * 'kbd' class
2594  * keyboard controller
2595  */
2596
2597 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2598         .rev_offs       = 0x0000,
2599         .sysc_offs      = 0x0010,
2600         .syss_offs      = 0x0014,
2601         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2602                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2603                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2604                            SYSS_HAS_RESET_STATUS),
2605         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2606         .sysc_fields    = &omap_hwmod_sysc_type1,
2607 };
2608
2609 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2610         .name   = "kbd",
2611         .sysc   = &omap44xx_kbd_sysc,
2612 };
2613
2614 /* kbd */
2615 static struct omap_hwmod omap44xx_kbd_hwmod;
2616 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2617         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2618 };
2619
2620 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2621         {
2622                 .pa_start       = 0x4a31c000,
2623                 .pa_end         = 0x4a31c07f,
2624                 .flags          = ADDR_TYPE_RT
2625         },
2626 };
2627
2628 /* l4_wkup -> kbd */
2629 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2630         .master         = &omap44xx_l4_wkup_hwmod,
2631         .slave          = &omap44xx_kbd_hwmod,
2632         .clk            = "l4_wkup_clk_mux_ck",
2633         .addr           = omap44xx_kbd_addrs,
2634         .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
2635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2636 };
2637
2638 /* kbd slave ports */
2639 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2640         &omap44xx_l4_wkup__kbd,
2641 };
2642
2643 static struct omap_hwmod omap44xx_kbd_hwmod = {
2644         .name           = "kbd",
2645         .class          = &omap44xx_kbd_hwmod_class,
2646         .mpu_irqs       = omap44xx_kbd_irqs,
2647         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
2648         .main_clk       = "kbd_fck",
2649         .prcm           = {
2650                 .omap4 = {
2651                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2652                 },
2653         },
2654         .slaves         = omap44xx_kbd_slaves,
2655         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2656         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2657 };
2658
2659 /*
2660  * 'mailbox' class
2661  * mailbox module allowing communication between the on-chip processors using a
2662  * queued mailbox-interrupt mechanism.
2663  */
2664
2665 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2666         .rev_offs       = 0x0000,
2667         .sysc_offs      = 0x0010,
2668         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2669                            SYSC_HAS_SOFTRESET),
2670         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2671         .sysc_fields    = &omap_hwmod_sysc_type2,
2672 };
2673
2674 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2675         .name   = "mailbox",
2676         .sysc   = &omap44xx_mailbox_sysc,
2677 };
2678
2679 /* mailbox */
2680 static struct omap_hwmod omap44xx_mailbox_hwmod;
2681 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2682         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2683 };
2684
2685 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2686         {
2687                 .pa_start       = 0x4a0f4000,
2688                 .pa_end         = 0x4a0f41ff,
2689                 .flags          = ADDR_TYPE_RT
2690         },
2691 };
2692
2693 /* l4_cfg -> mailbox */
2694 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2695         .master         = &omap44xx_l4_cfg_hwmod,
2696         .slave          = &omap44xx_mailbox_hwmod,
2697         .clk            = "l4_div_ck",
2698         .addr           = omap44xx_mailbox_addrs,
2699         .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
2700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2701 };
2702
2703 /* mailbox slave ports */
2704 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2705         &omap44xx_l4_cfg__mailbox,
2706 };
2707
2708 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2709         .name           = "mailbox",
2710         .class          = &omap44xx_mailbox_hwmod_class,
2711         .mpu_irqs       = omap44xx_mailbox_irqs,
2712         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
2713         .prcm           = {
2714                 .omap4 = {
2715                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2716                 },
2717         },
2718         .slaves         = omap44xx_mailbox_slaves,
2719         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2720         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2721 };
2722
2723 /*
2724  * 'mcbsp' class
2725  * multi channel buffered serial port controller
2726  */
2727
2728 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2729         .sysc_offs      = 0x008c,
2730         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2731                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2732         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2733         .sysc_fields    = &omap_hwmod_sysc_type1,
2734 };
2735
2736 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2737         .name   = "mcbsp",
2738         .sysc   = &omap44xx_mcbsp_sysc,
2739 };
2740
2741 /* mcbsp1 */
2742 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2743 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2744         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2745 };
2746
2747 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2748         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2749         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2750 };
2751
2752 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2753         {
2754                 .pa_start       = 0x40122000,
2755                 .pa_end         = 0x401220ff,
2756                 .flags          = ADDR_TYPE_RT
2757         },
2758 };
2759
2760 /* l4_abe -> mcbsp1 */
2761 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2762         .master         = &omap44xx_l4_abe_hwmod,
2763         .slave          = &omap44xx_mcbsp1_hwmod,
2764         .clk            = "ocp_abe_iclk",
2765         .addr           = omap44xx_mcbsp1_addrs,
2766         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2767         .user           = OCP_USER_MPU,
2768 };
2769
2770 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2771         {
2772                 .pa_start       = 0x49022000,
2773                 .pa_end         = 0x490220ff,
2774                 .flags          = ADDR_TYPE_RT
2775         },
2776 };
2777
2778 /* l4_abe -> mcbsp1 (dma) */
2779 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2780         .master         = &omap44xx_l4_abe_hwmod,
2781         .slave          = &omap44xx_mcbsp1_hwmod,
2782         .clk            = "ocp_abe_iclk",
2783         .addr           = omap44xx_mcbsp1_dma_addrs,
2784         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2785         .user           = OCP_USER_SDMA,
2786 };
2787
2788 /* mcbsp1 slave ports */
2789 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2790         &omap44xx_l4_abe__mcbsp1,
2791         &omap44xx_l4_abe__mcbsp1_dma,
2792 };
2793
2794 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2795         .name           = "mcbsp1",
2796         .class          = &omap44xx_mcbsp_hwmod_class,
2797         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2798         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2799         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2800         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2801         .main_clk       = "mcbsp1_fck",
2802         .prcm = {
2803                 .omap4 = {
2804                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2805                 },
2806         },
2807         .slaves         = omap44xx_mcbsp1_slaves,
2808         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2809         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2810 };
2811
2812 /* mcbsp2 */
2813 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2814 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2815         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2816 };
2817
2818 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2819         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2820         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2821 };
2822
2823 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2824         {
2825                 .pa_start       = 0x40124000,
2826                 .pa_end         = 0x401240ff,
2827                 .flags          = ADDR_TYPE_RT
2828         },
2829 };
2830
2831 /* l4_abe -> mcbsp2 */
2832 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2833         .master         = &omap44xx_l4_abe_hwmod,
2834         .slave          = &omap44xx_mcbsp2_hwmod,
2835         .clk            = "ocp_abe_iclk",
2836         .addr           = omap44xx_mcbsp2_addrs,
2837         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2838         .user           = OCP_USER_MPU,
2839 };
2840
2841 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2842         {
2843                 .pa_start       = 0x49024000,
2844                 .pa_end         = 0x490240ff,
2845                 .flags          = ADDR_TYPE_RT
2846         },
2847 };
2848
2849 /* l4_abe -> mcbsp2 (dma) */
2850 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2851         .master         = &omap44xx_l4_abe_hwmod,
2852         .slave          = &omap44xx_mcbsp2_hwmod,
2853         .clk            = "ocp_abe_iclk",
2854         .addr           = omap44xx_mcbsp2_dma_addrs,
2855         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2856         .user           = OCP_USER_SDMA,
2857 };
2858
2859 /* mcbsp2 slave ports */
2860 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2861         &omap44xx_l4_abe__mcbsp2,
2862         &omap44xx_l4_abe__mcbsp2_dma,
2863 };
2864
2865 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2866         .name           = "mcbsp2",
2867         .class          = &omap44xx_mcbsp_hwmod_class,
2868         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2869         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2870         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2871         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2872         .main_clk       = "mcbsp2_fck",
2873         .prcm = {
2874                 .omap4 = {
2875                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2876                 },
2877         },
2878         .slaves         = omap44xx_mcbsp2_slaves,
2879         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2880         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2881 };
2882
2883 /* mcbsp3 */
2884 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2885 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2886         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2887 };
2888
2889 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2890         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2891         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2892 };
2893
2894 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2895         {
2896                 .pa_start       = 0x40126000,
2897                 .pa_end         = 0x401260ff,
2898                 .flags          = ADDR_TYPE_RT
2899         },
2900 };
2901
2902 /* l4_abe -> mcbsp3 */
2903 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2904         .master         = &omap44xx_l4_abe_hwmod,
2905         .slave          = &omap44xx_mcbsp3_hwmod,
2906         .clk            = "ocp_abe_iclk",
2907         .addr           = omap44xx_mcbsp3_addrs,
2908         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2909         .user           = OCP_USER_MPU,
2910 };
2911
2912 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2913         {
2914                 .pa_start       = 0x49026000,
2915                 .pa_end         = 0x490260ff,
2916                 .flags          = ADDR_TYPE_RT
2917         },
2918 };
2919
2920 /* l4_abe -> mcbsp3 (dma) */
2921 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2922         .master         = &omap44xx_l4_abe_hwmod,
2923         .slave          = &omap44xx_mcbsp3_hwmod,
2924         .clk            = "ocp_abe_iclk",
2925         .addr           = omap44xx_mcbsp3_dma_addrs,
2926         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2927         .user           = OCP_USER_SDMA,
2928 };
2929
2930 /* mcbsp3 slave ports */
2931 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2932         &omap44xx_l4_abe__mcbsp3,
2933         &omap44xx_l4_abe__mcbsp3_dma,
2934 };
2935
2936 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2937         .name           = "mcbsp3",
2938         .class          = &omap44xx_mcbsp_hwmod_class,
2939         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2940         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2941         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2942         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2943         .main_clk       = "mcbsp3_fck",
2944         .prcm = {
2945                 .omap4 = {
2946                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2947                 },
2948         },
2949         .slaves         = omap44xx_mcbsp3_slaves,
2950         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2951         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2952 };
2953
2954 /* mcbsp4 */
2955 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2956 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2957         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2958 };
2959
2960 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2961         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2962         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2963 };
2964
2965 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2966         {
2967                 .pa_start       = 0x48096000,
2968                 .pa_end         = 0x480960ff,
2969                 .flags          = ADDR_TYPE_RT
2970         },
2971 };
2972
2973 /* l4_per -> mcbsp4 */
2974 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2975         .master         = &omap44xx_l4_per_hwmod,
2976         .slave          = &omap44xx_mcbsp4_hwmod,
2977         .clk            = "l4_div_ck",
2978         .addr           = omap44xx_mcbsp4_addrs,
2979         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
2980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2981 };
2982
2983 /* mcbsp4 slave ports */
2984 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
2985         &omap44xx_l4_per__mcbsp4,
2986 };
2987
2988 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2989         .name           = "mcbsp4",
2990         .class          = &omap44xx_mcbsp_hwmod_class,
2991         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2992         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
2993         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2994         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
2995         .main_clk       = "mcbsp4_fck",
2996         .prcm = {
2997                 .omap4 = {
2998                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2999                 },
3000         },
3001         .slaves         = omap44xx_mcbsp4_slaves,
3002         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3003         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3004 };
3005
3006 /*
3007  * 'mcpdm' class
3008  * multi channel pdm controller (proprietary interface with phoenix power
3009  * ic)
3010  */
3011
3012 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3013         .rev_offs       = 0x0000,
3014         .sysc_offs      = 0x0010,
3015         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3016                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3017         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3018                            SIDLE_SMART_WKUP),
3019         .sysc_fields    = &omap_hwmod_sysc_type2,
3020 };
3021
3022 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3023         .name   = "mcpdm",
3024         .sysc   = &omap44xx_mcpdm_sysc,
3025 };
3026
3027 /* mcpdm */
3028 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3029 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3030         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3031 };
3032
3033 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3034         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3035         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3036 };
3037
3038 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3039         {
3040                 .pa_start       = 0x40132000,
3041                 .pa_end         = 0x4013207f,
3042                 .flags          = ADDR_TYPE_RT
3043         },
3044 };
3045
3046 /* l4_abe -> mcpdm */
3047 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3048         .master         = &omap44xx_l4_abe_hwmod,
3049         .slave          = &omap44xx_mcpdm_hwmod,
3050         .clk            = "ocp_abe_iclk",
3051         .addr           = omap44xx_mcpdm_addrs,
3052         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3053         .user           = OCP_USER_MPU,
3054 };
3055
3056 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3057         {
3058                 .pa_start       = 0x49032000,
3059                 .pa_end         = 0x4903207f,
3060                 .flags          = ADDR_TYPE_RT
3061         },
3062 };
3063
3064 /* l4_abe -> mcpdm (dma) */
3065 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3066         .master         = &omap44xx_l4_abe_hwmod,
3067         .slave          = &omap44xx_mcpdm_hwmod,
3068         .clk            = "ocp_abe_iclk",
3069         .addr           = omap44xx_mcpdm_dma_addrs,
3070         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3071         .user           = OCP_USER_SDMA,
3072 };
3073
3074 /* mcpdm slave ports */
3075 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3076         &omap44xx_l4_abe__mcpdm,
3077         &omap44xx_l4_abe__mcpdm_dma,
3078 };
3079
3080 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3081         .name           = "mcpdm",
3082         .class          = &omap44xx_mcpdm_hwmod_class,
3083         .mpu_irqs       = omap44xx_mcpdm_irqs,
3084         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3085         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3086         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3087         .main_clk       = "mcpdm_fck",
3088         .prcm           = {
3089                 .omap4 = {
3090                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3091                 },
3092         },
3093         .slaves         = omap44xx_mcpdm_slaves,
3094         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3095         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3096 };
3097
3098 /*
3099  * 'mcspi' class
3100  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3101  * bus
3102  */
3103
3104 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3105         .rev_offs       = 0x0000,
3106         .sysc_offs      = 0x0010,
3107         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3108                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3109         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3110                            SIDLE_SMART_WKUP),
3111         .sysc_fields    = &omap_hwmod_sysc_type2,
3112 };
3113
3114 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3115         .name   = "mcspi",
3116         .sysc   = &omap44xx_mcspi_sysc,
3117 };
3118
3119 /* mcspi1 */
3120 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3121 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3122         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3123 };
3124
3125 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3126         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3127         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3128         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3129         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3130         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3131         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3132         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3133         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3134 };
3135
3136 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3137         {
3138                 .pa_start       = 0x48098000,
3139                 .pa_end         = 0x480981ff,
3140                 .flags          = ADDR_TYPE_RT
3141         },
3142 };
3143
3144 /* l4_per -> mcspi1 */
3145 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3146         .master         = &omap44xx_l4_per_hwmod,
3147         .slave          = &omap44xx_mcspi1_hwmod,
3148         .clk            = "l4_div_ck",
3149         .addr           = omap44xx_mcspi1_addrs,
3150         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3152 };
3153
3154 /* mcspi1 slave ports */
3155 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3156         &omap44xx_l4_per__mcspi1,
3157 };
3158
3159 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3160         .name           = "mcspi1",
3161         .class          = &omap44xx_mcspi_hwmod_class,
3162         .mpu_irqs       = omap44xx_mcspi1_irqs,
3163         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3164         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3165         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3166         .main_clk       = "mcspi1_fck",
3167         .prcm = {
3168                 .omap4 = {
3169                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3170                 },
3171         },
3172         .slaves         = omap44xx_mcspi1_slaves,
3173         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3174         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3175 };
3176
3177 /* mcspi2 */
3178 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3179 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3180         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3181 };
3182
3183 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3184         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3185         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3186         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3187         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3188 };
3189
3190 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3191         {
3192                 .pa_start       = 0x4809a000,
3193                 .pa_end         = 0x4809a1ff,
3194                 .flags          = ADDR_TYPE_RT
3195         },
3196 };
3197
3198 /* l4_per -> mcspi2 */
3199 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3200         .master         = &omap44xx_l4_per_hwmod,
3201         .slave          = &omap44xx_mcspi2_hwmod,
3202         .clk            = "l4_div_ck",
3203         .addr           = omap44xx_mcspi2_addrs,
3204         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3206 };
3207
3208 /* mcspi2 slave ports */
3209 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3210         &omap44xx_l4_per__mcspi2,
3211 };
3212
3213 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3214         .name           = "mcspi2",
3215         .class          = &omap44xx_mcspi_hwmod_class,
3216         .mpu_irqs       = omap44xx_mcspi2_irqs,
3217         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3218         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3219         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3220         .main_clk       = "mcspi2_fck",
3221         .prcm = {
3222                 .omap4 = {
3223                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3224                 },
3225         },
3226         .slaves         = omap44xx_mcspi2_slaves,
3227         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3228         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3229 };
3230
3231 /* mcspi3 */
3232 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3233 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3234         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3235 };
3236
3237 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3238         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3239         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3240         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3241         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3242 };
3243
3244 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3245         {
3246                 .pa_start       = 0x480b8000,
3247                 .pa_end         = 0x480b81ff,
3248                 .flags          = ADDR_TYPE_RT
3249         },
3250 };
3251
3252 /* l4_per -> mcspi3 */
3253 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3254         .master         = &omap44xx_l4_per_hwmod,
3255         .slave          = &omap44xx_mcspi3_hwmod,
3256         .clk            = "l4_div_ck",
3257         .addr           = omap44xx_mcspi3_addrs,
3258         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3260 };
3261
3262 /* mcspi3 slave ports */
3263 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3264         &omap44xx_l4_per__mcspi3,
3265 };
3266
3267 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3268         .name           = "mcspi3",
3269         .class          = &omap44xx_mcspi_hwmod_class,
3270         .mpu_irqs       = omap44xx_mcspi3_irqs,
3271         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3272         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3273         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3274         .main_clk       = "mcspi3_fck",
3275         .prcm = {
3276                 .omap4 = {
3277                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3278                 },
3279         },
3280         .slaves         = omap44xx_mcspi3_slaves,
3281         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3282         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3283 };
3284
3285 /* mcspi4 */
3286 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3287 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3288         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3289 };
3290
3291 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3292         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3293         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3294 };
3295
3296 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3297         {
3298                 .pa_start       = 0x480ba000,
3299                 .pa_end         = 0x480ba1ff,
3300                 .flags          = ADDR_TYPE_RT
3301         },
3302 };
3303
3304 /* l4_per -> mcspi4 */
3305 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3306         .master         = &omap44xx_l4_per_hwmod,
3307         .slave          = &omap44xx_mcspi4_hwmod,
3308         .clk            = "l4_div_ck",
3309         .addr           = omap44xx_mcspi4_addrs,
3310         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* mcspi4 slave ports */
3315 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3316         &omap44xx_l4_per__mcspi4,
3317 };
3318
3319 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3320         .name           = "mcspi4",
3321         .class          = &omap44xx_mcspi_hwmod_class,
3322         .mpu_irqs       = omap44xx_mcspi4_irqs,
3323         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3324         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3325         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3326         .main_clk       = "mcspi4_fck",
3327         .prcm = {
3328                 .omap4 = {
3329                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3330                 },
3331         },
3332         .slaves         = omap44xx_mcspi4_slaves,
3333         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3334         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3335 };
3336
3337 /*
3338  * 'mmc' class
3339  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3340  */
3341
3342 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3343         .rev_offs       = 0x0000,
3344         .sysc_offs      = 0x0010,
3345         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3346                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3347                            SYSC_HAS_SOFTRESET),
3348         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3349                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3350                            MSTANDBY_SMART),
3351         .sysc_fields    = &omap_hwmod_sysc_type2,
3352 };
3353
3354 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3355         .name   = "mmc",
3356         .sysc   = &omap44xx_mmc_sysc,
3357 };
3358
3359 /* mmc1 */
3360 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3361         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3362 };
3363
3364 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3365         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3366         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3367 };
3368
3369 /* mmc1 master ports */
3370 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3371         &omap44xx_mmc1__l3_main_1,
3372 };
3373
3374 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3375         {
3376                 .pa_start       = 0x4809c000,
3377                 .pa_end         = 0x4809c3ff,
3378                 .flags          = ADDR_TYPE_RT
3379         },
3380 };
3381
3382 /* l4_per -> mmc1 */
3383 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3384         .master         = &omap44xx_l4_per_hwmod,
3385         .slave          = &omap44xx_mmc1_hwmod,
3386         .clk            = "l4_div_ck",
3387         .addr           = omap44xx_mmc1_addrs,
3388         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
3389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3390 };
3391
3392 /* mmc1 slave ports */
3393 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3394         &omap44xx_l4_per__mmc1,
3395 };
3396
3397 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3398         .name           = "mmc1",
3399         .class          = &omap44xx_mmc_hwmod_class,
3400         .mpu_irqs       = omap44xx_mmc1_irqs,
3401         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
3402         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3403         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3404         .main_clk       = "mmc1_fck",
3405         .prcm           = {
3406                 .omap4 = {
3407                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3408                 },
3409         },
3410         .slaves         = omap44xx_mmc1_slaves,
3411         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3412         .masters        = omap44xx_mmc1_masters,
3413         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3414         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3415 };
3416
3417 /* mmc2 */
3418 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3419         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3420 };
3421
3422 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3423         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3424         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3425 };
3426
3427 /* mmc2 master ports */
3428 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3429         &omap44xx_mmc2__l3_main_1,
3430 };
3431
3432 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3433         {
3434                 .pa_start       = 0x480b4000,
3435                 .pa_end         = 0x480b43ff,
3436                 .flags          = ADDR_TYPE_RT
3437         },
3438 };
3439
3440 /* l4_per -> mmc2 */
3441 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3442         .master         = &omap44xx_l4_per_hwmod,
3443         .slave          = &omap44xx_mmc2_hwmod,
3444         .clk            = "l4_div_ck",
3445         .addr           = omap44xx_mmc2_addrs,
3446         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
3447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3448 };
3449
3450 /* mmc2 slave ports */
3451 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3452         &omap44xx_l4_per__mmc2,
3453 };
3454
3455 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3456         .name           = "mmc2",
3457         .class          = &omap44xx_mmc_hwmod_class,
3458         .mpu_irqs       = omap44xx_mmc2_irqs,
3459         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
3460         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3461         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3462         .main_clk       = "mmc2_fck",
3463         .prcm           = {
3464                 .omap4 = {
3465                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3466                 },
3467         },
3468         .slaves         = omap44xx_mmc2_slaves,
3469         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3470         .masters        = omap44xx_mmc2_masters,
3471         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3472         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3473 };
3474
3475 /* mmc3 */
3476 static struct omap_hwmod omap44xx_mmc3_hwmod;
3477 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3478         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3479 };
3480
3481 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3482         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3483         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3484 };
3485
3486 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3487         {
3488                 .pa_start       = 0x480ad000,
3489                 .pa_end         = 0x480ad3ff,
3490                 .flags          = ADDR_TYPE_RT
3491         },
3492 };
3493
3494 /* l4_per -> mmc3 */
3495 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3496         .master         = &omap44xx_l4_per_hwmod,
3497         .slave          = &omap44xx_mmc3_hwmod,
3498         .clk            = "l4_div_ck",
3499         .addr           = omap44xx_mmc3_addrs,
3500         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
3501         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3502 };
3503
3504 /* mmc3 slave ports */
3505 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3506         &omap44xx_l4_per__mmc3,
3507 };
3508
3509 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3510         .name           = "mmc3",
3511         .class          = &omap44xx_mmc_hwmod_class,
3512         .mpu_irqs       = omap44xx_mmc3_irqs,
3513         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
3514         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3515         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3516         .main_clk       = "mmc3_fck",
3517         .prcm           = {
3518                 .omap4 = {
3519                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3520                 },
3521         },
3522         .slaves         = omap44xx_mmc3_slaves,
3523         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3524         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3525 };
3526
3527 /* mmc4 */
3528 static struct omap_hwmod omap44xx_mmc4_hwmod;
3529 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3530         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3531 };
3532
3533 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3534         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3535         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3536 };
3537
3538 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3539         {
3540                 .pa_start       = 0x480d1000,
3541                 .pa_end         = 0x480d13ff,
3542                 .flags          = ADDR_TYPE_RT
3543         },
3544 };
3545
3546 /* l4_per -> mmc4 */
3547 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3548         .master         = &omap44xx_l4_per_hwmod,
3549         .slave          = &omap44xx_mmc4_hwmod,
3550         .clk            = "l4_div_ck",
3551         .addr           = omap44xx_mmc4_addrs,
3552         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
3553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3554 };
3555
3556 /* mmc4 slave ports */
3557 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3558         &omap44xx_l4_per__mmc4,
3559 };
3560
3561 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3562         .name           = "mmc4",
3563         .class          = &omap44xx_mmc_hwmod_class,
3564         .mpu_irqs       = omap44xx_mmc4_irqs,
3565         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
3566         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3567         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3568         .main_clk       = "mmc4_fck",
3569         .prcm           = {
3570                 .omap4 = {
3571                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3572                 },
3573         },
3574         .slaves         = omap44xx_mmc4_slaves,
3575         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3577 };
3578
3579 /* mmc5 */
3580 static struct omap_hwmod omap44xx_mmc5_hwmod;
3581 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3582         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3583 };
3584
3585 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3586         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3587         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3588 };
3589
3590 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3591         {
3592                 .pa_start       = 0x480d5000,
3593                 .pa_end         = 0x480d53ff,
3594                 .flags          = ADDR_TYPE_RT
3595         },
3596 };
3597
3598 /* l4_per -> mmc5 */
3599 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3600         .master         = &omap44xx_l4_per_hwmod,
3601         .slave          = &omap44xx_mmc5_hwmod,
3602         .clk            = "l4_div_ck",
3603         .addr           = omap44xx_mmc5_addrs,
3604         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
3605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3606 };
3607
3608 /* mmc5 slave ports */
3609 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3610         &omap44xx_l4_per__mmc5,
3611 };
3612
3613 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3614         .name           = "mmc5",
3615         .class          = &omap44xx_mmc_hwmod_class,
3616         .mpu_irqs       = omap44xx_mmc5_irqs,
3617         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
3618         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3619         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3620         .main_clk       = "mmc5_fck",
3621         .prcm           = {
3622                 .omap4 = {
3623                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3624                 },
3625         },
3626         .slaves         = omap44xx_mmc5_slaves,
3627         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3628         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3629 };
3630
3631 /*
3632  * 'mpu' class
3633  * mpu sub-system
3634  */
3635
3636 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3637         .name   = "mpu",
3638 };
3639
3640 /* mpu */
3641 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3642         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3643         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3644         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3645 };
3646
3647 /* mpu master ports */
3648 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3649         &omap44xx_mpu__l3_main_1,
3650         &omap44xx_mpu__l4_abe,
3651         &omap44xx_mpu__dmm,
3652 };
3653
3654 static struct omap_hwmod omap44xx_mpu_hwmod = {
3655         .name           = "mpu",
3656         .class          = &omap44xx_mpu_hwmod_class,
3657         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3658         .mpu_irqs       = omap44xx_mpu_irqs,
3659         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
3660         .main_clk       = "dpll_mpu_m2_ck",
3661         .prcm = {
3662                 .omap4 = {
3663                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3664                 },
3665         },
3666         .masters        = omap44xx_mpu_masters,
3667         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3668         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3669 };
3670
3671 /*
3672  * 'smartreflex' class
3673  * smartreflex module (monitor silicon performance and outputs a measure of
3674  * performance error)
3675  */
3676
3677 /* The IP is not compliant to type1 / type2 scheme */
3678 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3679         .sidle_shift    = 24,
3680         .enwkup_shift   = 26,
3681 };
3682
3683 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3684         .sysc_offs      = 0x0038,
3685         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3686         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3687                            SIDLE_SMART_WKUP),
3688         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3689 };
3690
3691 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3692         .name   = "smartreflex",
3693         .sysc   = &omap44xx_smartreflex_sysc,
3694         .rev    = 2,
3695 };
3696
3697 /* smartreflex_core */
3698 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3699 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3700         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3701 };
3702
3703 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3704         {
3705                 .pa_start       = 0x4a0dd000,
3706                 .pa_end         = 0x4a0dd03f,
3707                 .flags          = ADDR_TYPE_RT
3708         },
3709 };
3710
3711 /* l4_cfg -> smartreflex_core */
3712 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3713         .master         = &omap44xx_l4_cfg_hwmod,
3714         .slave          = &omap44xx_smartreflex_core_hwmod,
3715         .clk            = "l4_div_ck",
3716         .addr           = omap44xx_smartreflex_core_addrs,
3717         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3718         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3719 };
3720
3721 /* smartreflex_core slave ports */
3722 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3723         &omap44xx_l4_cfg__smartreflex_core,
3724 };
3725
3726 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3727         .name           = "smartreflex_core",
3728         .class          = &omap44xx_smartreflex_hwmod_class,
3729         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3730         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3731         .main_clk       = "smartreflex_core_fck",
3732         .vdd_name       = "core",
3733         .prcm = {
3734                 .omap4 = {
3735                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3736                 },
3737         },
3738         .slaves         = omap44xx_smartreflex_core_slaves,
3739         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3740         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3741 };
3742
3743 /* smartreflex_iva */
3744 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3745 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3746         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3747 };
3748
3749 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3750         {
3751                 .pa_start       = 0x4a0db000,
3752                 .pa_end         = 0x4a0db03f,
3753                 .flags          = ADDR_TYPE_RT
3754         },
3755 };
3756
3757 /* l4_cfg -> smartreflex_iva */
3758 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3759         .master         = &omap44xx_l4_cfg_hwmod,
3760         .slave          = &omap44xx_smartreflex_iva_hwmod,
3761         .clk            = "l4_div_ck",
3762         .addr           = omap44xx_smartreflex_iva_addrs,
3763         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3765 };
3766
3767 /* smartreflex_iva slave ports */
3768 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3769         &omap44xx_l4_cfg__smartreflex_iva,
3770 };
3771
3772 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3773         .name           = "smartreflex_iva",
3774         .class          = &omap44xx_smartreflex_hwmod_class,
3775         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3776         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3777         .main_clk       = "smartreflex_iva_fck",
3778         .vdd_name       = "iva",
3779         .prcm = {
3780                 .omap4 = {
3781                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3782                 },
3783         },
3784         .slaves         = omap44xx_smartreflex_iva_slaves,
3785         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3786         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3787 };
3788
3789 /* smartreflex_mpu */
3790 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3791 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3792         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3793 };
3794
3795 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3796         {
3797                 .pa_start       = 0x4a0d9000,
3798                 .pa_end         = 0x4a0d903f,
3799                 .flags          = ADDR_TYPE_RT
3800         },
3801 };
3802
3803 /* l4_cfg -> smartreflex_mpu */
3804 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3805         .master         = &omap44xx_l4_cfg_hwmod,
3806         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3807         .clk            = "l4_div_ck",
3808         .addr           = omap44xx_smartreflex_mpu_addrs,
3809         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3811 };
3812
3813 /* smartreflex_mpu slave ports */
3814 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3815         &omap44xx_l4_cfg__smartreflex_mpu,
3816 };
3817
3818 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3819         .name           = "smartreflex_mpu",
3820         .class          = &omap44xx_smartreflex_hwmod_class,
3821         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3822         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3823         .main_clk       = "smartreflex_mpu_fck",
3824         .vdd_name       = "mpu",
3825         .prcm = {
3826                 .omap4 = {
3827                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3828                 },
3829         },
3830         .slaves         = omap44xx_smartreflex_mpu_slaves,
3831         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3832         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3833 };
3834
3835 /*
3836  * 'spinlock' class
3837  * spinlock provides hardware assistance for synchronizing the processes
3838  * running on multiple processors
3839  */
3840
3841 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3842         .rev_offs       = 0x0000,
3843         .sysc_offs      = 0x0010,
3844         .syss_offs      = 0x0014,
3845         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3846                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3847                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3848         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3849                            SIDLE_SMART_WKUP),
3850         .sysc_fields    = &omap_hwmod_sysc_type1,
3851 };
3852
3853 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3854         .name   = "spinlock",
3855         .sysc   = &omap44xx_spinlock_sysc,
3856 };
3857
3858 /* spinlock */
3859 static struct omap_hwmod omap44xx_spinlock_hwmod;
3860 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3861         {
3862                 .pa_start       = 0x4a0f6000,
3863                 .pa_end         = 0x4a0f6fff,
3864                 .flags          = ADDR_TYPE_RT
3865         },
3866 };
3867
3868 /* l4_cfg -> spinlock */
3869 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3870         .master         = &omap44xx_l4_cfg_hwmod,
3871         .slave          = &omap44xx_spinlock_hwmod,
3872         .clk            = "l4_div_ck",
3873         .addr           = omap44xx_spinlock_addrs,
3874         .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
3875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3876 };
3877
3878 /* spinlock slave ports */
3879 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3880         &omap44xx_l4_cfg__spinlock,
3881 };
3882
3883 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3884         .name           = "spinlock",
3885         .class          = &omap44xx_spinlock_hwmod_class,
3886         .prcm = {
3887                 .omap4 = {
3888                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3889                 },
3890         },
3891         .slaves         = omap44xx_spinlock_slaves,
3892         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3893         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3894 };
3895
3896 /*
3897  * 'timer' class
3898  * general purpose timer module with accurate 1ms tick
3899  * This class contains several variants: ['timer_1ms', 'timer']
3900  */
3901
3902 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3903         .rev_offs       = 0x0000,
3904         .sysc_offs      = 0x0010,
3905         .syss_offs      = 0x0014,
3906         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3907                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3908                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3909                            SYSS_HAS_RESET_STATUS),
3910         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3911         .sysc_fields    = &omap_hwmod_sysc_type1,
3912 };
3913
3914 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3915         .name   = "timer",
3916         .sysc   = &omap44xx_timer_1ms_sysc,
3917 };
3918
3919 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3920         .rev_offs       = 0x0000,
3921         .sysc_offs      = 0x0010,
3922         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3923                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3924         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3925                            SIDLE_SMART_WKUP),
3926         .sysc_fields    = &omap_hwmod_sysc_type2,
3927 };
3928
3929 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3930         .name   = "timer",
3931         .sysc   = &omap44xx_timer_sysc,
3932 };
3933
3934 /* timer1 */
3935 static struct omap_hwmod omap44xx_timer1_hwmod;
3936 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3937         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3938 };
3939
3940 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3941         {
3942                 .pa_start       = 0x4a318000,
3943                 .pa_end         = 0x4a31807f,
3944                 .flags          = ADDR_TYPE_RT
3945         },
3946 };
3947
3948 /* l4_wkup -> timer1 */
3949 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3950         .master         = &omap44xx_l4_wkup_hwmod,
3951         .slave          = &omap44xx_timer1_hwmod,
3952         .clk            = "l4_wkup_clk_mux_ck",
3953         .addr           = omap44xx_timer1_addrs,
3954         .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
3955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3957
3958 /* timer1 slave ports */
3959 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3960         &omap44xx_l4_wkup__timer1,
3961 };
3962
3963 static struct omap_hwmod omap44xx_timer1_hwmod = {
3964         .name           = "timer1",
3965         .class          = &omap44xx_timer_1ms_hwmod_class,
3966         .mpu_irqs       = omap44xx_timer1_irqs,
3967         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
3968         .main_clk       = "timer1_fck",
3969         .prcm = {
3970                 .omap4 = {
3971                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
3972                 },
3973         },
3974         .slaves         = omap44xx_timer1_slaves,
3975         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
3976         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3977 };
3978
3979 /* timer2 */
3980 static struct omap_hwmod omap44xx_timer2_hwmod;
3981 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3982         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3983 };
3984
3985 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
3986         {
3987                 .pa_start       = 0x48032000,
3988                 .pa_end         = 0x4803207f,
3989                 .flags          = ADDR_TYPE_RT
3990         },
3991 };
3992
3993 /* l4_per -> timer2 */
3994 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3995         .master         = &omap44xx_l4_per_hwmod,
3996         .slave          = &omap44xx_timer2_hwmod,
3997         .clk            = "l4_div_ck",
3998         .addr           = omap44xx_timer2_addrs,
3999         .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
4000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4001 };
4002
4003 /* timer2 slave ports */
4004 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4005         &omap44xx_l4_per__timer2,
4006 };
4007
4008 static struct omap_hwmod omap44xx_timer2_hwmod = {
4009         .name           = "timer2",
4010         .class          = &omap44xx_timer_1ms_hwmod_class,
4011         .mpu_irqs       = omap44xx_timer2_irqs,
4012         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
4013         .main_clk       = "timer2_fck",
4014         .prcm = {
4015                 .omap4 = {
4016                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4017                 },
4018         },
4019         .slaves         = omap44xx_timer2_slaves,
4020         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4022 };
4023
4024 /* timer3 */
4025 static struct omap_hwmod omap44xx_timer3_hwmod;
4026 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4027         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4028 };
4029
4030 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4031         {
4032                 .pa_start       = 0x48034000,
4033                 .pa_end         = 0x4803407f,
4034                 .flags          = ADDR_TYPE_RT
4035         },
4036 };
4037
4038 /* l4_per -> timer3 */
4039 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4040         .master         = &omap44xx_l4_per_hwmod,
4041         .slave          = &omap44xx_timer3_hwmod,
4042         .clk            = "l4_div_ck",
4043         .addr           = omap44xx_timer3_addrs,
4044         .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
4045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4046 };
4047
4048 /* timer3 slave ports */
4049 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4050         &omap44xx_l4_per__timer3,
4051 };
4052
4053 static struct omap_hwmod omap44xx_timer3_hwmod = {
4054         .name           = "timer3",
4055         .class          = &omap44xx_timer_hwmod_class,
4056         .mpu_irqs       = omap44xx_timer3_irqs,
4057         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
4058         .main_clk       = "timer3_fck",
4059         .prcm = {
4060                 .omap4 = {
4061                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4062                 },
4063         },
4064         .slaves         = omap44xx_timer3_slaves,
4065         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4066         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4067 };
4068
4069 /* timer4 */
4070 static struct omap_hwmod omap44xx_timer4_hwmod;
4071 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4072         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4073 };
4074
4075 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4076         {
4077                 .pa_start       = 0x48036000,
4078                 .pa_end         = 0x4803607f,
4079                 .flags          = ADDR_TYPE_RT
4080         },
4081 };
4082
4083 /* l4_per -> timer4 */
4084 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4085         .master         = &omap44xx_l4_per_hwmod,
4086         .slave          = &omap44xx_timer4_hwmod,
4087         .clk            = "l4_div_ck",
4088         .addr           = omap44xx_timer4_addrs,
4089         .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
4090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4091 };
4092
4093 /* timer4 slave ports */
4094 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4095         &omap44xx_l4_per__timer4,
4096 };
4097
4098 static struct omap_hwmod omap44xx_timer4_hwmod = {
4099         .name           = "timer4",
4100         .class          = &omap44xx_timer_hwmod_class,
4101         .mpu_irqs       = omap44xx_timer4_irqs,
4102         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
4103         .main_clk       = "timer4_fck",
4104         .prcm = {
4105                 .omap4 = {
4106                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4107                 },
4108         },
4109         .slaves         = omap44xx_timer4_slaves,
4110         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4111         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4112 };
4113
4114 /* timer5 */
4115 static struct omap_hwmod omap44xx_timer5_hwmod;
4116 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4117         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4118 };
4119
4120 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4121         {
4122                 .pa_start       = 0x40138000,
4123                 .pa_end         = 0x4013807f,
4124                 .flags          = ADDR_TYPE_RT
4125         },
4126 };
4127
4128 /* l4_abe -> timer5 */
4129 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4130         .master         = &omap44xx_l4_abe_hwmod,
4131         .slave          = &omap44xx_timer5_hwmod,
4132         .clk            = "ocp_abe_iclk",
4133         .addr           = omap44xx_timer5_addrs,
4134         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
4135         .user           = OCP_USER_MPU,
4136 };
4137
4138 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4139         {
4140                 .pa_start       = 0x49038000,
4141                 .pa_end         = 0x4903807f,
4142                 .flags          = ADDR_TYPE_RT
4143         },
4144 };
4145
4146 /* l4_abe -> timer5 (dma) */
4147 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4148         .master         = &omap44xx_l4_abe_hwmod,
4149         .slave          = &omap44xx_timer5_hwmod,
4150         .clk            = "ocp_abe_iclk",
4151         .addr           = omap44xx_timer5_dma_addrs,
4152         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4153         .user           = OCP_USER_SDMA,
4154 };
4155
4156 /* timer5 slave ports */
4157 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4158         &omap44xx_l4_abe__timer5,
4159         &omap44xx_l4_abe__timer5_dma,
4160 };
4161
4162 static struct omap_hwmod omap44xx_timer5_hwmod = {
4163         .name           = "timer5",
4164         .class          = &omap44xx_timer_hwmod_class,
4165         .mpu_irqs       = omap44xx_timer5_irqs,
4166         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
4167         .main_clk       = "timer5_fck",
4168         .prcm = {
4169                 .omap4 = {
4170                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4171                 },
4172         },
4173         .slaves         = omap44xx_timer5_slaves,
4174         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4175         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4176 };
4177
4178 /* timer6 */
4179 static struct omap_hwmod omap44xx_timer6_hwmod;
4180 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4181         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4182 };
4183
4184 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4185         {
4186                 .pa_start       = 0x4013a000,
4187                 .pa_end         = 0x4013a07f,
4188                 .flags          = ADDR_TYPE_RT
4189         },
4190 };
4191
4192 /* l4_abe -> timer6 */
4193 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4194         .master         = &omap44xx_l4_abe_hwmod,
4195         .slave          = &omap44xx_timer6_hwmod,
4196         .clk            = "ocp_abe_iclk",
4197         .addr           = omap44xx_timer6_addrs,
4198         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
4199         .user           = OCP_USER_MPU,
4200 };
4201
4202 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4203         {
4204                 .pa_start       = 0x4903a000,
4205                 .pa_end         = 0x4903a07f,
4206                 .flags          = ADDR_TYPE_RT
4207         },
4208 };
4209
4210 /* l4_abe -> timer6 (dma) */
4211 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4212         .master         = &omap44xx_l4_abe_hwmod,
4213         .slave          = &omap44xx_timer6_hwmod,
4214         .clk            = "ocp_abe_iclk",
4215         .addr           = omap44xx_timer6_dma_addrs,
4216         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4217         .user           = OCP_USER_SDMA,
4218 };
4219
4220 /* timer6 slave ports */
4221 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4222         &omap44xx_l4_abe__timer6,
4223         &omap44xx_l4_abe__timer6_dma,
4224 };
4225
4226 static struct omap_hwmod omap44xx_timer6_hwmod = {
4227         .name           = "timer6",
4228         .class          = &omap44xx_timer_hwmod_class,
4229         .mpu_irqs       = omap44xx_timer6_irqs,
4230         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
4231         .main_clk       = "timer6_fck",
4232         .prcm = {
4233                 .omap4 = {
4234                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4235                 },
4236         },
4237         .slaves         = omap44xx_timer6_slaves,
4238         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4239         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4240 };
4241
4242 /* timer7 */
4243 static struct omap_hwmod omap44xx_timer7_hwmod;
4244 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4245         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4246 };
4247
4248 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4249         {
4250                 .pa_start       = 0x4013c000,
4251                 .pa_end         = 0x4013c07f,
4252                 .flags          = ADDR_TYPE_RT
4253         },
4254 };
4255
4256 /* l4_abe -> timer7 */
4257 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4258         .master         = &omap44xx_l4_abe_hwmod,
4259         .slave          = &omap44xx_timer7_hwmod,
4260         .clk            = "ocp_abe_iclk",
4261         .addr           = omap44xx_timer7_addrs,
4262         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
4263         .user           = OCP_USER_MPU,
4264 };
4265
4266 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4267         {
4268                 .pa_start       = 0x4903c000,
4269                 .pa_end         = 0x4903c07f,
4270                 .flags          = ADDR_TYPE_RT
4271         },
4272 };
4273
4274 /* l4_abe -> timer7 (dma) */
4275 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4276         .master         = &omap44xx_l4_abe_hwmod,
4277         .slave          = &omap44xx_timer7_hwmod,
4278         .clk            = "ocp_abe_iclk",
4279         .addr           = omap44xx_timer7_dma_addrs,
4280         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4281         .user           = OCP_USER_SDMA,
4282 };
4283
4284 /* timer7 slave ports */
4285 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4286         &omap44xx_l4_abe__timer7,
4287         &omap44xx_l4_abe__timer7_dma,
4288 };
4289
4290 static struct omap_hwmod omap44xx_timer7_hwmod = {
4291         .name           = "timer7",
4292         .class          = &omap44xx_timer_hwmod_class,
4293         .mpu_irqs       = omap44xx_timer7_irqs,
4294         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
4295         .main_clk       = "timer7_fck",
4296         .prcm = {
4297                 .omap4 = {
4298                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4299                 },
4300         },
4301         .slaves         = omap44xx_timer7_slaves,
4302         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4303         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4304 };
4305
4306 /* timer8 */
4307 static struct omap_hwmod omap44xx_timer8_hwmod;
4308 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4309         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4310 };
4311
4312 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4313         {
4314                 .pa_start       = 0x4013e000,
4315                 .pa_end         = 0x4013e07f,
4316                 .flags          = ADDR_TYPE_RT
4317         },
4318 };
4319
4320 /* l4_abe -> timer8 */
4321 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4322         .master         = &omap44xx_l4_abe_hwmod,
4323         .slave          = &omap44xx_timer8_hwmod,
4324         .clk            = "ocp_abe_iclk",
4325         .addr           = omap44xx_timer8_addrs,
4326         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
4327         .user           = OCP_USER_MPU,
4328 };
4329
4330 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4331         {
4332                 .pa_start       = 0x4903e000,
4333                 .pa_end         = 0x4903e07f,
4334                 .flags          = ADDR_TYPE_RT
4335         },
4336 };
4337
4338 /* l4_abe -> timer8 (dma) */
4339 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4340         .master         = &omap44xx_l4_abe_hwmod,
4341         .slave          = &omap44xx_timer8_hwmod,
4342         .clk            = "ocp_abe_iclk",
4343         .addr           = omap44xx_timer8_dma_addrs,
4344         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4345         .user           = OCP_USER_SDMA,
4346 };
4347
4348 /* timer8 slave ports */
4349 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4350         &omap44xx_l4_abe__timer8,
4351         &omap44xx_l4_abe__timer8_dma,
4352 };
4353
4354 static struct omap_hwmod omap44xx_timer8_hwmod = {
4355         .name           = "timer8",
4356         .class          = &omap44xx_timer_hwmod_class,
4357         .mpu_irqs       = omap44xx_timer8_irqs,
4358         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
4359         .main_clk       = "timer8_fck",
4360         .prcm = {
4361                 .omap4 = {
4362                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4363                 },
4364         },
4365         .slaves         = omap44xx_timer8_slaves,
4366         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4367         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4368 };
4369
4370 /* timer9 */
4371 static struct omap_hwmod omap44xx_timer9_hwmod;
4372 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4373         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4374 };
4375
4376 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4377         {
4378                 .pa_start       = 0x4803e000,
4379                 .pa_end         = 0x4803e07f,
4380                 .flags          = ADDR_TYPE_RT
4381         },
4382 };
4383
4384 /* l4_per -> timer9 */
4385 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4386         .master         = &omap44xx_l4_per_hwmod,
4387         .slave          = &omap44xx_timer9_hwmod,
4388         .clk            = "l4_div_ck",
4389         .addr           = omap44xx_timer9_addrs,
4390         .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
4391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4392 };
4393
4394 /* timer9 slave ports */
4395 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4396         &omap44xx_l4_per__timer9,
4397 };
4398
4399 static struct omap_hwmod omap44xx_timer9_hwmod = {
4400         .name           = "timer9",
4401         .class          = &omap44xx_timer_hwmod_class,
4402         .mpu_irqs       = omap44xx_timer9_irqs,
4403         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
4404         .main_clk       = "timer9_fck",
4405         .prcm = {
4406                 .omap4 = {
4407                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4408                 },
4409         },
4410         .slaves         = omap44xx_timer9_slaves,
4411         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4413 };
4414
4415 /* timer10 */
4416 static struct omap_hwmod omap44xx_timer10_hwmod;
4417 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4418         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4419 };
4420
4421 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4422         {
4423                 .pa_start       = 0x48086000,
4424                 .pa_end         = 0x4808607f,
4425                 .flags          = ADDR_TYPE_RT
4426         },
4427 };
4428
4429 /* l4_per -> timer10 */
4430 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4431         .master         = &omap44xx_l4_per_hwmod,
4432         .slave          = &omap44xx_timer10_hwmod,
4433         .clk            = "l4_div_ck",
4434         .addr           = omap44xx_timer10_addrs,
4435         .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
4436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4437 };
4438
4439 /* timer10 slave ports */
4440 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4441         &omap44xx_l4_per__timer10,
4442 };
4443
4444 static struct omap_hwmod omap44xx_timer10_hwmod = {
4445         .name           = "timer10",
4446         .class          = &omap44xx_timer_1ms_hwmod_class,
4447         .mpu_irqs       = omap44xx_timer10_irqs,
4448         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
4449         .main_clk       = "timer10_fck",
4450         .prcm = {
4451                 .omap4 = {
4452                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4453                 },
4454         },
4455         .slaves         = omap44xx_timer10_slaves,
4456         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4457         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4458 };
4459
4460 /* timer11 */
4461 static struct omap_hwmod omap44xx_timer11_hwmod;
4462 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4463         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4464 };
4465
4466 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4467         {
4468                 .pa_start       = 0x48088000,
4469                 .pa_end         = 0x4808807f,
4470                 .flags          = ADDR_TYPE_RT
4471         },
4472 };
4473
4474 /* l4_per -> timer11 */
4475 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4476         .master         = &omap44xx_l4_per_hwmod,
4477         .slave          = &omap44xx_timer11_hwmod,
4478         .clk            = "l4_div_ck",
4479         .addr           = omap44xx_timer11_addrs,
4480         .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
4481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4482 };
4483
4484 /* timer11 slave ports */
4485 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4486         &omap44xx_l4_per__timer11,
4487 };
4488
4489 static struct omap_hwmod omap44xx_timer11_hwmod = {
4490         .name           = "timer11",
4491         .class          = &omap44xx_timer_hwmod_class,
4492         .mpu_irqs       = omap44xx_timer11_irqs,
4493         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
4494         .main_clk       = "timer11_fck",
4495         .prcm = {
4496                 .omap4 = {
4497                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4498                 },
4499         },
4500         .slaves         = omap44xx_timer11_slaves,
4501         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4502         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4503 };
4504
4505 /*
4506  * 'uart' class
4507  * universal asynchronous receiver/transmitter (uart)
4508  */
4509
4510 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4511         .rev_offs       = 0x0050,
4512         .sysc_offs      = 0x0054,
4513         .syss_offs      = 0x0058,
4514         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4515                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4516                            SYSS_HAS_RESET_STATUS),
4517         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4518                            SIDLE_SMART_WKUP),
4519         .sysc_fields    = &omap_hwmod_sysc_type1,
4520 };
4521
4522 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4523         .name   = "uart",
4524         .sysc   = &omap44xx_uart_sysc,
4525 };
4526
4527 /* uart1 */
4528 static struct omap_hwmod omap44xx_uart1_hwmod;
4529 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4530         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4531 };
4532
4533 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4534         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4535         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4536 };
4537
4538 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4539         {
4540                 .pa_start       = 0x4806a000,
4541                 .pa_end         = 0x4806a0ff,
4542                 .flags          = ADDR_TYPE_RT
4543         },
4544 };
4545
4546 /* l4_per -> uart1 */
4547 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4548         .master         = &omap44xx_l4_per_hwmod,
4549         .slave          = &omap44xx_uart1_hwmod,
4550         .clk            = "l4_div_ck",
4551         .addr           = omap44xx_uart1_addrs,
4552         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
4553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4554 };
4555
4556 /* uart1 slave ports */
4557 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4558         &omap44xx_l4_per__uart1,
4559 };
4560
4561 static struct omap_hwmod omap44xx_uart1_hwmod = {
4562         .name           = "uart1",
4563         .class          = &omap44xx_uart_hwmod_class,
4564         .mpu_irqs       = omap44xx_uart1_irqs,
4565         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
4566         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4567         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4568         .main_clk       = "uart1_fck",
4569         .prcm = {
4570                 .omap4 = {
4571                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4572                 },
4573         },
4574         .slaves         = omap44xx_uart1_slaves,
4575         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4577 };
4578
4579 /* uart2 */
4580 static struct omap_hwmod omap44xx_uart2_hwmod;
4581 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4582         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4583 };
4584
4585 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4586         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4587         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4588 };
4589
4590 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4591         {
4592                 .pa_start       = 0x4806c000,
4593                 .pa_end         = 0x4806c0ff,
4594                 .flags          = ADDR_TYPE_RT
4595         },
4596 };
4597
4598 /* l4_per -> uart2 */
4599 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4600         .master         = &omap44xx_l4_per_hwmod,
4601         .slave          = &omap44xx_uart2_hwmod,
4602         .clk            = "l4_div_ck",
4603         .addr           = omap44xx_uart2_addrs,
4604         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
4605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4606 };
4607
4608 /* uart2 slave ports */
4609 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4610         &omap44xx_l4_per__uart2,
4611 };
4612
4613 static struct omap_hwmod omap44xx_uart2_hwmod = {
4614         .name           = "uart2",
4615         .class          = &omap44xx_uart_hwmod_class,
4616         .mpu_irqs       = omap44xx_uart2_irqs,
4617         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
4618         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4619         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4620         .main_clk       = "uart2_fck",
4621         .prcm = {
4622                 .omap4 = {
4623                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4624                 },
4625         },
4626         .slaves         = omap44xx_uart2_slaves,
4627         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4628         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4629 };
4630
4631 /* uart3 */
4632 static struct omap_hwmod omap44xx_uart3_hwmod;
4633 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4634         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4635 };
4636
4637 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4638         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4639         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4640 };
4641
4642 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4643         {
4644                 .pa_start       = 0x48020000,
4645                 .pa_end         = 0x480200ff,
4646                 .flags          = ADDR_TYPE_RT
4647         },
4648 };
4649
4650 /* l4_per -> uart3 */
4651 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4652         .master         = &omap44xx_l4_per_hwmod,
4653         .slave          = &omap44xx_uart3_hwmod,
4654         .clk            = "l4_div_ck",
4655         .addr           = omap44xx_uart3_addrs,
4656         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
4657         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4658 };
4659
4660 /* uart3 slave ports */
4661 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4662         &omap44xx_l4_per__uart3,
4663 };
4664
4665 static struct omap_hwmod omap44xx_uart3_hwmod = {
4666         .name           = "uart3",
4667         .class          = &omap44xx_uart_hwmod_class,
4668         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4669         .mpu_irqs       = omap44xx_uart3_irqs,
4670         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
4671         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4672         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4673         .main_clk       = "uart3_fck",
4674         .prcm = {
4675                 .omap4 = {
4676                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4677                 },
4678         },
4679         .slaves         = omap44xx_uart3_slaves,
4680         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4681         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4682 };
4683
4684 /* uart4 */
4685 static struct omap_hwmod omap44xx_uart4_hwmod;
4686 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4687         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4688 };
4689
4690 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4691         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4692         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4693 };
4694
4695 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4696         {
4697                 .pa_start       = 0x4806e000,
4698                 .pa_end         = 0x4806e0ff,
4699                 .flags          = ADDR_TYPE_RT
4700         },
4701 };
4702
4703 /* l4_per -> uart4 */
4704 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4705         .master         = &omap44xx_l4_per_hwmod,
4706         .slave          = &omap44xx_uart4_hwmod,
4707         .clk            = "l4_div_ck",
4708         .addr           = omap44xx_uart4_addrs,
4709         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
4710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4711 };
4712
4713 /* uart4 slave ports */
4714 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4715         &omap44xx_l4_per__uart4,
4716 };
4717
4718 static struct omap_hwmod omap44xx_uart4_hwmod = {
4719         .name           = "uart4",
4720         .class          = &omap44xx_uart_hwmod_class,
4721         .mpu_irqs       = omap44xx_uart4_irqs,
4722         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
4723         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4724         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4725         .main_clk       = "uart4_fck",
4726         .prcm = {
4727                 .omap4 = {
4728                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4729                 },
4730         },
4731         .slaves         = omap44xx_uart4_slaves,
4732         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4733         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4734 };
4735
4736 /*
4737  * 'usb_otg_hs' class
4738  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4739  */
4740
4741 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4742         .rev_offs       = 0x0400,
4743         .sysc_offs      = 0x0404,
4744         .syss_offs      = 0x0408,
4745         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4746                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4747                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4748         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4749                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4750                            MSTANDBY_SMART),
4751         .sysc_fields    = &omap_hwmod_sysc_type1,
4752 };
4753
4754 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4755         .name = "usb_otg_hs",
4756         .sysc = &omap44xx_usb_otg_hs_sysc,
4757 };
4758
4759 /* usb_otg_hs */
4760 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4761         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4762         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4763 };
4764
4765 /* usb_otg_hs master ports */
4766 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4767         &omap44xx_usb_otg_hs__l3_main_2,
4768 };
4769
4770 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4771         {
4772                 .pa_start       = 0x4a0ab000,
4773                 .pa_end         = 0x4a0ab003,
4774                 .flags          = ADDR_TYPE_RT
4775         },
4776 };
4777
4778 /* l4_cfg -> usb_otg_hs */
4779 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4780         .master         = &omap44xx_l4_cfg_hwmod,
4781         .slave          = &omap44xx_usb_otg_hs_hwmod,
4782         .clk            = "l4_div_ck",
4783         .addr           = omap44xx_usb_otg_hs_addrs,
4784         .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4786 };
4787
4788 /* usb_otg_hs slave ports */
4789 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4790         &omap44xx_l4_cfg__usb_otg_hs,
4791 };
4792
4793 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4794         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4795 };
4796
4797 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4798         .name           = "usb_otg_hs",
4799         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4800         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4801         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4802         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4803         .main_clk       = "usb_otg_hs_ick",
4804         .prcm = {
4805                 .omap4 = {
4806                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4807                 },
4808         },
4809         .opt_clks       = usb_otg_hs_opt_clks,
4810         .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4811         .slaves         = omap44xx_usb_otg_hs_slaves,
4812         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4813         .masters        = omap44xx_usb_otg_hs_masters,
4814         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4815         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4816 };
4817
4818 /*
4819  * 'wd_timer' class
4820  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4821  * overflow condition
4822  */
4823
4824 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4825         .rev_offs       = 0x0000,
4826         .sysc_offs      = 0x0010,
4827         .syss_offs      = 0x0014,
4828         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4829                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4830         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4831                            SIDLE_SMART_WKUP),
4832         .sysc_fields    = &omap_hwmod_sysc_type1,
4833 };
4834
4835 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4836         .name           = "wd_timer",
4837         .sysc           = &omap44xx_wd_timer_sysc,
4838         .pre_shutdown   = &omap2_wd_timer_disable,
4839 };
4840
4841 /* wd_timer2 */
4842 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4843 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4844         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4845 };
4846
4847 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4848         {
4849                 .pa_start       = 0x4a314000,
4850                 .pa_end         = 0x4a31407f,
4851                 .flags          = ADDR_TYPE_RT
4852         },
4853 };
4854
4855 /* l4_wkup -> wd_timer2 */
4856 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4857         .master         = &omap44xx_l4_wkup_hwmod,
4858         .slave          = &omap44xx_wd_timer2_hwmod,
4859         .clk            = "l4_wkup_clk_mux_ck",
4860         .addr           = omap44xx_wd_timer2_addrs,
4861         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4863 };
4864
4865 /* wd_timer2 slave ports */
4866 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4867         &omap44xx_l4_wkup__wd_timer2,
4868 };
4869
4870 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4871         .name           = "wd_timer2",
4872         .class          = &omap44xx_wd_timer_hwmod_class,
4873         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4874         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4875         .main_clk       = "wd_timer2_fck",
4876         .prcm = {
4877                 .omap4 = {
4878                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4879                 },
4880         },
4881         .slaves         = omap44xx_wd_timer2_slaves,
4882         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4883         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4884 };
4885
4886 /* wd_timer3 */
4887 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4888 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4889         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4890 };
4891
4892 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4893         {
4894                 .pa_start       = 0x40130000,
4895                 .pa_end         = 0x4013007f,
4896                 .flags          = ADDR_TYPE_RT
4897         },
4898 };
4899
4900 /* l4_abe -> wd_timer3 */
4901 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4902         .master         = &omap44xx_l4_abe_hwmod,
4903         .slave          = &omap44xx_wd_timer3_hwmod,
4904         .clk            = "ocp_abe_iclk",
4905         .addr           = omap44xx_wd_timer3_addrs,
4906         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4907         .user           = OCP_USER_MPU,
4908 };
4909
4910 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4911         {
4912                 .pa_start       = 0x49030000,
4913                 .pa_end         = 0x4903007f,
4914                 .flags          = ADDR_TYPE_RT
4915         },
4916 };
4917
4918 /* l4_abe -> wd_timer3 (dma) */
4919 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4920         .master         = &omap44xx_l4_abe_hwmod,
4921         .slave          = &omap44xx_wd_timer3_hwmod,
4922         .clk            = "ocp_abe_iclk",
4923         .addr           = omap44xx_wd_timer3_dma_addrs,
4924         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
4925         .user           = OCP_USER_SDMA,
4926 };
4927
4928 /* wd_timer3 slave ports */
4929 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
4930         &omap44xx_l4_abe__wd_timer3,
4931         &omap44xx_l4_abe__wd_timer3_dma,
4932 };
4933
4934 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
4935         .name           = "wd_timer3",
4936         .class          = &omap44xx_wd_timer_hwmod_class,
4937         .mpu_irqs       = omap44xx_wd_timer3_irqs,
4938         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
4939         .main_clk       = "wd_timer3_fck",
4940         .prcm = {
4941                 .omap4 = {
4942                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
4943                 },
4944         },
4945         .slaves         = omap44xx_wd_timer3_slaves,
4946         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
4947         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4948 };
4949
4950 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
4951
4952         /* dmm class */
4953         &omap44xx_dmm_hwmod,
4954
4955         /* emif_fw class */
4956         &omap44xx_emif_fw_hwmod,
4957
4958         /* l3 class */
4959         &omap44xx_l3_instr_hwmod,
4960         &omap44xx_l3_main_1_hwmod,
4961         &omap44xx_l3_main_2_hwmod,
4962         &omap44xx_l3_main_3_hwmod,
4963
4964         /* l4 class */
4965         &omap44xx_l4_abe_hwmod,
4966         &omap44xx_l4_cfg_hwmod,
4967         &omap44xx_l4_per_hwmod,
4968         &omap44xx_l4_wkup_hwmod,
4969
4970         /* mpu_bus class */
4971         &omap44xx_mpu_private_hwmod,
4972
4973         /* aess class */
4974 /*      &omap44xx_aess_hwmod, */
4975
4976         /* bandgap class */
4977         &omap44xx_bandgap_hwmod,
4978
4979         /* counter class */
4980 /*      &omap44xx_counter_32k_hwmod, */
4981
4982         /* dma class */
4983         &omap44xx_dma_system_hwmod,
4984
4985         /* dmic class */
4986         &omap44xx_dmic_hwmod,
4987
4988         /* dsp class */
4989         &omap44xx_dsp_hwmod,
4990         &omap44xx_dsp_c0_hwmod,
4991
4992         /* dss class */
4993         &omap44xx_dss_hwmod,
4994         &omap44xx_dss_dispc_hwmod,
4995         &omap44xx_dss_dsi1_hwmod,
4996         &omap44xx_dss_dsi2_hwmod,
4997         &omap44xx_dss_hdmi_hwmod,
4998         &omap44xx_dss_rfbi_hwmod,
4999         &omap44xx_dss_venc_hwmod,
5000
5001         /* gpio class */
5002         &omap44xx_gpio1_hwmod,
5003         &omap44xx_gpio2_hwmod,
5004         &omap44xx_gpio3_hwmod,
5005         &omap44xx_gpio4_hwmod,
5006         &omap44xx_gpio5_hwmod,
5007         &omap44xx_gpio6_hwmod,
5008
5009         /* hsi class */
5010 /*      &omap44xx_hsi_hwmod, */
5011
5012         /* i2c class */
5013         &omap44xx_i2c1_hwmod,
5014         &omap44xx_i2c2_hwmod,
5015         &omap44xx_i2c3_hwmod,
5016         &omap44xx_i2c4_hwmod,
5017
5018         /* ipu class */
5019         &omap44xx_ipu_hwmod,
5020         &omap44xx_ipu_c0_hwmod,
5021         &omap44xx_ipu_c1_hwmod,
5022
5023         /* iss class */
5024 /*      &omap44xx_iss_hwmod, */
5025
5026         /* iva class */
5027         &omap44xx_iva_hwmod,
5028         &omap44xx_iva_seq0_hwmod,
5029         &omap44xx_iva_seq1_hwmod,
5030
5031         /* kbd class */
5032 /*      &omap44xx_kbd_hwmod, */
5033
5034         /* mailbox class */
5035         &omap44xx_mailbox_hwmod,
5036
5037         /* mcbsp class */
5038         &omap44xx_mcbsp1_hwmod,
5039         &omap44xx_mcbsp2_hwmod,
5040         &omap44xx_mcbsp3_hwmod,
5041         &omap44xx_mcbsp4_hwmod,
5042
5043         /* mcpdm class */
5044 /*      &omap44xx_mcpdm_hwmod, */
5045
5046         /* mcspi class */
5047         &omap44xx_mcspi1_hwmod,
5048         &omap44xx_mcspi2_hwmod,
5049         &omap44xx_mcspi3_hwmod,
5050         &omap44xx_mcspi4_hwmod,
5051
5052         /* mmc class */
5053 /*      &omap44xx_mmc1_hwmod, */
5054 /*      &omap44xx_mmc2_hwmod, */
5055 /*      &omap44xx_mmc3_hwmod, */
5056 /*      &omap44xx_mmc4_hwmod, */
5057 /*      &omap44xx_mmc5_hwmod, */
5058
5059         /* mpu class */
5060         &omap44xx_mpu_hwmod,
5061
5062         /* smartreflex class */
5063         &omap44xx_smartreflex_core_hwmod,
5064         &omap44xx_smartreflex_iva_hwmod,
5065         &omap44xx_smartreflex_mpu_hwmod,
5066
5067         /* spinlock class */
5068         &omap44xx_spinlock_hwmod,
5069
5070         /* timer class */
5071         &omap44xx_timer1_hwmod,
5072         &omap44xx_timer2_hwmod,
5073         &omap44xx_timer3_hwmod,
5074         &omap44xx_timer4_hwmod,
5075         &omap44xx_timer5_hwmod,
5076         &omap44xx_timer6_hwmod,
5077         &omap44xx_timer7_hwmod,
5078         &omap44xx_timer8_hwmod,
5079         &omap44xx_timer9_hwmod,
5080         &omap44xx_timer10_hwmod,
5081         &omap44xx_timer11_hwmod,
5082
5083         /* uart class */
5084         &omap44xx_uart1_hwmod,
5085         &omap44xx_uart2_hwmod,
5086         &omap44xx_uart3_hwmod,
5087         &omap44xx_uart4_hwmod,
5088
5089         /* usb_otg_hs class */
5090         &omap44xx_usb_otg_hs_hwmod,
5091
5092         /* wd_timer class */
5093         &omap44xx_wd_timer2_hwmod,
5094         &omap44xx_wd_timer3_hwmod,
5095
5096         NULL,
5097 };
5098
5099 int __init omap44xx_hwmod_init(void)
5100 {
5101         return omap_hwmod_init(omap44xx_hwmods);
5102 }
5103