arch/arm/mach-omap2/mmc-twl4030.c

   1 /*
   2  * linux/arch/arm/mach-omap2/mmc-twl4030.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/gpio.h>
  19 #include <linux/i2c/twl4030.h>
  20 #include <linux/regulator/machine.h>
  21
  22 #include <mach/hardware.h>
  23 #include <mach/control.h>
  24 #include <mach/mmc.h>
  25 #include <mach/board.h>
  26
  27 #include "mmc-twl4030.h"
  28
  29 #if defined(CONFIG_TWL4030_CORE) && \
  30         (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
  31
  32 #define LDO_CLR                 0x00
  33 #define VSEL_S2_CLR             0x40
  34
  35 #define VMMC1_DEV_GRP           0x27
  36 #define VMMC1_CLR               0x00
  37 #define VMMC1_315V              0x03
  38 #define VMMC1_300V              0x02
  39 #define VMMC1_285V              0x01
  40 #define VMMC1_185V              0x00
  41 #define VMMC1_DEDICATED         0x2A
  42
  43 #define VMMC2_DEV_GRP           0x2B
  44 #define VMMC2_CLR               0x40
  45 #define VMMC2_315V              0x0c
  46 #define VMMC2_300V              0x0b
  47 #define VMMC2_285V              0x0a
  48 #define VMMC2_280V              0x09
  49 #define VMMC2_260V              0x08
  50 #define VMMC2_185V              0x06
  51 #define VMMC2_DEDICATED         0x2E
  52
  53 #define VMMC_DEV_GRP_P1         0x20
  54
  55 static u16 control_pbias_offset;
  56 static u16 control_devconf1_offset;
  57
  58 #define HSMMC_NAME_LEN  9
  59
  60 static struct twl_mmc_controller {
  61         struct omap_mmc_platform_data   *mmc;
  62         u8              twl_vmmc_dev_grp;
  63         u8              twl_mmc_dedicated;
  64         char            name[HSMMC_NAME_LEN + 1];
  65 } hsmmc[OMAP34XX_NR_MMC] = {
  66         {
  67                 .twl_vmmc_dev_grp               = VMMC1_DEV_GRP,
  68                 .twl_mmc_dedicated              = VMMC1_DEDICATED,
  69         },
  70         {
  71                 .twl_vmmc_dev_grp               = VMMC2_DEV_GRP,
  72                 .twl_mmc_dedicated              = VMMC2_DEDICATED,
  73         },
  74 };
  75
  76 static int twl_mmc_card_detect(int irq)
  77 {
  78         unsigned i;
  79
  80         for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
  81                 struct omap_mmc_platform_data *mmc;
  82
  83                 mmc = hsmmc[i].mmc;
  84                 if (!mmc)
  85                         continue;
  86                 if (irq != mmc->slots[0].card_detect_irq)
  87                         continue;
  88
  89                 /* NOTE: assumes card detect signal is active-low */
  90                 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  91         }
  92         return -ENOSYS;
  93 }
  94
  95 static int twl_mmc_get_ro(struct device *dev, int slot)
  96 {
  97         struct omap_mmc_platform_data *mmc = dev->platform_data;
  98
  99         /* NOTE: assumes write protect signal is active-high */
 100         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 101 }
 102
 103 /*
 104  * MMC Slot Initialization.
 105  */
 106 static int twl_mmc_late_init(struct device *dev)
 107 {
 108         struct omap_mmc_platform_data *mmc = dev->platform_data;
 109         int ret = 0;
 110         int i;
 111
 112         ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
 113         if (ret)
 114                 goto done;
 115         ret = gpio_direction_input(mmc->slots[0].switch_pin);
 116         if (ret)
 117                 goto err;
 118
 119         for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
 120                 if (hsmmc[i].name == mmc->slots[0].name) {
 121                         hsmmc[i].mmc = mmc;
 122                         break;
 123                 }
 124         }
 125
 126         return 0;
 127
 128 err:
 129         gpio_free(mmc->slots[0].switch_pin);
 130 done:
 131         mmc->slots[0].card_detect_irq = 0;
 132         mmc->slots[0].card_detect = NULL;
 133
 134         dev_err(dev, "err %d configuring card detect\n", ret);
 135         return ret;
 136 }
 137
 138 static void twl_mmc_cleanup(struct device *dev)
 139 {
 140         struct omap_mmc_platform_data *mmc = dev->platform_data;
 141
 142         gpio_free(mmc->slots[0].switch_pin);
 143 }
 144
 145 #ifdef CONFIG_PM
 146
 147 static int twl_mmc_suspend(struct device *dev, int slot)
 148 {
 149         struct omap_mmc_platform_data *mmc = dev->platform_data;
 150
 151         disable_irq(mmc->slots[0].card_detect_irq);
 152         return 0;
 153 }
 154
 155 static int twl_mmc_resume(struct device *dev, int slot)
 156 {
 157         struct omap_mmc_platform_data *mmc = dev->platform_data;
 158
 159         enable_irq(mmc->slots[0].card_detect_irq);
 160         return 0;
 161 }
 162
 163 #else
 164 #define twl_mmc_suspend NULL
 165 #define twl_mmc_resume  NULL
 166 #endif
 167
 168 /*
 169  * Sets the MMC voltage in twl4030
 170  */
 171
 172 #define MMC1_OCR        (MMC_VDD_165_195 \
 173                 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
 174 #define MMC2_OCR        (MMC_VDD_165_195 \
 175                 |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \
 176                 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
 177
 178 static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
 179 {
 180         int ret;
 181         u8 vmmc, dev_grp_val;
 182
 183         if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) {
 184                 /* VMMC1:  max 220 mA.  And for 8-bit mode,
 185                  * VSIM:  max 50 mA
 186                  */
 187                 switch (1 << vdd) {
 188                 case MMC_VDD_165_195:
 189                         vmmc = VMMC1_185V;
 190                         /* and VSIM_180V */
 191                         break;
 192                 case MMC_VDD_28_29:
 193                         vmmc = VMMC1_285V;
 194                         /* and VSIM_280V */
 195                         break;
 196                 case MMC_VDD_29_30:
 197                 case MMC_VDD_30_31:
 198                         vmmc = VMMC1_300V;
 199                         /* and VSIM_300V */
 200                         break;
 201                 case MMC_VDD_31_32:
 202                         vmmc = VMMC1_315V;
 203                         /* error if VSIM needed */
 204                         break;
 205                 default:
 206                         vmmc = 0;
 207                         break;
 208                 }
 209         } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) {
 210                 /* VMMC2:  max 100 mA */
 211                 switch (1 << vdd) {
 212                 case MMC_VDD_165_195:
 213                         vmmc = VMMC2_185V;
 214                         break;
 215                 case MMC_VDD_25_26:
 216                 case MMC_VDD_26_27:
 217                         vmmc = VMMC2_260V;
 218                         break;
 219                 case MMC_VDD_27_28:
 220                         vmmc = VMMC2_280V;
 221                         break;
 222                 case MMC_VDD_28_29:
 223                         vmmc = VMMC2_285V;
 224                         break;
 225                 case MMC_VDD_29_30:
 226                 case MMC_VDD_30_31:
 227                         vmmc = VMMC2_300V;
 228                         break;
 229                 case MMC_VDD_31_32:
 230                         vmmc = VMMC2_315V;
 231                         break;
 232                 default:
 233                         vmmc = 0;
 234                         break;
 235                 }
 236         } else {
 237                 return 0;
 238         }
 239
 240         if (vmmc)
 241                 dev_grp_val = VMMC_DEV_GRP_P1;  /* Power up */
 242         else
 243                 dev_grp_val = LDO_CLR;          /* Power down */
 244
 245         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 246                                         dev_grp_val, c->twl_vmmc_dev_grp);
 247         if (ret)
 248                 return ret;
 249
 250         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 251                                         vmmc, c->twl_mmc_dedicated);
 252
 253         return ret;
 254 }
 255
 256 static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
 257                                 int vdd)
 258 {
 259         u32 reg;
 260         int ret = 0;
 261         struct twl_mmc_controller *c = &hsmmc[0];
 262         struct omap_mmc_platform_data *mmc = dev->platform_data;
 263
 264         /*
 265          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 266          * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both
 267          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 268          *
 269          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
 270          * is most naturally TWL VSIM; those pins also use PBIAS.
 271          */
 272         if (power_on) {
 273                 if (cpu_is_omap2430()) {
 274                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
 275                         if ((1 << vdd) >= MMC_VDD_30_31)
 276                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
 277                         else
 278                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
 279                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
 280                 }
 281
 282                 if (mmc->slots[0].internal_clock) {
 283                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 284                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
 285                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
 286                 }
 287
 288                 reg = omap_ctrl_readl(control_pbias_offset);
 289                 reg |= OMAP2_PBIASSPEEDCTRL0;
 290                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 291                 omap_ctrl_writel(reg, control_pbias_offset);
 292
 293                 ret = twl_mmc_set_voltage(c, vdd);
 294
 295                 /* 100ms delay required for PBIAS configuration */
 296                 msleep(100);
 297                 reg = omap_ctrl_readl(control_pbias_offset);
 298                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 299                 if ((1 << vdd) <= MMC_VDD_165_195)
 300                         reg &= ~OMAP2_PBIASLITEVMODE0;
 301                 else
 302                         reg |= OMAP2_PBIASLITEVMODE0;
 303                 omap_ctrl_writel(reg, control_pbias_offset);
 304         } else {
 305                 reg = omap_ctrl_readl(control_pbias_offset);
 306                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 307                 omap_ctrl_writel(reg, control_pbias_offset);
 308
 309                 ret = twl_mmc_set_voltage(c, 0);
 310
 311                 /* 100ms delay required for PBIAS configuration */
 312                 msleep(100);
 313                 reg = omap_ctrl_readl(control_pbias_offset);
 314                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 315                         OMAP2_PBIASLITEVMODE0);
 316                 omap_ctrl_writel(reg, control_pbias_offset);
 317         }
 318
 319         return ret;
 320 }
 321
 322 static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
 323 {
 324         int ret;
 325         struct twl_mmc_controller *c = &hsmmc[1];
 326         struct omap_mmc_platform_data *mmc = dev->platform_data;
 327
 328         /*
 329          * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP
 330          * VDDS is used to power the pins, optionally with a transceiver to
 331          * support cards using voltages other than VDDS (1.8V nominal).  When a
 332          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 333          */
 334         if (power_on) {
 335                 if (mmc->slots[0].internal_clock) {
 336                         u32 reg;
 337
 338                         reg = omap_ctrl_readl(control_devconf1_offset);
 339                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 340                         omap_ctrl_writel(reg, control_devconf1_offset);
 341                 }
 342                 ret = twl_mmc_set_voltage(c, vdd);
 343         } else {
 344                 ret = twl_mmc_set_voltage(c, 0);
 345         }
 346
 347         return ret;
 348 }
 349
 350 static int twl_mmc3_set_power(struct device *dev, int slot, int power_on,
 351                 int vdd)
 352 {
 353         /*
 354          * Assume MMC3 has self-powered device connected, for example on-board
 355          * chip with external power source.
 356          */
 357         return 0;
 358 }
 359
 360 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
 361
 362 void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
 363 {
 364         struct twl4030_hsmmc_info *c;
 365         int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
 366
 367         if (cpu_is_omap2430()) {
 368                 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 369                 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 370                 nr_hsmmc = 2;
 371         } else {
 372                 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 373                 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 374         }
 375
 376         for (c = controllers; c->mmc; c++) {
 377                 struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
 378                 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
 379
 380                 if (!c->mmc || c->mmc > nr_hsmmc) {
 381                         pr_debug("MMC%d: no such controller\n", c->mmc);
 382                         continue;
 383                 }
 384                 if (mmc) {
 385                         pr_debug("MMC%d: already configured\n", c->mmc);
 386                         continue;
 387                 }
 388
 389                 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 390                 if (!mmc) {
 391                         pr_err("Cannot allocate memory for mmc device!\n");
 392                         return;
 393                 }
 394
 395                 snprintf(twl->name, ARRAY_SIZE(twl->name), "mmc%islot%i",
 396                                 c->mmc, 1);
 397                 mmc->slots[0].name = twl->name;
 398                 mmc->nr_slots = 1;
 399                 mmc->slots[0].wires = c->wires;
 400                 mmc->slots[0].internal_clock = !c->ext_clock;
 401                 mmc->dma_mask = 0xffffffff;
 402
 403                 /* note: twl4030 card detect GPIOs normally switch VMMCx ... */
 404                 if (gpio_is_valid(c->gpio_cd)) {
 405                         mmc->init = twl_mmc_late_init;
 406                         mmc->cleanup = twl_mmc_cleanup;
 407                         mmc->suspend = twl_mmc_suspend;
 408                         mmc->resume = twl_mmc_resume;
 409
 410                         mmc->slots[0].switch_pin = c->gpio_cd;
 411                         mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
 412                         mmc->slots[0].card_detect = twl_mmc_card_detect;
 413                 } else
 414                         mmc->slots[0].switch_pin = -EINVAL;
 415
 416                 /* write protect normally uses an OMAP gpio */
 417                 if (gpio_is_valid(c->gpio_wp)) {
 418                         gpio_request(c->gpio_wp, "mmc_wp");
 419                         gpio_direction_input(c->gpio_wp);
 420
 421                         mmc->slots[0].gpio_wp = c->gpio_wp;
 422                         mmc->slots[0].get_ro = twl_mmc_get_ro;
 423                 } else
 424                         mmc->slots[0].gpio_wp = -EINVAL;
 425
 426                 /* NOTE:  we assume OMAP's MMC1 and MMC2 use
 427                  * the TWL4030's VMMC1 and VMMC2, respectively;
 428                  * and that MMC3 device has it's own power source.
 429                  */
 430
 431                 switch (c->mmc) {
 432                 case 1:
 433                         mmc->slots[0].set_power = twl_mmc1_set_power;
 434                         mmc->slots[0].ocr_mask = MMC1_OCR;
 435                         break;
 436                 case 2:
 437                         mmc->slots[0].set_power = twl_mmc2_set_power;
 438                         if (c->transceiver)
 439                                 mmc->slots[0].ocr_mask = MMC2_OCR;
 440                         else
 441                                 mmc->slots[0].ocr_mask = MMC_VDD_165_195;
 442                         break;
 443                 case 3:
 444                         mmc->slots[0].set_power = twl_mmc3_set_power;
 445                         mmc->slots[0].ocr_mask = MMC_VDD_165_195;
 446                         break;
 447                 default:
 448                         pr_err("MMC%d configuration not supported!\n", c->mmc);
 449                         kfree(mmc);
 450                         continue;
 451                 }
 452                 hsmmc_data[c->mmc - 1] = mmc;
 453         }
 454
 455         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
 456
 457         /* pass the device nodes back to board setup code */
 458         for (c = controllers; c->mmc; c++) {
 459                 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
 460
 461                 if (!c->mmc || c->mmc > nr_hsmmc)
 462                         continue;
 463                 c->dev = mmc->dev;
 464         }
 465 }
 466
 467 #endif