2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
4 * OMAP3 CPU IDLE Routines
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
18 * Based on pm.c for omap2
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
27 #include <linux/export.h>
29 #include <plat/prcm.h>
30 #include <plat/irqs.h>
31 #include "powerdomain.h"
32 #include "clockdomain.h"
33 #include <plat/serial.h>
38 #ifdef CONFIG_CPU_IDLE
41 * The latencies/thresholds for various C states have
42 * to be configured from the respective board files.
43 * These are some default values (which might not provide
44 * the best power savings) used on boards which do not
45 * pass these details from the board file.
47 static struct cpuidle_params cpuidle_params_table[] = {
55 {1500 + 1800, 4000, 1},
57 {2500 + 7500, 12000, 1},
59 {3000 + 8500, 15000, 1},
61 {10000 + 30000, 300000, 1},
63 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
65 /* Mach specific information to be recorded in the C-state driver_data */
66 struct omap3_idle_statedata {
71 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
73 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
76 * omap3_enter_idle - Programs OMAP3 to enter the specified state
77 * @dev: cpuidle device
78 * @drv: cpuidle driver
79 * @index: the index of state to be entered
81 * Called from the CPUidle framework to program the device to the
82 * specified target state selected by the governor.
84 static int omap3_enter_idle(struct cpuidle_device *dev,
85 struct cpuidle_driver *drv,
88 struct omap3_idle_statedata *cx =
89 cpuidle_get_statedata(&dev->states_usage[index]);
90 struct timespec ts_preidle, ts_postidle, ts_idle;
91 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
94 /* Used to keep track of the total time in idle */
95 getnstimeofday(&ts_preidle);
99 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
100 pwrdm_set_next_pwrst(core_pd, core_state);
102 if (omap_irq_pending() || need_resched())
103 goto return_sleep_time;
105 /* Deny idle for C1 */
107 clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
108 clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
111 /* Execute ARM wfi */
114 /* Re-allow idle for C1 */
116 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
117 clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
121 getnstimeofday(&ts_postidle);
122 ts_idle = timespec_sub(ts_postidle, ts_preidle);
126 idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
129 /* Update cpuidle counters */
130 dev->last_residency = idle_time;
136 * next_valid_state - Find next valid C-state
137 * @dev: cpuidle device
138 * @drv: cpuidle driver
139 * @index: Index of currently selected c-state
141 * If the state corresponding to index is valid, index is returned back
142 * to the caller. Else, this function searches for a lower c-state which is
143 * still valid (as defined in omap3_power_states[]) and returns its index.
145 * A state is valid if the 'valid' field is enabled and
146 * if it satisfies the enable_off_mode condition.
148 static int next_valid_state(struct cpuidle_device *dev,
149 struct cpuidle_driver *drv,
152 struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
153 struct cpuidle_state *curr = &drv->states[index];
154 struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
155 u32 mpu_deepest_state = PWRDM_POWER_RET;
156 u32 core_deepest_state = PWRDM_POWER_RET;
159 if (enable_off_mode) {
160 mpu_deepest_state = PWRDM_POWER_OFF;
162 * Erratum i583: valable for ES rev < Es1.2 on 3630.
163 * CORE OFF mode is not supported in a stable form, restrict
164 * instead the CORE state to RET.
166 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
167 core_deepest_state = PWRDM_POWER_OFF;
170 if (!omap_uart_can_sleep())
171 core_deepest_state = PWRDM_POWER_RET;
173 /* Check if current state is valid */
175 (cx->mpu_state >= mpu_deepest_state) &&
176 (cx->core_state >= core_deepest_state)) {
179 int idx = OMAP3_NUM_STATES - 1;
181 /* Reach the current state starting at highest C-state */
182 for (; idx >= 0; idx--) {
183 if (&drv->states[idx] == curr) {
189 /* Should never hit this condition */
190 WARN_ON(next_index == -1);
193 * Drop to next valid state.
194 * Start search from the next (lower) state.
197 for (; idx >= 0; idx--) {
198 cx = cpuidle_get_statedata(&dev->states_usage[idx]);
200 (cx->mpu_state >= mpu_deepest_state) &&
201 (cx->core_state >= core_deepest_state)) {
207 * C1 is always valid.
208 * So, no need to check for 'next_index == -1' outside
217 * omap3_enter_idle_bm - Checks for any bus activity
218 * @dev: cpuidle device
219 * @drv: cpuidle driver
220 * @index: array index of target state to be programmed
222 * This function checks for any pending activity and then programs
223 * the device to the specified or a safer state.
225 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
226 struct cpuidle_driver *drv,
230 u32 core_next_state, per_next_state = 0, per_saved_state = 0;
231 struct omap3_idle_statedata *cx;
235 * Use only C1 if CAM is active.
236 * CAM does not have wakeup capability in OMAP3.
238 if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
239 new_state_idx = drv->safe_state_index;
241 new_state_idx = next_valid_state(dev, drv, index);
244 * FIXME: we currently manage device-specific idle states
245 * for PER and CORE in combination with CPU-specific
246 * idle states. This is wrong, and device-specific
247 * idle management needs to be separated out into
251 /* Program PER state */
252 cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
253 core_next_state = cx->core_state;
254 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
255 if (new_state_idx == 0) {
256 /* In C1 do not allow PER state lower than CORE state */
257 if (per_next_state < core_next_state)
258 per_next_state = core_next_state;
261 * Prevent PER OFF if CORE is not in RETention or OFF as this
262 * would disable PER wakeups completely.
264 if ((per_next_state == PWRDM_POWER_OFF) &&
265 (core_next_state > PWRDM_POWER_RET))
266 per_next_state = PWRDM_POWER_RET;
269 /* Are we changing PER target state? */
270 if (per_next_state != per_saved_state)
271 pwrdm_set_next_pwrst(per_pd, per_next_state);
273 ret = omap3_enter_idle(dev, drv, new_state_idx);
275 /* Restore original PER state if it was modified */
276 if (per_next_state != per_saved_state)
277 pwrdm_set_next_pwrst(per_pd, per_saved_state);
282 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
284 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
288 if (!cpuidle_board_params)
291 for (i = 0; i < OMAP3_NUM_STATES; i++) {
292 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
293 cpuidle_params_table[i].exit_latency =
294 cpuidle_board_params[i].exit_latency;
295 cpuidle_params_table[i].target_residency =
296 cpuidle_board_params[i].target_residency;
301 struct cpuidle_driver omap3_idle_driver = {
302 .name = "omap3_idle",
303 .owner = THIS_MODULE,
306 /* Helper to fill the C-state common data*/
307 static inline void _fill_cstate(struct cpuidle_driver *drv,
308 int idx, const char *descr)
310 struct cpuidle_state *state = &drv->states[idx];
312 state->exit_latency = cpuidle_params_table[idx].exit_latency;
313 state->target_residency = cpuidle_params_table[idx].target_residency;
314 state->flags = CPUIDLE_FLAG_TIME_VALID;
315 state->enter = omap3_enter_idle_bm;
316 sprintf(state->name, "C%d", idx + 1);
317 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
321 /* Helper to register the driver_data */
322 static inline struct omap3_idle_statedata *_fill_cstate_usage(
323 struct cpuidle_device *dev,
326 struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
327 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
329 cx->valid = cpuidle_params_table[idx].valid;
330 cpuidle_set_statedata(state_usage, cx);
336 * omap3_idle_init - Init routine for OMAP3 idle
338 * Registers the OMAP3 specific cpuidle driver to the cpuidle
339 * framework with the valid set of states.
341 int __init omap3_idle_init(void)
343 struct cpuidle_device *dev;
344 struct cpuidle_driver *drv = &omap3_idle_driver;
345 struct omap3_idle_statedata *cx;
347 mpu_pd = pwrdm_lookup("mpu_pwrdm");
348 core_pd = pwrdm_lookup("core_pwrdm");
349 per_pd = pwrdm_lookup("per_pwrdm");
350 cam_pd = pwrdm_lookup("cam_pwrdm");
353 drv->safe_state_index = -1;
354 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
356 /* C1 . MPU WFI + Core active */
357 _fill_cstate(drv, 0, "MPU ON + CORE ON");
358 (&drv->states[0])->enter = omap3_enter_idle;
359 drv->safe_state_index = 0;
360 cx = _fill_cstate_usage(dev, 0);
361 cx->valid = 1; /* C1 is always valid */
362 cx->mpu_state = PWRDM_POWER_ON;
363 cx->core_state = PWRDM_POWER_ON;
365 /* C2 . MPU WFI + Core inactive */
366 _fill_cstate(drv, 1, "MPU ON + CORE ON");
367 cx = _fill_cstate_usage(dev, 1);
368 cx->mpu_state = PWRDM_POWER_ON;
369 cx->core_state = PWRDM_POWER_ON;
371 /* C3 . MPU CSWR + Core inactive */
372 _fill_cstate(drv, 2, "MPU RET + CORE ON");
373 cx = _fill_cstate_usage(dev, 2);
374 cx->mpu_state = PWRDM_POWER_RET;
375 cx->core_state = PWRDM_POWER_ON;
377 /* C4 . MPU OFF + Core inactive */
378 _fill_cstate(drv, 3, "MPU OFF + CORE ON");
379 cx = _fill_cstate_usage(dev, 3);
380 cx->mpu_state = PWRDM_POWER_OFF;
381 cx->core_state = PWRDM_POWER_ON;
383 /* C5 . MPU RET + Core RET */
384 _fill_cstate(drv, 4, "MPU RET + CORE RET");
385 cx = _fill_cstate_usage(dev, 4);
386 cx->mpu_state = PWRDM_POWER_RET;
387 cx->core_state = PWRDM_POWER_RET;
389 /* C6 . MPU OFF + Core RET */
390 _fill_cstate(drv, 5, "MPU OFF + CORE RET");
391 cx = _fill_cstate_usage(dev, 5);
392 cx->mpu_state = PWRDM_POWER_OFF;
393 cx->core_state = PWRDM_POWER_RET;
395 /* C7 . MPU OFF + Core OFF */
396 _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
397 cx = _fill_cstate_usage(dev, 6);
399 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
400 * enable OFF mode in a stable form for previous revisions.
401 * We disable C7 state as a result.
403 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
405 pr_warn("%s: core off state C7 disabled due to i583\n",
408 cx->mpu_state = PWRDM_POWER_OFF;
409 cx->core_state = PWRDM_POWER_OFF;
411 drv->state_count = OMAP3_NUM_STATES;
412 cpuidle_register_driver(&omap3_idle_driver);
414 dev->state_count = OMAP3_NUM_STATES;
415 if (cpuidle_register_device(dev)) {
416 printk(KERN_ERR "%s: CPUidle register device failed\n",
424 int __init omap3_idle_init(void)
428 #endif /* CONFIG_CPU_IDLE */