arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm-regbits-44xx.h"
  38 #include "control.h"
  39 #include "scrm44xx.h"
  40
  41 /* OMAP4 modulemode control */
  42 #define OMAP4430_MODULEMODE_HWCTRL                      0
  43 #define OMAP4430_MODULEMODE_SWCTRL                      1
  44
  45 /* Root clocks */
  46
  47 static struct clk extalt_clkin_ck = {
  48         .name           = "extalt_clkin_ck",
  49         .rate           = 59000000,
  50         .ops            = &clkops_null,
  51 };
  52
  53 static struct clk pad_clks_ck = {
  54         .name           = "pad_clks_ck",
  55         .rate           = 12000000,
  56         .ops            = &clkops_omap2_dflt,
  57         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  58         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  59 };
  60
  61 static struct clk pad_slimbus_core_clks_ck = {
  62         .name           = "pad_slimbus_core_clks_ck",
  63         .rate           = 12000000,
  64         .ops            = &clkops_null,
  65 };
  66
  67 static struct clk secure_32k_clk_src_ck = {
  68         .name           = "secure_32k_clk_src_ck",
  69         .rate           = 32768,
  70         .ops            = &clkops_null,
  71 };
  72
  73 static struct clk slimbus_clk = {
  74         .name           = "slimbus_clk",
  75         .rate           = 12000000,
  76         .ops            = &clkops_omap2_dflt,
  77         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  78         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  79 };
  80
  81 static struct clk sys_32k_ck = {
  82         .name           = "sys_32k_ck",
  83         .rate           = 32768,
  84         .ops            = &clkops_null,
  85 };
  86
  87 static struct clk virt_12000000_ck = {
  88         .name           = "virt_12000000_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 12000000,
  91 };
  92
  93 static struct clk virt_13000000_ck = {
  94         .name           = "virt_13000000_ck",
  95         .ops            = &clkops_null,
  96         .rate           = 13000000,
  97 };
  98
  99 static struct clk virt_16800000_ck = {
 100         .name           = "virt_16800000_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 16800000,
 103 };
 104
 105 static struct clk virt_19200000_ck = {
 106         .name           = "virt_19200000_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 19200000,
 109 };
 110
 111 static struct clk virt_26000000_ck = {
 112         .name           = "virt_26000000_ck",
 113         .ops            = &clkops_null,
 114         .rate           = 26000000,
 115 };
 116
 117 static struct clk virt_27000000_ck = {
 118         .name           = "virt_27000000_ck",
 119         .ops            = &clkops_null,
 120         .rate           = 27000000,
 121 };
 122
 123 static struct clk virt_38400000_ck = {
 124         .name           = "virt_38400000_ck",
 125         .ops            = &clkops_null,
 126         .rate           = 38400000,
 127 };
 128
 129 static const struct clksel_rate div_1_0_rates[] = {
 130         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 131         { .div = 0 },
 132 };
 133
 134 static const struct clksel_rate div_1_1_rates[] = {
 135         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 136         { .div = 0 },
 137 };
 138
 139 static const struct clksel_rate div_1_2_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 141         { .div = 0 },
 142 };
 143
 144 static const struct clksel_rate div_1_3_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 146         { .div = 0 },
 147 };
 148
 149 static const struct clksel_rate div_1_4_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 151         { .div = 0 },
 152 };
 153
 154 static const struct clksel_rate div_1_5_rates[] = {
 155         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 156         { .div = 0 },
 157 };
 158
 159 static const struct clksel_rate div_1_6_rates[] = {
 160         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 161         { .div = 0 },
 162 };
 163
 164 static const struct clksel_rate div_1_7_rates[] = {
 165         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel sys_clkin_sel[] = {
 170         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 171         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 172         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 173         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 174         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 175         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 176         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk sys_clkin_ck = {
 181         .name           = "sys_clkin_ck",
 182         .rate           = 38400000,
 183         .clksel         = sys_clkin_sel,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 186         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 187         .ops            = &clkops_null,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static struct clk tie_low_clock_ck = {
 192         .name           = "tie_low_clock_ck",
 193         .rate           = 0,
 194         .ops            = &clkops_null,
 195 };
 196
 197 static struct clk utmi_phy_clkout_ck = {
 198         .name           = "utmi_phy_clkout_ck",
 199         .rate           = 60000000,
 200         .ops            = &clkops_null,
 201 };
 202
 203 static struct clk xclk60mhsp1_ck = {
 204         .name           = "xclk60mhsp1_ck",
 205         .rate           = 60000000,
 206         .ops            = &clkops_null,
 207 };
 208
 209 static struct clk xclk60mhsp2_ck = {
 210         .name           = "xclk60mhsp2_ck",
 211         .rate           = 60000000,
 212         .ops            = &clkops_null,
 213 };
 214
 215 static struct clk xclk60motg_ck = {
 216         .name           = "xclk60motg_ck",
 217         .rate           = 60000000,
 218         .ops            = &clkops_null,
 219 };
 220
 221 /* Module clocks and DPLL outputs */
 222
 223 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 224         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 225         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 226         { .parent = NULL },
 227 };
 228
 229 static struct clk abe_dpll_bypass_clk_mux_ck = {
 230         .name           = "abe_dpll_bypass_clk_mux_ck",
 231         .parent         = &sys_clkin_ck,
 232         .ops            = &clkops_null,
 233         .recalc         = &followparent_recalc,
 234 };
 235
 236 static struct clk abe_dpll_refclk_mux_ck = {
 237         .name           = "abe_dpll_refclk_mux_ck",
 238         .parent         = &sys_clkin_ck,
 239         .clksel         = abe_dpll_bypass_clk_mux_sel,
 240         .init           = &omap2_init_clksel_parent,
 241         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 242         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 243         .ops            = &clkops_null,
 244         .recalc         = &omap2_clksel_recalc,
 245 };
 246
 247 /* DPLL_ABE */
 248 static struct dpll_data dpll_abe_dd = {
 249         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 250         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 251         .clk_ref        = &abe_dpll_refclk_mux_ck,
 252         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 253         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 254         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 255         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 256         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 257         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 258         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 259         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 260         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 261         .max_multiplier = 2047,
 262         .max_divider    = 128,
 263         .min_divider    = 1,
 264 };
 265
 266
 267 static struct clk dpll_abe_ck = {
 268         .name           = "dpll_abe_ck",
 269         .parent         = &abe_dpll_refclk_mux_ck,
 270         .dpll_data      = &dpll_abe_dd,
 271         .init           = &omap2_init_dpll_parent,
 272         .ops            = &clkops_omap3_noncore_dpll_ops,
 273         .recalc         = &omap3_dpll_recalc,
 274         .round_rate     = &omap2_dpll_round_rate,
 275         .set_rate       = &omap3_noncore_dpll_set_rate,
 276 };
 277
 278 static struct clk dpll_abe_x2_ck = {
 279         .name           = "dpll_abe_x2_ck",
 280         .parent         = &dpll_abe_ck,
 281         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 282         .flags          = CLOCK_CLKOUTX2,
 283         .ops            = &clkops_omap4_dpllmx_ops,
 284         .recalc         = &omap3_clkoutx2_recalc,
 285 };
 286
 287 static const struct clksel_rate div31_1to31_rates[] = {
 288         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 289         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 290         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 291         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 292         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 293         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 294         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 295         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 296         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 297         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 298         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 299         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 300         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 301         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 302         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 303         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 304         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 305         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 306         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 307         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 308         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 309         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 310         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 311         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 312         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 313         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 314         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 315         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 316         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 317         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 318         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 319         { .div = 0 },
 320 };
 321
 322 static const struct clksel dpll_abe_m2x2_div[] = {
 323         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 324         { .parent = NULL },
 325 };
 326
 327 static struct clk dpll_abe_m2x2_ck = {
 328         .name           = "dpll_abe_m2x2_ck",
 329         .parent         = &dpll_abe_x2_ck,
 330         .clksel         = dpll_abe_m2x2_div,
 331         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 332         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 333         .ops            = &clkops_omap4_dpllmx_ops,
 334         .recalc         = &omap2_clksel_recalc,
 335         .round_rate     = &omap2_clksel_round_rate,
 336         .set_rate       = &omap2_clksel_set_rate,
 337 };
 338
 339 static struct clk abe_24m_fclk = {
 340         .name           = "abe_24m_fclk",
 341         .parent         = &dpll_abe_m2x2_ck,
 342         .ops            = &clkops_null,
 343         .fixed_div      = 8,
 344         .recalc         = &omap_fixed_divisor_recalc,
 345 };
 346
 347 static const struct clksel_rate div3_1to4_rates[] = {
 348         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 349         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 350         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 351         { .div = 0 },
 352 };
 353
 354 static const struct clksel abe_clk_div[] = {
 355         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 356         { .parent = NULL },
 357 };
 358
 359 static struct clk abe_clk = {
 360         .name           = "abe_clk",
 361         .parent         = &dpll_abe_m2x2_ck,
 362         .clksel         = abe_clk_div,
 363         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 364         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 365         .ops            = &clkops_null,
 366         .recalc         = &omap2_clksel_recalc,
 367         .round_rate     = &omap2_clksel_round_rate,
 368         .set_rate       = &omap2_clksel_set_rate,
 369 };
 370
 371 static const struct clksel_rate div2_1to2_rates[] = {
 372         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 373         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 374         { .div = 0 },
 375 };
 376
 377 static const struct clksel aess_fclk_div[] = {
 378         { .parent = &abe_clk, .rates = div2_1to2_rates },
 379         { .parent = NULL },
 380 };
 381
 382 static struct clk aess_fclk = {
 383         .name           = "aess_fclk",
 384         .parent         = &abe_clk,
 385         .clksel         = aess_fclk_div,
 386         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 387         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 388         .ops            = &clkops_null,
 389         .recalc         = &omap2_clksel_recalc,
 390         .round_rate     = &omap2_clksel_round_rate,
 391         .set_rate       = &omap2_clksel_set_rate,
 392 };
 393
 394 static struct clk dpll_abe_m3x2_ck = {
 395         .name           = "dpll_abe_m3x2_ck",
 396         .parent         = &dpll_abe_x2_ck,
 397         .clksel         = dpll_abe_m2x2_div,
 398         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 399         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 400         .ops            = &clkops_omap4_dpllmx_ops,
 401         .recalc         = &omap2_clksel_recalc,
 402         .round_rate     = &omap2_clksel_round_rate,
 403         .set_rate       = &omap2_clksel_set_rate,
 404 };
 405
 406 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 407         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 408         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 409         { .parent = NULL },
 410 };
 411
 412 static struct clk core_hsd_byp_clk_mux_ck = {
 413         .name           = "core_hsd_byp_clk_mux_ck",
 414         .parent         = &sys_clkin_ck,
 415         .clksel         = core_hsd_byp_clk_mux_sel,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 418         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 419         .ops            = &clkops_null,
 420         .recalc         = &omap2_clksel_recalc,
 421 };
 422
 423 /* DPLL_CORE */
 424 static struct dpll_data dpll_core_dd = {
 425         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 426         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 427         .clk_ref        = &sys_clkin_ck,
 428         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 429         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 430         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 431         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 432         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 433         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 434         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 435         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 436         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 437         .max_multiplier = 2047,
 438         .max_divider    = 128,
 439         .min_divider    = 1,
 440 };
 441
 442
 443 static struct clk dpll_core_ck = {
 444         .name           = "dpll_core_ck",
 445         .parent         = &sys_clkin_ck,
 446         .dpll_data      = &dpll_core_dd,
 447         .init           = &omap2_init_dpll_parent,
 448         .ops            = &clkops_omap3_core_dpll_ops,
 449         .recalc         = &omap3_dpll_recalc,
 450 };
 451
 452 static struct clk dpll_core_x2_ck = {
 453         .name           = "dpll_core_x2_ck",
 454         .parent         = &dpll_core_ck,
 455         .flags          = CLOCK_CLKOUTX2,
 456         .ops            = &clkops_null,
 457         .recalc         = &omap3_clkoutx2_recalc,
 458 };
 459
 460 static const struct clksel dpll_core_m6x2_div[] = {
 461         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 462         { .parent = NULL },
 463 };
 464
 465 static struct clk dpll_core_m6x2_ck = {
 466         .name           = "dpll_core_m6x2_ck",
 467         .parent         = &dpll_core_x2_ck,
 468         .clksel         = dpll_core_m6x2_div,
 469         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 470         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 471         .ops            = &clkops_omap4_dpllmx_ops,
 472         .recalc         = &omap2_clksel_recalc,
 473         .round_rate     = &omap2_clksel_round_rate,
 474         .set_rate       = &omap2_clksel_set_rate,
 475 };
 476
 477 static const struct clksel dbgclk_mux_sel[] = {
 478         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 479         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 480         { .parent = NULL },
 481 };
 482
 483 static struct clk dbgclk_mux_ck = {
 484         .name           = "dbgclk_mux_ck",
 485         .parent         = &sys_clkin_ck,
 486         .ops            = &clkops_null,
 487         .recalc         = &followparent_recalc,
 488 };
 489
 490 static const struct clksel dpll_core_m2_div[] = {
 491         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 492         { .parent = NULL },
 493 };
 494
 495 static struct clk dpll_core_m2_ck = {
 496         .name           = "dpll_core_m2_ck",
 497         .parent         = &dpll_core_ck,
 498         .clksel         = dpll_core_m2_div,
 499         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 500         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 501         .ops            = &clkops_omap4_dpllmx_ops,
 502         .recalc         = &omap2_clksel_recalc,
 503         .round_rate     = &omap2_clksel_round_rate,
 504         .set_rate       = &omap2_clksel_set_rate,
 505 };
 506
 507 static struct clk ddrphy_ck = {
 508         .name           = "ddrphy_ck",
 509         .parent         = &dpll_core_m2_ck,
 510         .ops            = &clkops_null,
 511         .fixed_div      = 2,
 512         .recalc         = &omap_fixed_divisor_recalc,
 513 };
 514
 515 static struct clk dpll_core_m5x2_ck = {
 516         .name           = "dpll_core_m5x2_ck",
 517         .parent         = &dpll_core_x2_ck,
 518         .clksel         = dpll_core_m6x2_div,
 519         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 520         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 521         .ops            = &clkops_omap4_dpllmx_ops,
 522         .recalc         = &omap2_clksel_recalc,
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap2_clksel_set_rate,
 525 };
 526
 527 static const struct clksel div_core_div[] = {
 528         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 529         { .parent = NULL },
 530 };
 531
 532 static struct clk div_core_ck = {
 533         .name           = "div_core_ck",
 534         .parent         = &dpll_core_m5x2_ck,
 535         .clksel         = div_core_div,
 536         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 537         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 538         .ops            = &clkops_null,
 539         .recalc         = &omap2_clksel_recalc,
 540         .round_rate     = &omap2_clksel_round_rate,
 541         .set_rate       = &omap2_clksel_set_rate,
 542 };
 543
 544 static const struct clksel_rate div4_1to8_rates[] = {
 545         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 546         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 547         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 548         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 549         { .div = 0 },
 550 };
 551
 552 static const struct clksel div_iva_hs_clk_div[] = {
 553         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 554         { .parent = NULL },
 555 };
 556
 557 static struct clk div_iva_hs_clk = {
 558         .name           = "div_iva_hs_clk",
 559         .parent         = &dpll_core_m5x2_ck,
 560         .clksel         = div_iva_hs_clk_div,
 561         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 562         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 563         .ops            = &clkops_null,
 564         .recalc         = &omap2_clksel_recalc,
 565         .round_rate     = &omap2_clksel_round_rate,
 566         .set_rate       = &omap2_clksel_set_rate,
 567 };
 568
 569 static struct clk div_mpu_hs_clk = {
 570         .name           = "div_mpu_hs_clk",
 571         .parent         = &dpll_core_m5x2_ck,
 572         .clksel         = div_iva_hs_clk_div,
 573         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 574         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 575         .ops            = &clkops_null,
 576         .recalc         = &omap2_clksel_recalc,
 577         .round_rate     = &omap2_clksel_round_rate,
 578         .set_rate       = &omap2_clksel_set_rate,
 579 };
 580
 581 static struct clk dpll_core_m4x2_ck = {
 582         .name           = "dpll_core_m4x2_ck",
 583         .parent         = &dpll_core_x2_ck,
 584         .clksel         = dpll_core_m6x2_div,
 585         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 586         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 587         .ops            = &clkops_omap4_dpllmx_ops,
 588         .recalc         = &omap2_clksel_recalc,
 589         .round_rate     = &omap2_clksel_round_rate,
 590         .set_rate       = &omap2_clksel_set_rate,
 591 };
 592
 593 static struct clk dll_clk_div_ck = {
 594         .name           = "dll_clk_div_ck",
 595         .parent         = &dpll_core_m4x2_ck,
 596         .ops            = &clkops_null,
 597         .fixed_div      = 2,
 598         .recalc         = &omap_fixed_divisor_recalc,
 599 };
 600
 601 static const struct clksel dpll_abe_m2_div[] = {
 602         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 603         { .parent = NULL },
 604 };
 605
 606 static struct clk dpll_abe_m2_ck = {
 607         .name           = "dpll_abe_m2_ck",
 608         .parent         = &dpll_abe_ck,
 609         .clksel         = dpll_abe_m2_div,
 610         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 611         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 612         .ops            = &clkops_omap4_dpllmx_ops,
 613         .recalc         = &omap2_clksel_recalc,
 614         .round_rate     = &omap2_clksel_round_rate,
 615         .set_rate       = &omap2_clksel_set_rate,
 616 };
 617
 618 static struct clk dpll_core_m3x2_ck = {
 619         .name           = "dpll_core_m3x2_ck",
 620         .parent         = &dpll_core_x2_ck,
 621         .clksel         = dpll_core_m6x2_div,
 622         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 623         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 624         .ops            = &clkops_omap2_dflt,
 625         .recalc         = &omap2_clksel_recalc,
 626         .round_rate     = &omap2_clksel_round_rate,
 627         .set_rate       = &omap2_clksel_set_rate,
 628         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 629         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 630 };
 631
 632 static struct clk dpll_core_m7x2_ck = {
 633         .name           = "dpll_core_m7x2_ck",
 634         .parent         = &dpll_core_x2_ck,
 635         .clksel         = dpll_core_m6x2_div,
 636         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 637         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 638         .ops            = &clkops_omap4_dpllmx_ops,
 639         .recalc         = &omap2_clksel_recalc,
 640         .round_rate     = &omap2_clksel_round_rate,
 641         .set_rate       = &omap2_clksel_set_rate,
 642 };
 643
 644 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 645         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 646         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 647         { .parent = NULL },
 648 };
 649
 650 static struct clk iva_hsd_byp_clk_mux_ck = {
 651         .name           = "iva_hsd_byp_clk_mux_ck",
 652         .parent         = &sys_clkin_ck,
 653         .clksel         = iva_hsd_byp_clk_mux_sel,
 654         .init           = &omap2_init_clksel_parent,
 655         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 656         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 657         .ops            = &clkops_null,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 /* DPLL_IVA */
 662 static struct dpll_data dpll_iva_dd = {
 663         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 664         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 665         .clk_ref        = &sys_clkin_ck,
 666         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 667         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 668         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 669         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 670         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 671         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 672         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 673         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 674         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 675         .max_multiplier = 2047,
 676         .max_divider    = 128,
 677         .min_divider    = 1,
 678 };
 679
 680
 681 static struct clk dpll_iva_ck = {
 682         .name           = "dpll_iva_ck",
 683         .parent         = &sys_clkin_ck,
 684         .dpll_data      = &dpll_iva_dd,
 685         .init           = &omap2_init_dpll_parent,
 686         .ops            = &clkops_omap3_noncore_dpll_ops,
 687         .recalc         = &omap3_dpll_recalc,
 688         .round_rate     = &omap2_dpll_round_rate,
 689         .set_rate       = &omap3_noncore_dpll_set_rate,
 690 };
 691
 692 static struct clk dpll_iva_x2_ck = {
 693         .name           = "dpll_iva_x2_ck",
 694         .parent         = &dpll_iva_ck,
 695         .flags          = CLOCK_CLKOUTX2,
 696         .ops            = &clkops_null,
 697         .recalc         = &omap3_clkoutx2_recalc,
 698 };
 699
 700 static const struct clksel dpll_iva_m4x2_div[] = {
 701         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 702         { .parent = NULL },
 703 };
 704
 705 static struct clk dpll_iva_m4x2_ck = {
 706         .name           = "dpll_iva_m4x2_ck",
 707         .parent         = &dpll_iva_x2_ck,
 708         .clksel         = dpll_iva_m4x2_div,
 709         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 710         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 711         .ops            = &clkops_omap4_dpllmx_ops,
 712         .recalc         = &omap2_clksel_recalc,
 713         .round_rate     = &omap2_clksel_round_rate,
 714         .set_rate       = &omap2_clksel_set_rate,
 715 };
 716
 717 static struct clk dpll_iva_m5x2_ck = {
 718         .name           = "dpll_iva_m5x2_ck",
 719         .parent         = &dpll_iva_x2_ck,
 720         .clksel         = dpll_iva_m4x2_div,
 721         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 722         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 723         .ops            = &clkops_omap4_dpllmx_ops,
 724         .recalc         = &omap2_clksel_recalc,
 725         .round_rate     = &omap2_clksel_round_rate,
 726         .set_rate       = &omap2_clksel_set_rate,
 727 };
 728
 729 /* DPLL_MPU */
 730 static struct dpll_data dpll_mpu_dd = {
 731         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 732         .clk_bypass     = &div_mpu_hs_clk,
 733         .clk_ref        = &sys_clkin_ck,
 734         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 735         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 736         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 737         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 738         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 739         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 740         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 741         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 742         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 743         .max_multiplier = 2047,
 744         .max_divider    = 128,
 745         .min_divider    = 1,
 746 };
 747
 748
 749 static struct clk dpll_mpu_ck = {
 750         .name           = "dpll_mpu_ck",
 751         .parent         = &sys_clkin_ck,
 752         .dpll_data      = &dpll_mpu_dd,
 753         .init           = &omap2_init_dpll_parent,
 754         .ops            = &clkops_omap3_noncore_dpll_ops,
 755         .recalc         = &omap3_dpll_recalc,
 756         .round_rate     = &omap2_dpll_round_rate,
 757         .set_rate       = &omap3_noncore_dpll_set_rate,
 758 };
 759
 760 static const struct clksel dpll_mpu_m2_div[] = {
 761         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 762         { .parent = NULL },
 763 };
 764
 765 static struct clk dpll_mpu_m2_ck = {
 766         .name           = "dpll_mpu_m2_ck",
 767         .parent         = &dpll_mpu_ck,
 768         .clksel         = dpll_mpu_m2_div,
 769         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 770         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 771         .ops            = &clkops_omap4_dpllmx_ops,
 772         .recalc         = &omap2_clksel_recalc,
 773         .round_rate     = &omap2_clksel_round_rate,
 774         .set_rate       = &omap2_clksel_set_rate,
 775 };
 776
 777 static struct clk per_hs_clk_div_ck = {
 778         .name           = "per_hs_clk_div_ck",
 779         .parent         = &dpll_abe_m3x2_ck,
 780         .ops            = &clkops_null,
 781         .fixed_div      = 2,
 782         .recalc         = &omap_fixed_divisor_recalc,
 783 };
 784
 785 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 786         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 787         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 788         { .parent = NULL },
 789 };
 790
 791 static struct clk per_hsd_byp_clk_mux_ck = {
 792         .name           = "per_hsd_byp_clk_mux_ck",
 793         .parent         = &sys_clkin_ck,
 794         .clksel         = per_hsd_byp_clk_mux_sel,
 795         .init           = &omap2_init_clksel_parent,
 796         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 797         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 798         .ops            = &clkops_null,
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 /* DPLL_PER */
 803 static struct dpll_data dpll_per_dd = {
 804         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 805         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 806         .clk_ref        = &sys_clkin_ck,
 807         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 808         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 809         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 810         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 811         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 812         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 813         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 814         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 815         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 816         .max_multiplier = 2047,
 817         .max_divider    = 128,
 818         .min_divider    = 1,
 819 };
 820
 821
 822 static struct clk dpll_per_ck = {
 823         .name           = "dpll_per_ck",
 824         .parent         = &sys_clkin_ck,
 825         .dpll_data      = &dpll_per_dd,
 826         .init           = &omap2_init_dpll_parent,
 827         .ops            = &clkops_omap3_noncore_dpll_ops,
 828         .recalc         = &omap3_dpll_recalc,
 829         .round_rate     = &omap2_dpll_round_rate,
 830         .set_rate       = &omap3_noncore_dpll_set_rate,
 831 };
 832
 833 static const struct clksel dpll_per_m2_div[] = {
 834         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 835         { .parent = NULL },
 836 };
 837
 838 static struct clk dpll_per_m2_ck = {
 839         .name           = "dpll_per_m2_ck",
 840         .parent         = &dpll_per_ck,
 841         .clksel         = dpll_per_m2_div,
 842         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 843         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 844         .ops            = &clkops_omap4_dpllmx_ops,
 845         .recalc         = &omap2_clksel_recalc,
 846         .round_rate     = &omap2_clksel_round_rate,
 847         .set_rate       = &omap2_clksel_set_rate,
 848 };
 849
 850 static struct clk dpll_per_x2_ck = {
 851         .name           = "dpll_per_x2_ck",
 852         .parent         = &dpll_per_ck,
 853         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 854         .flags          = CLOCK_CLKOUTX2,
 855         .ops            = &clkops_omap4_dpllmx_ops,
 856         .recalc         = &omap3_clkoutx2_recalc,
 857 };
 858
 859 static const struct clksel dpll_per_m2x2_div[] = {
 860         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 861         { .parent = NULL },
 862 };
 863
 864 static struct clk dpll_per_m2x2_ck = {
 865         .name           = "dpll_per_m2x2_ck",
 866         .parent         = &dpll_per_x2_ck,
 867         .clksel         = dpll_per_m2x2_div,
 868         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 869         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 870         .ops            = &clkops_omap4_dpllmx_ops,
 871         .recalc         = &omap2_clksel_recalc,
 872         .round_rate     = &omap2_clksel_round_rate,
 873         .set_rate       = &omap2_clksel_set_rate,
 874 };
 875
 876 static struct clk dpll_per_m3x2_ck = {
 877         .name           = "dpll_per_m3x2_ck",
 878         .parent         = &dpll_per_x2_ck,
 879         .clksel         = dpll_per_m2x2_div,
 880         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 881         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 882         .ops            = &clkops_omap2_dflt,
 883         .recalc         = &omap2_clksel_recalc,
 884         .round_rate     = &omap2_clksel_round_rate,
 885         .set_rate       = &omap2_clksel_set_rate,
 886         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 887         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 888 };
 889
 890 static struct clk dpll_per_m4x2_ck = {
 891         .name           = "dpll_per_m4x2_ck",
 892         .parent         = &dpll_per_x2_ck,
 893         .clksel         = dpll_per_m2x2_div,
 894         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 895         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 896         .ops            = &clkops_omap4_dpllmx_ops,
 897         .recalc         = &omap2_clksel_recalc,
 898         .round_rate     = &omap2_clksel_round_rate,
 899         .set_rate       = &omap2_clksel_set_rate,
 900 };
 901
 902 static struct clk dpll_per_m5x2_ck = {
 903         .name           = "dpll_per_m5x2_ck",
 904         .parent         = &dpll_per_x2_ck,
 905         .clksel         = dpll_per_m2x2_div,
 906         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 907         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 908         .ops            = &clkops_omap4_dpllmx_ops,
 909         .recalc         = &omap2_clksel_recalc,
 910         .round_rate     = &omap2_clksel_round_rate,
 911         .set_rate       = &omap2_clksel_set_rate,
 912 };
 913
 914 static struct clk dpll_per_m6x2_ck = {
 915         .name           = "dpll_per_m6x2_ck",
 916         .parent         = &dpll_per_x2_ck,
 917         .clksel         = dpll_per_m2x2_div,
 918         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 919         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 920         .ops            = &clkops_omap4_dpllmx_ops,
 921         .recalc         = &omap2_clksel_recalc,
 922         .round_rate     = &omap2_clksel_round_rate,
 923         .set_rate       = &omap2_clksel_set_rate,
 924 };
 925
 926 static struct clk dpll_per_m7x2_ck = {
 927         .name           = "dpll_per_m7x2_ck",
 928         .parent         = &dpll_per_x2_ck,
 929         .clksel         = dpll_per_m2x2_div,
 930         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 931         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 932         .ops            = &clkops_omap4_dpllmx_ops,
 933         .recalc         = &omap2_clksel_recalc,
 934         .round_rate     = &omap2_clksel_round_rate,
 935         .set_rate       = &omap2_clksel_set_rate,
 936 };
 937
 938 static struct clk usb_hs_clk_div_ck = {
 939         .name           = "usb_hs_clk_div_ck",
 940         .parent         = &dpll_abe_m3x2_ck,
 941         .ops            = &clkops_null,
 942         .fixed_div      = 3,
 943         .recalc         = &omap_fixed_divisor_recalc,
 944 };
 945
 946 /* DPLL_USB */
 947 static struct dpll_data dpll_usb_dd = {
 948         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 949         .clk_bypass     = &usb_hs_clk_div_ck,
 950         .flags          = DPLL_J_TYPE,
 951         .clk_ref        = &sys_clkin_ck,
 952         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 953         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 954         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 955         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 956         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 957         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 958         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 959         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 960         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 961         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 962         .max_multiplier = 4095,
 963         .max_divider    = 256,
 964         .min_divider    = 1,
 965 };
 966
 967
 968 static struct clk dpll_usb_ck = {
 969         .name           = "dpll_usb_ck",
 970         .parent         = &sys_clkin_ck,
 971         .dpll_data      = &dpll_usb_dd,
 972         .init           = &omap2_init_dpll_parent,
 973         .ops            = &clkops_omap3_noncore_dpll_ops,
 974         .recalc         = &omap3_dpll_recalc,
 975         .round_rate     = &omap2_dpll_round_rate,
 976         .set_rate       = &omap3_noncore_dpll_set_rate,
 977 };
 978
 979 static struct clk dpll_usb_clkdcoldo_ck = {
 980         .name           = "dpll_usb_clkdcoldo_ck",
 981         .parent         = &dpll_usb_ck,
 982         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 983         .ops            = &clkops_omap4_dpllmx_ops,
 984         .recalc         = &followparent_recalc,
 985 };
 986
 987 static const struct clksel dpll_usb_m2_div[] = {
 988         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
 989         { .parent = NULL },
 990 };
 991
 992 static struct clk dpll_usb_m2_ck = {
 993         .name           = "dpll_usb_m2_ck",
 994         .parent         = &dpll_usb_ck,
 995         .clksel         = dpll_usb_m2_div,
 996         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
 997         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
 998         .ops            = &clkops_omap4_dpllmx_ops,
 999         .recalc         = &omap2_clksel_recalc,
1000         .round_rate     = &omap2_clksel_round_rate,
1001         .set_rate       = &omap2_clksel_set_rate,
1002 };
1003
1004 static const struct clksel ducati_clk_mux_sel[] = {
1005         { .parent = &div_core_ck, .rates = div_1_0_rates },
1006         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1007         { .parent = NULL },
1008 };
1009
1010 static struct clk ducati_clk_mux_ck = {
1011         .name           = "ducati_clk_mux_ck",
1012         .parent         = &div_core_ck,
1013         .clksel         = ducati_clk_mux_sel,
1014         .init           = &omap2_init_clksel_parent,
1015         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1016         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1017         .ops            = &clkops_null,
1018         .recalc         = &omap2_clksel_recalc,
1019 };
1020
1021 static struct clk func_12m_fclk = {
1022         .name           = "func_12m_fclk",
1023         .parent         = &dpll_per_m2x2_ck,
1024         .ops            = &clkops_null,
1025         .fixed_div      = 16,
1026         .recalc         = &omap_fixed_divisor_recalc,
1027 };
1028
1029 static struct clk func_24m_clk = {
1030         .name           = "func_24m_clk",
1031         .parent         = &dpll_per_m2_ck,
1032         .ops            = &clkops_null,
1033         .fixed_div      = 4,
1034         .recalc         = &omap_fixed_divisor_recalc,
1035 };
1036
1037 static struct clk func_24mc_fclk = {
1038         .name           = "func_24mc_fclk",
1039         .parent         = &dpll_per_m2x2_ck,
1040         .ops            = &clkops_null,
1041         .fixed_div      = 8,
1042         .recalc         = &omap_fixed_divisor_recalc,
1043 };
1044
1045 static const struct clksel_rate div2_4to8_rates[] = {
1046         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1047         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1048         { .div = 0 },
1049 };
1050
1051 static const struct clksel func_48m_fclk_div[] = {
1052         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1053         { .parent = NULL },
1054 };
1055
1056 static struct clk func_48m_fclk = {
1057         .name           = "func_48m_fclk",
1058         .parent         = &dpll_per_m2x2_ck,
1059         .clksel         = func_48m_fclk_div,
1060         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1061         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1062         .ops            = &clkops_null,
1063         .recalc         = &omap2_clksel_recalc,
1064         .round_rate     = &omap2_clksel_round_rate,
1065         .set_rate       = &omap2_clksel_set_rate,
1066 };
1067
1068 static struct clk func_48mc_fclk = {
1069         .name           = "func_48mc_fclk",
1070         .parent         = &dpll_per_m2x2_ck,
1071         .ops            = &clkops_null,
1072         .fixed_div      = 4,
1073         .recalc         = &omap_fixed_divisor_recalc,
1074 };
1075
1076 static const struct clksel_rate div2_2to4_rates[] = {
1077         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1078         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1079         { .div = 0 },
1080 };
1081
1082 static const struct clksel func_64m_fclk_div[] = {
1083         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1084         { .parent = NULL },
1085 };
1086
1087 static struct clk func_64m_fclk = {
1088         .name           = "func_64m_fclk",
1089         .parent         = &dpll_per_m4x2_ck,
1090         .clksel         = func_64m_fclk_div,
1091         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1092         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1093         .ops            = &clkops_null,
1094         .recalc         = &omap2_clksel_recalc,
1095         .round_rate     = &omap2_clksel_round_rate,
1096         .set_rate       = &omap2_clksel_set_rate,
1097 };
1098
1099 static const struct clksel func_96m_fclk_div[] = {
1100         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1101         { .parent = NULL },
1102 };
1103
1104 static struct clk func_96m_fclk = {
1105         .name           = "func_96m_fclk",
1106         .parent         = &dpll_per_m2x2_ck,
1107         .clksel         = func_96m_fclk_div,
1108         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1109         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1110         .ops            = &clkops_null,
1111         .recalc         = &omap2_clksel_recalc,
1112         .round_rate     = &omap2_clksel_round_rate,
1113         .set_rate       = &omap2_clksel_set_rate,
1114 };
1115
1116 static const struct clksel_rate div2_1to8_rates[] = {
1117         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1118         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1119         { .div = 0 },
1120 };
1121
1122 static const struct clksel init_60m_fclk_div[] = {
1123         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1124         { .parent = NULL },
1125 };
1126
1127 static struct clk init_60m_fclk = {
1128         .name           = "init_60m_fclk",
1129         .parent         = &dpll_usb_m2_ck,
1130         .clksel         = init_60m_fclk_div,
1131         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1132         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1133         .ops            = &clkops_null,
1134         .recalc         = &omap2_clksel_recalc,
1135         .round_rate     = &omap2_clksel_round_rate,
1136         .set_rate       = &omap2_clksel_set_rate,
1137 };
1138
1139 static const struct clksel l3_div_div[] = {
1140         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1141         { .parent = NULL },
1142 };
1143
1144 static struct clk l3_div_ck = {
1145         .name           = "l3_div_ck",
1146         .parent         = &div_core_ck,
1147         .clksel         = l3_div_div,
1148         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1149         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1150         .ops            = &clkops_null,
1151         .recalc         = &omap2_clksel_recalc,
1152         .round_rate     = &omap2_clksel_round_rate,
1153         .set_rate       = &omap2_clksel_set_rate,
1154 };
1155
1156 static const struct clksel l4_div_div[] = {
1157         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1158         { .parent = NULL },
1159 };
1160
1161 static struct clk l4_div_ck = {
1162         .name           = "l4_div_ck",
1163         .parent         = &l3_div_ck,
1164         .clksel         = l4_div_div,
1165         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1166         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1167         .ops            = &clkops_null,
1168         .recalc         = &omap2_clksel_recalc,
1169         .round_rate     = &omap2_clksel_round_rate,
1170         .set_rate       = &omap2_clksel_set_rate,
1171 };
1172
1173 static struct clk lp_clk_div_ck = {
1174         .name           = "lp_clk_div_ck",
1175         .parent         = &dpll_abe_m2x2_ck,
1176         .ops            = &clkops_null,
1177         .fixed_div      = 16,
1178         .recalc         = &omap_fixed_divisor_recalc,
1179 };
1180
1181 static const struct clksel l4_wkup_clk_mux_sel[] = {
1182         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1183         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1184         { .parent = NULL },
1185 };
1186
1187 static struct clk l4_wkup_clk_mux_ck = {
1188         .name           = "l4_wkup_clk_mux_ck",
1189         .parent         = &sys_clkin_ck,
1190         .clksel         = l4_wkup_clk_mux_sel,
1191         .init           = &omap2_init_clksel_parent,
1192         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1193         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1194         .ops            = &clkops_null,
1195         .recalc         = &omap2_clksel_recalc,
1196 };
1197
1198 static struct clk ocp_abe_iclk = {
1199         .name           = "ocp_abe_iclk",
1200         .parent         = &aess_fclk,
1201         .ops            = &clkops_null,
1202         .recalc         = &followparent_recalc,
1203 };
1204
1205 static struct clk per_abe_24m_fclk = {
1206         .name           = "per_abe_24m_fclk",
1207         .parent         = &dpll_abe_m2_ck,
1208         .ops            = &clkops_null,
1209         .fixed_div      = 4,
1210         .recalc         = &omap_fixed_divisor_recalc,
1211 };
1212
1213 static const struct clksel per_abe_nc_fclk_div[] = {
1214         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1215         { .parent = NULL },
1216 };
1217
1218 static struct clk per_abe_nc_fclk = {
1219         .name           = "per_abe_nc_fclk",
1220         .parent         = &dpll_abe_m2_ck,
1221         .clksel         = per_abe_nc_fclk_div,
1222         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1223         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1224         .ops            = &clkops_null,
1225         .recalc         = &omap2_clksel_recalc,
1226         .round_rate     = &omap2_clksel_round_rate,
1227         .set_rate       = &omap2_clksel_set_rate,
1228 };
1229
1230 static const struct clksel pmd_stm_clock_mux_sel[] = {
1231         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1232         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1233         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1234         { .parent = NULL },
1235 };
1236
1237 static struct clk pmd_stm_clock_mux_ck = {
1238         .name           = "pmd_stm_clock_mux_ck",
1239         .parent         = &sys_clkin_ck,
1240         .ops            = &clkops_null,
1241         .recalc         = &followparent_recalc,
1242 };
1243
1244 static struct clk pmd_trace_clk_mux_ck = {
1245         .name           = "pmd_trace_clk_mux_ck",
1246         .parent         = &sys_clkin_ck,
1247         .ops            = &clkops_null,
1248         .recalc         = &followparent_recalc,
1249 };
1250
1251 static const struct clksel syc_clk_div_div[] = {
1252         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1253         { .parent = NULL },
1254 };
1255
1256 static struct clk syc_clk_div_ck = {
1257         .name           = "syc_clk_div_ck",
1258         .parent         = &sys_clkin_ck,
1259         .clksel         = syc_clk_div_div,
1260         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1261         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1262         .ops            = &clkops_null,
1263         .recalc         = &omap2_clksel_recalc,
1264         .round_rate     = &omap2_clksel_round_rate,
1265         .set_rate       = &omap2_clksel_set_rate,
1266 };
1267
1268 /* Leaf clocks controlled by modules */
1269
1270 static struct clk aes1_fck = {
1271         .name           = "aes1_fck",
1272         .ops            = &clkops_omap2_dflt,
1273         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1274         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1275         .clkdm_name     = "l4_secure_clkdm",
1276         .parent         = &l3_div_ck,
1277         .recalc         = &followparent_recalc,
1278 };
1279
1280 static struct clk aes2_fck = {
1281         .name           = "aes2_fck",
1282         .ops            = &clkops_omap2_dflt,
1283         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1284         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1285         .clkdm_name     = "l4_secure_clkdm",
1286         .parent         = &l3_div_ck,
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 static struct clk aess_fck = {
1291         .name           = "aess_fck",
1292         .ops            = &clkops_omap2_dflt,
1293         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1294         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1295         .clkdm_name     = "abe_clkdm",
1296         .parent         = &aess_fclk,
1297         .recalc         = &followparent_recalc,
1298 };
1299
1300 static struct clk bandgap_fclk = {
1301         .name           = "bandgap_fclk",
1302         .ops            = &clkops_omap2_dflt,
1303         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1304         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1305         .clkdm_name     = "l4_wkup_clkdm",
1306         .parent         = &sys_32k_ck,
1307         .recalc         = &followparent_recalc,
1308 };
1309
1310 static struct clk des3des_fck = {
1311         .name           = "des3des_fck",
1312         .ops            = &clkops_omap2_dflt,
1313         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1314         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1315         .clkdm_name     = "l4_secure_clkdm",
1316         .parent         = &l4_div_ck,
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 static const struct clksel dmic_sync_mux_sel[] = {
1321         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1322         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1323         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1324         { .parent = NULL },
1325 };
1326
1327 static struct clk dmic_sync_mux_ck = {
1328         .name           = "dmic_sync_mux_ck",
1329         .parent         = &abe_24m_fclk,
1330         .clksel         = dmic_sync_mux_sel,
1331         .init           = &omap2_init_clksel_parent,
1332         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1333         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1334         .ops            = &clkops_null,
1335         .recalc         = &omap2_clksel_recalc,
1336 };
1337
1338 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1339         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1340         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1341         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1342         { .parent = NULL },
1343 };
1344
1345 /* Merged func_dmic_abe_gfclk into dmic */
1346 static struct clk dmic_fck = {
1347         .name           = "dmic_fck",
1348         .parent         = &dmic_sync_mux_ck,
1349         .clksel         = func_dmic_abe_gfclk_sel,
1350         .init           = &omap2_init_clksel_parent,
1351         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1352         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1353         .ops            = &clkops_omap2_dflt,
1354         .recalc         = &omap2_clksel_recalc,
1355         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1356         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1357         .clkdm_name     = "abe_clkdm",
1358 };
1359
1360 static struct clk dsp_fck = {
1361         .name           = "dsp_fck",
1362         .ops            = &clkops_omap2_dflt,
1363         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1364         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1365         .clkdm_name     = "tesla_clkdm",
1366         .parent         = &dpll_iva_m4x2_ck,
1367         .recalc         = &followparent_recalc,
1368 };
1369
1370 static struct clk dss_sys_clk = {
1371         .name           = "dss_sys_clk",
1372         .ops            = &clkops_omap2_dflt,
1373         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1374         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1375         .clkdm_name     = "l3_dss_clkdm",
1376         .parent         = &syc_clk_div_ck,
1377         .recalc         = &followparent_recalc,
1378 };
1379
1380 static struct clk dss_tv_clk = {
1381         .name           = "dss_tv_clk",
1382         .ops            = &clkops_omap2_dflt,
1383         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1384         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1385         .clkdm_name     = "l3_dss_clkdm",
1386         .parent         = &extalt_clkin_ck,
1387         .recalc         = &followparent_recalc,
1388 };
1389
1390 static struct clk dss_dss_clk = {
1391         .name           = "dss_dss_clk",
1392         .ops            = &clkops_omap2_dflt,
1393         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1394         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1395         .clkdm_name     = "l3_dss_clkdm",
1396         .parent         = &dpll_per_m5x2_ck,
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static struct clk dss_48mhz_clk = {
1401         .name           = "dss_48mhz_clk",
1402         .ops            = &clkops_omap2_dflt,
1403         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1404         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1405         .clkdm_name     = "l3_dss_clkdm",
1406         .parent         = &func_48mc_fclk,
1407         .recalc         = &followparent_recalc,
1408 };
1409
1410 static struct clk dss_fck = {
1411         .name           = "dss_fck",
1412         .ops            = &clkops_omap2_dflt,
1413         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1414         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1415         .clkdm_name     = "l3_dss_clkdm",
1416         .parent         = &l3_div_ck,
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 static struct clk efuse_ctrl_cust_fck = {
1421         .name           = "efuse_ctrl_cust_fck",
1422         .ops            = &clkops_omap2_dflt,
1423         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1424         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1425         .clkdm_name     = "l4_cefuse_clkdm",
1426         .parent         = &sys_clkin_ck,
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk emif1_fck = {
1431         .name           = "emif1_fck",
1432         .ops            = &clkops_omap2_dflt,
1433         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1434         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1435         .flags          = ENABLE_ON_INIT,
1436         .clkdm_name     = "l3_emif_clkdm",
1437         .parent         = &ddrphy_ck,
1438         .recalc         = &followparent_recalc,
1439 };
1440
1441 static struct clk emif2_fck = {
1442         .name           = "emif2_fck",
1443         .ops            = &clkops_omap2_dflt,
1444         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1445         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1446         .flags          = ENABLE_ON_INIT,
1447         .clkdm_name     = "l3_emif_clkdm",
1448         .parent         = &ddrphy_ck,
1449         .recalc         = &followparent_recalc,
1450 };
1451
1452 static const struct clksel fdif_fclk_div[] = {
1453         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1454         { .parent = NULL },
1455 };
1456
1457 /* Merged fdif_fclk into fdif */
1458 static struct clk fdif_fck = {
1459         .name           = "fdif_fck",
1460         .parent         = &dpll_per_m4x2_ck,
1461         .clksel         = fdif_fclk_div,
1462         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1463         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1464         .ops            = &clkops_omap2_dflt,
1465         .recalc         = &omap2_clksel_recalc,
1466         .round_rate     = &omap2_clksel_round_rate,
1467         .set_rate       = &omap2_clksel_set_rate,
1468         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1469         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1470         .clkdm_name     = "iss_clkdm",
1471 };
1472
1473 static struct clk fpka_fck = {
1474         .name           = "fpka_fck",
1475         .ops            = &clkops_omap2_dflt,
1476         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1477         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1478         .clkdm_name     = "l4_secure_clkdm",
1479         .parent         = &l4_div_ck,
1480         .recalc         = &followparent_recalc,
1481 };
1482
1483 static struct clk gpio1_dbclk = {
1484         .name           = "gpio1_dbclk",
1485         .ops            = &clkops_omap2_dflt,
1486         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1487         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1488         .clkdm_name     = "l4_wkup_clkdm",
1489         .parent         = &sys_32k_ck,
1490         .recalc         = &followparent_recalc,
1491 };
1492
1493 static struct clk gpio1_ick = {
1494         .name           = "gpio1_ick",
1495         .ops            = &clkops_omap2_dflt,
1496         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1497         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1498         .clkdm_name     = "l4_wkup_clkdm",
1499         .parent         = &l4_wkup_clk_mux_ck,
1500         .recalc         = &followparent_recalc,
1501 };
1502
1503 static struct clk gpio2_dbclk = {
1504         .name           = "gpio2_dbclk",
1505         .ops            = &clkops_omap2_dflt,
1506         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1507         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1508         .clkdm_name     = "l4_per_clkdm",
1509         .parent         = &sys_32k_ck,
1510         .recalc         = &followparent_recalc,
1511 };
1512
1513 static struct clk gpio2_ick = {
1514         .name           = "gpio2_ick",
1515         .ops            = &clkops_omap2_dflt,
1516         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1517         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1518         .clkdm_name     = "l4_per_clkdm",
1519         .parent         = &l4_div_ck,
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 static struct clk gpio3_dbclk = {
1524         .name           = "gpio3_dbclk",
1525         .ops            = &clkops_omap2_dflt,
1526         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1527         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1528         .clkdm_name     = "l4_per_clkdm",
1529         .parent         = &sys_32k_ck,
1530         .recalc         = &followparent_recalc,
1531 };
1532
1533 static struct clk gpio3_ick = {
1534         .name           = "gpio3_ick",
1535         .ops            = &clkops_omap2_dflt,
1536         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1537         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1538         .clkdm_name     = "l4_per_clkdm",
1539         .parent         = &l4_div_ck,
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk gpio4_dbclk = {
1544         .name           = "gpio4_dbclk",
1545         .ops            = &clkops_omap2_dflt,
1546         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1547         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1548         .clkdm_name     = "l4_per_clkdm",
1549         .parent         = &sys_32k_ck,
1550         .recalc         = &followparent_recalc,
1551 };
1552
1553 static struct clk gpio4_ick = {
1554         .name           = "gpio4_ick",
1555         .ops            = &clkops_omap2_dflt,
1556         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1557         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1558         .clkdm_name     = "l4_per_clkdm",
1559         .parent         = &l4_div_ck,
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 static struct clk gpio5_dbclk = {
1564         .name           = "gpio5_dbclk",
1565         .ops            = &clkops_omap2_dflt,
1566         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1567         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1568         .clkdm_name     = "l4_per_clkdm",
1569         .parent         = &sys_32k_ck,
1570         .recalc         = &followparent_recalc,
1571 };
1572
1573 static struct clk gpio5_ick = {
1574         .name           = "gpio5_ick",
1575         .ops            = &clkops_omap2_dflt,
1576         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1577         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1578         .clkdm_name     = "l4_per_clkdm",
1579         .parent         = &l4_div_ck,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk gpio6_dbclk = {
1584         .name           = "gpio6_dbclk",
1585         .ops            = &clkops_omap2_dflt,
1586         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1587         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1588         .clkdm_name     = "l4_per_clkdm",
1589         .parent         = &sys_32k_ck,
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk gpio6_ick = {
1594         .name           = "gpio6_ick",
1595         .ops            = &clkops_omap2_dflt,
1596         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1597         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1598         .clkdm_name     = "l4_per_clkdm",
1599         .parent         = &l4_div_ck,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk gpmc_ick = {
1604         .name           = "gpmc_ick",
1605         .ops            = &clkops_omap2_dflt,
1606         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1607         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1608         .flags          = ENABLE_ON_INIT,
1609         .clkdm_name     = "l3_2_clkdm",
1610         .parent         = &l3_div_ck,
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static const struct clksel sgx_clk_mux_sel[] = {
1615         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1616         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1617         { .parent = NULL },
1618 };
1619
1620 /* Merged sgx_clk_mux into gpu */
1621 static struct clk gpu_fck = {
1622         .name           = "gpu_fck",
1623         .parent         = &dpll_core_m7x2_ck,
1624         .clksel         = sgx_clk_mux_sel,
1625         .init           = &omap2_init_clksel_parent,
1626         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1627         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1628         .ops            = &clkops_omap2_dflt,
1629         .recalc         = &omap2_clksel_recalc,
1630         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1631         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1632         .clkdm_name     = "l3_gfx_clkdm",
1633 };
1634
1635 static struct clk hdq1w_fck = {
1636         .name           = "hdq1w_fck",
1637         .ops            = &clkops_omap2_dflt,
1638         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1639         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .parent         = &func_12m_fclk,
1642         .recalc         = &followparent_recalc,
1643 };
1644
1645 static const struct clksel hsi_fclk_div[] = {
1646         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1647         { .parent = NULL },
1648 };
1649
1650 /* Merged hsi_fclk into hsi */
1651 static struct clk hsi_fck = {
1652         .name           = "hsi_fck",
1653         .parent         = &dpll_per_m2x2_ck,
1654         .clksel         = hsi_fclk_div,
1655         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1656         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1657         .ops            = &clkops_omap2_dflt,
1658         .recalc         = &omap2_clksel_recalc,
1659         .round_rate     = &omap2_clksel_round_rate,
1660         .set_rate       = &omap2_clksel_set_rate,
1661         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1662         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1663         .clkdm_name     = "l3_init_clkdm",
1664 };
1665
1666 static struct clk i2c1_fck = {
1667         .name           = "i2c1_fck",
1668         .ops            = &clkops_omap2_dflt,
1669         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1670         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1671         .clkdm_name     = "l4_per_clkdm",
1672         .parent         = &func_96m_fclk,
1673         .recalc         = &followparent_recalc,
1674 };
1675
1676 static struct clk i2c2_fck = {
1677         .name           = "i2c2_fck",
1678         .ops            = &clkops_omap2_dflt,
1679         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1680         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1681         .clkdm_name     = "l4_per_clkdm",
1682         .parent         = &func_96m_fclk,
1683         .recalc         = &followparent_recalc,
1684 };
1685
1686 static struct clk i2c3_fck = {
1687         .name           = "i2c3_fck",
1688         .ops            = &clkops_omap2_dflt,
1689         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1690         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1691         .clkdm_name     = "l4_per_clkdm",
1692         .parent         = &func_96m_fclk,
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 static struct clk i2c4_fck = {
1697         .name           = "i2c4_fck",
1698         .ops            = &clkops_omap2_dflt,
1699         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1700         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1701         .clkdm_name     = "l4_per_clkdm",
1702         .parent         = &func_96m_fclk,
1703         .recalc         = &followparent_recalc,
1704 };
1705
1706 static struct clk ipu_fck = {
1707         .name           = "ipu_fck",
1708         .ops            = &clkops_omap2_dflt,
1709         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1710         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1711         .clkdm_name     = "ducati_clkdm",
1712         .parent         = &ducati_clk_mux_ck,
1713         .recalc         = &followparent_recalc,
1714 };
1715
1716 static struct clk iss_ctrlclk = {
1717         .name           = "iss_ctrlclk",
1718         .ops            = &clkops_omap2_dflt,
1719         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1720         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1721         .clkdm_name     = "iss_clkdm",
1722         .parent         = &func_96m_fclk,
1723         .recalc         = &followparent_recalc,
1724 };
1725
1726 static struct clk iss_fck = {
1727         .name           = "iss_fck",
1728         .ops            = &clkops_omap2_dflt,
1729         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1730         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1731         .clkdm_name     = "iss_clkdm",
1732         .parent         = &ducati_clk_mux_ck,
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk iva_fck = {
1737         .name           = "iva_fck",
1738         .ops            = &clkops_omap2_dflt,
1739         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1740         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1741         .clkdm_name     = "ivahd_clkdm",
1742         .parent         = &dpll_iva_m5x2_ck,
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk kbd_fck = {
1747         .name           = "kbd_fck",
1748         .ops            = &clkops_omap2_dflt,
1749         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1750         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1751         .clkdm_name     = "l4_wkup_clkdm",
1752         .parent         = &sys_32k_ck,
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 static struct clk l3_instr_ick = {
1757         .name           = "l3_instr_ick",
1758         .ops            = &clkops_omap2_dflt,
1759         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1760         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1761         .flags          = ENABLE_ON_INIT,
1762         .clkdm_name     = "l3_instr_clkdm",
1763         .parent         = &l3_div_ck,
1764         .recalc         = &followparent_recalc,
1765 };
1766
1767 static struct clk l3_main_3_ick = {
1768         .name           = "l3_main_3_ick",
1769         .ops            = &clkops_omap2_dflt,
1770         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1771         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1772         .flags          = ENABLE_ON_INIT,
1773         .clkdm_name     = "l3_instr_clkdm",
1774         .parent         = &l3_div_ck,
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk mcasp_sync_mux_ck = {
1779         .name           = "mcasp_sync_mux_ck",
1780         .parent         = &abe_24m_fclk,
1781         .clksel         = dmic_sync_mux_sel,
1782         .init           = &omap2_init_clksel_parent,
1783         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1784         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1785         .ops            = &clkops_null,
1786         .recalc         = &omap2_clksel_recalc,
1787 };
1788
1789 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1790         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1791         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1792         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1793         { .parent = NULL },
1794 };
1795
1796 /* Merged func_mcasp_abe_gfclk into mcasp */
1797 static struct clk mcasp_fck = {
1798         .name           = "mcasp_fck",
1799         .parent         = &mcasp_sync_mux_ck,
1800         .clksel         = func_mcasp_abe_gfclk_sel,
1801         .init           = &omap2_init_clksel_parent,
1802         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1803         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1804         .ops            = &clkops_omap2_dflt,
1805         .recalc         = &omap2_clksel_recalc,
1806         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1807         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1808         .clkdm_name     = "abe_clkdm",
1809 };
1810
1811 static struct clk mcbsp1_sync_mux_ck = {
1812         .name           = "mcbsp1_sync_mux_ck",
1813         .parent         = &abe_24m_fclk,
1814         .clksel         = dmic_sync_mux_sel,
1815         .init           = &omap2_init_clksel_parent,
1816         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1817         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1818         .ops            = &clkops_null,
1819         .recalc         = &omap2_clksel_recalc,
1820 };
1821
1822 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1823         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1824         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1825         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1826         { .parent = NULL },
1827 };
1828
1829 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1830 static struct clk mcbsp1_fck = {
1831         .name           = "mcbsp1_fck",
1832         .parent         = &mcbsp1_sync_mux_ck,
1833         .clksel         = func_mcbsp1_gfclk_sel,
1834         .init           = &omap2_init_clksel_parent,
1835         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1836         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1837         .ops            = &clkops_omap2_dflt,
1838         .recalc         = &omap2_clksel_recalc,
1839         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1840         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1841         .clkdm_name     = "abe_clkdm",
1842 };
1843
1844 static struct clk mcbsp2_sync_mux_ck = {
1845         .name           = "mcbsp2_sync_mux_ck",
1846         .parent         = &abe_24m_fclk,
1847         .clksel         = dmic_sync_mux_sel,
1848         .init           = &omap2_init_clksel_parent,
1849         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1850         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1851         .ops            = &clkops_null,
1852         .recalc         = &omap2_clksel_recalc,
1853 };
1854
1855 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1856         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1857         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1858         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1859         { .parent = NULL },
1860 };
1861
1862 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1863 static struct clk mcbsp2_fck = {
1864         .name           = "mcbsp2_fck",
1865         .parent         = &mcbsp2_sync_mux_ck,
1866         .clksel         = func_mcbsp2_gfclk_sel,
1867         .init           = &omap2_init_clksel_parent,
1868         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1869         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1870         .ops            = &clkops_omap2_dflt,
1871         .recalc         = &omap2_clksel_recalc,
1872         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1873         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1874         .clkdm_name     = "abe_clkdm",
1875 };
1876
1877 static struct clk mcbsp3_sync_mux_ck = {
1878         .name           = "mcbsp3_sync_mux_ck",
1879         .parent         = &abe_24m_fclk,
1880         .clksel         = dmic_sync_mux_sel,
1881         .init           = &omap2_init_clksel_parent,
1882         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1883         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1884         .ops            = &clkops_null,
1885         .recalc         = &omap2_clksel_recalc,
1886 };
1887
1888 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1889         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1890         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1891         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1892         { .parent = NULL },
1893 };
1894
1895 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1896 static struct clk mcbsp3_fck = {
1897         .name           = "mcbsp3_fck",
1898         .parent         = &mcbsp3_sync_mux_ck,
1899         .clksel         = func_mcbsp3_gfclk_sel,
1900         .init           = &omap2_init_clksel_parent,
1901         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1902         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1903         .ops            = &clkops_omap2_dflt,
1904         .recalc         = &omap2_clksel_recalc,
1905         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1906         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1907         .clkdm_name     = "abe_clkdm",
1908 };
1909
1910 static const struct clksel mcbsp4_sync_mux_sel[] = {
1911         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1912         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1913         { .parent = NULL },
1914 };
1915
1916 static struct clk mcbsp4_sync_mux_ck = {
1917         .name           = "mcbsp4_sync_mux_ck",
1918         .parent         = &func_96m_fclk,
1919         .clksel         = mcbsp4_sync_mux_sel,
1920         .init           = &omap2_init_clksel_parent,
1921         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1922         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1923         .ops            = &clkops_null,
1924         .recalc         = &omap2_clksel_recalc,
1925 };
1926
1927 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1928         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1929         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1930         { .parent = NULL },
1931 };
1932
1933 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1934 static struct clk mcbsp4_fck = {
1935         .name           = "mcbsp4_fck",
1936         .parent         = &mcbsp4_sync_mux_ck,
1937         .clksel         = per_mcbsp4_gfclk_sel,
1938         .init           = &omap2_init_clksel_parent,
1939         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1940         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1941         .ops            = &clkops_omap2_dflt,
1942         .recalc         = &omap2_clksel_recalc,
1943         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1944         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1945         .clkdm_name     = "l4_per_clkdm",
1946 };
1947
1948 static struct clk mcpdm_fck = {
1949         .name           = "mcpdm_fck",
1950         .ops            = &clkops_omap2_dflt,
1951         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1952         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1953         .clkdm_name     = "abe_clkdm",
1954         .parent         = &pad_clks_ck,
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk mcspi1_fck = {
1959         .name           = "mcspi1_fck",
1960         .ops            = &clkops_omap2_dflt,
1961         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1962         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1963         .clkdm_name     = "l4_per_clkdm",
1964         .parent         = &func_48m_fclk,
1965         .recalc         = &followparent_recalc,
1966 };
1967
1968 static struct clk mcspi2_fck = {
1969         .name           = "mcspi2_fck",
1970         .ops            = &clkops_omap2_dflt,
1971         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1972         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1973         .clkdm_name     = "l4_per_clkdm",
1974         .parent         = &func_48m_fclk,
1975         .recalc         = &followparent_recalc,
1976 };
1977
1978 static struct clk mcspi3_fck = {
1979         .name           = "mcspi3_fck",
1980         .ops            = &clkops_omap2_dflt,
1981         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1982         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1983         .clkdm_name     = "l4_per_clkdm",
1984         .parent         = &func_48m_fclk,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk mcspi4_fck = {
1989         .name           = "mcspi4_fck",
1990         .ops            = &clkops_omap2_dflt,
1991         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1992         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1993         .clkdm_name     = "l4_per_clkdm",
1994         .parent         = &func_48m_fclk,
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static const struct clksel hsmmc1_fclk_sel[] = {
1999         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2000         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2001         { .parent = NULL },
2002 };
2003
2004 /* Merged hsmmc1_fclk into mmc1 */
2005 static struct clk mmc1_fck = {
2006         .name           = "mmc1_fck",
2007         .parent         = &func_64m_fclk,
2008         .clksel         = hsmmc1_fclk_sel,
2009         .init           = &omap2_init_clksel_parent,
2010         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2011         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2012         .ops            = &clkops_omap2_dflt,
2013         .recalc         = &omap2_clksel_recalc,
2014         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2015         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2016         .clkdm_name     = "l3_init_clkdm",
2017 };
2018
2019 /* Merged hsmmc2_fclk into mmc2 */
2020 static struct clk mmc2_fck = {
2021         .name           = "mmc2_fck",
2022         .parent         = &func_64m_fclk,
2023         .clksel         = hsmmc1_fclk_sel,
2024         .init           = &omap2_init_clksel_parent,
2025         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2026         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2027         .ops            = &clkops_omap2_dflt,
2028         .recalc         = &omap2_clksel_recalc,
2029         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2030         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2031         .clkdm_name     = "l3_init_clkdm",
2032 };
2033
2034 static struct clk mmc3_fck = {
2035         .name           = "mmc3_fck",
2036         .ops            = &clkops_omap2_dflt,
2037         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2038         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2039         .clkdm_name     = "l4_per_clkdm",
2040         .parent         = &func_48m_fclk,
2041         .recalc         = &followparent_recalc,
2042 };
2043
2044 static struct clk mmc4_fck = {
2045         .name           = "mmc4_fck",
2046         .ops            = &clkops_omap2_dflt,
2047         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2048         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2049         .clkdm_name     = "l4_per_clkdm",
2050         .parent         = &func_48m_fclk,
2051         .recalc         = &followparent_recalc,
2052 };
2053
2054 static struct clk mmc5_fck = {
2055         .name           = "mmc5_fck",
2056         .ops            = &clkops_omap2_dflt,
2057         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2058         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2059         .clkdm_name     = "l4_per_clkdm",
2060         .parent         = &func_48m_fclk,
2061         .recalc         = &followparent_recalc,
2062 };
2063
2064 static struct clk ocp2scp_usb_phy_phy_48m = {
2065         .name           = "ocp2scp_usb_phy_phy_48m",
2066         .ops            = &clkops_omap2_dflt,
2067         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2068         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2069         .clkdm_name     = "l3_init_clkdm",
2070         .parent         = &func_48m_fclk,
2071         .recalc         = &followparent_recalc,
2072 };
2073
2074 static struct clk ocp2scp_usb_phy_ick = {
2075         .name           = "ocp2scp_usb_phy_ick",
2076         .ops            = &clkops_omap2_dflt,
2077         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2078         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2079         .clkdm_name     = "l3_init_clkdm",
2080         .parent         = &l4_div_ck,
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk ocp_wp_noc_ick = {
2085         .name           = "ocp_wp_noc_ick",
2086         .ops            = &clkops_omap2_dflt,
2087         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2088         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2089         .flags          = ENABLE_ON_INIT,
2090         .clkdm_name     = "l3_instr_clkdm",
2091         .parent         = &l3_div_ck,
2092         .recalc         = &followparent_recalc,
2093 };
2094
2095 static struct clk rng_ick = {
2096         .name           = "rng_ick",
2097         .ops            = &clkops_omap2_dflt,
2098         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2099         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2100         .clkdm_name     = "l4_secure_clkdm",
2101         .parent         = &l4_div_ck,
2102         .recalc         = &followparent_recalc,
2103 };
2104
2105 static struct clk sha2md5_fck = {
2106         .name           = "sha2md5_fck",
2107         .ops            = &clkops_omap2_dflt,
2108         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2109         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2110         .clkdm_name     = "l4_secure_clkdm",
2111         .parent         = &l3_div_ck,
2112         .recalc         = &followparent_recalc,
2113 };
2114
2115 static struct clk sl2if_ick = {
2116         .name           = "sl2if_ick",
2117         .ops            = &clkops_omap2_dflt,
2118         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2119         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2120         .clkdm_name     = "ivahd_clkdm",
2121         .parent         = &dpll_iva_m5x2_ck,
2122         .recalc         = &followparent_recalc,
2123 };
2124
2125 static struct clk slimbus1_fclk_1 = {
2126         .name           = "slimbus1_fclk_1",
2127         .ops            = &clkops_omap2_dflt,
2128         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2129         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2130         .clkdm_name     = "abe_clkdm",
2131         .parent         = &func_24m_clk,
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk slimbus1_fclk_0 = {
2136         .name           = "slimbus1_fclk_0",
2137         .ops            = &clkops_omap2_dflt,
2138         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2139         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2140         .clkdm_name     = "abe_clkdm",
2141         .parent         = &abe_24m_fclk,
2142         .recalc         = &followparent_recalc,
2143 };
2144
2145 static struct clk slimbus1_fclk_2 = {
2146         .name           = "slimbus1_fclk_2",
2147         .ops            = &clkops_omap2_dflt,
2148         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2149         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2150         .clkdm_name     = "abe_clkdm",
2151         .parent         = &pad_clks_ck,
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk slimbus1_slimbus_clk = {
2156         .name           = "slimbus1_slimbus_clk",
2157         .ops            = &clkops_omap2_dflt,
2158         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2159         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2160         .clkdm_name     = "abe_clkdm",
2161         .parent         = &slimbus_clk,
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk slimbus1_fck = {
2166         .name           = "slimbus1_fck",
2167         .ops            = &clkops_omap2_dflt,
2168         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2169         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2170         .clkdm_name     = "abe_clkdm",
2171         .parent         = &ocp_abe_iclk,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk slimbus2_fclk_1 = {
2176         .name           = "slimbus2_fclk_1",
2177         .ops            = &clkops_omap2_dflt,
2178         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2179         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2180         .clkdm_name     = "l4_per_clkdm",
2181         .parent         = &per_abe_24m_fclk,
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk slimbus2_fclk_0 = {
2186         .name           = "slimbus2_fclk_0",
2187         .ops            = &clkops_omap2_dflt,
2188         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2189         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2190         .clkdm_name     = "l4_per_clkdm",
2191         .parent         = &func_24mc_fclk,
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk slimbus2_slimbus_clk = {
2196         .name           = "slimbus2_slimbus_clk",
2197         .ops            = &clkops_omap2_dflt,
2198         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2199         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2200         .clkdm_name     = "l4_per_clkdm",
2201         .parent         = &pad_slimbus_core_clks_ck,
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk slimbus2_fck = {
2206         .name           = "slimbus2_fck",
2207         .ops            = &clkops_omap2_dflt,
2208         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2209         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2210         .clkdm_name     = "l4_per_clkdm",
2211         .parent         = &l4_div_ck,
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 static struct clk smartreflex_core_fck = {
2216         .name           = "smartreflex_core_fck",
2217         .ops            = &clkops_omap2_dflt,
2218         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2219         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2220         .clkdm_name     = "l4_ao_clkdm",
2221         .parent         = &l4_wkup_clk_mux_ck,
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk smartreflex_iva_fck = {
2226         .name           = "smartreflex_iva_fck",
2227         .ops            = &clkops_omap2_dflt,
2228         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2229         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2230         .clkdm_name     = "l4_ao_clkdm",
2231         .parent         = &l4_wkup_clk_mux_ck,
2232         .recalc         = &followparent_recalc,
2233 };
2234
2235 static struct clk smartreflex_mpu_fck = {
2236         .name           = "smartreflex_mpu_fck",
2237         .ops            = &clkops_omap2_dflt,
2238         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2239         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2240         .clkdm_name     = "l4_ao_clkdm",
2241         .parent         = &l4_wkup_clk_mux_ck,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 /* Merged dmt1_clk_mux into timer1 */
2246 static struct clk timer1_fck = {
2247         .name           = "timer1_fck",
2248         .parent         = &sys_clkin_ck,
2249         .clksel         = abe_dpll_bypass_clk_mux_sel,
2250         .init           = &omap2_init_clksel_parent,
2251         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2252         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2253         .ops            = &clkops_omap2_dflt,
2254         .recalc         = &omap2_clksel_recalc,
2255         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2256         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2257         .clkdm_name     = "l4_wkup_clkdm",
2258 };
2259
2260 /* Merged cm2_dm10_mux into timer10 */
2261 static struct clk timer10_fck = {
2262         .name           = "timer10_fck",
2263         .parent         = &sys_clkin_ck,
2264         .clksel         = abe_dpll_bypass_clk_mux_sel,
2265         .init           = &omap2_init_clksel_parent,
2266         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2267         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2268         .ops            = &clkops_omap2_dflt,
2269         .recalc         = &omap2_clksel_recalc,
2270         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2271         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2272         .clkdm_name     = "l4_per_clkdm",
2273 };
2274
2275 /* Merged cm2_dm11_mux into timer11 */
2276 static struct clk timer11_fck = {
2277         .name           = "timer11_fck",
2278         .parent         = &sys_clkin_ck,
2279         .clksel         = abe_dpll_bypass_clk_mux_sel,
2280         .init           = &omap2_init_clksel_parent,
2281         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2282         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2283         .ops            = &clkops_omap2_dflt,
2284         .recalc         = &omap2_clksel_recalc,
2285         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2286         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2287         .clkdm_name     = "l4_per_clkdm",
2288 };
2289
2290 /* Merged cm2_dm2_mux into timer2 */
2291 static struct clk timer2_fck = {
2292         .name           = "timer2_fck",
2293         .parent         = &sys_clkin_ck,
2294         .clksel         = abe_dpll_bypass_clk_mux_sel,
2295         .init           = &omap2_init_clksel_parent,
2296         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2297         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2298         .ops            = &clkops_omap2_dflt,
2299         .recalc         = &omap2_clksel_recalc,
2300         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2301         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2302         .clkdm_name     = "l4_per_clkdm",
2303 };
2304
2305 /* Merged cm2_dm3_mux into timer3 */
2306 static struct clk timer3_fck = {
2307         .name           = "timer3_fck",
2308         .parent         = &sys_clkin_ck,
2309         .clksel         = abe_dpll_bypass_clk_mux_sel,
2310         .init           = &omap2_init_clksel_parent,
2311         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2312         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2313         .ops            = &clkops_omap2_dflt,
2314         .recalc         = &omap2_clksel_recalc,
2315         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2316         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2317         .clkdm_name     = "l4_per_clkdm",
2318 };
2319
2320 /* Merged cm2_dm4_mux into timer4 */
2321 static struct clk timer4_fck = {
2322         .name           = "timer4_fck",
2323         .parent         = &sys_clkin_ck,
2324         .clksel         = abe_dpll_bypass_clk_mux_sel,
2325         .init           = &omap2_init_clksel_parent,
2326         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2327         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2328         .ops            = &clkops_omap2_dflt,
2329         .recalc         = &omap2_clksel_recalc,
2330         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2331         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2332         .clkdm_name     = "l4_per_clkdm",
2333 };
2334
2335 static const struct clksel timer5_sync_mux_sel[] = {
2336         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2337         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2338         { .parent = NULL },
2339 };
2340
2341 /* Merged timer5_sync_mux into timer5 */
2342 static struct clk timer5_fck = {
2343         .name           = "timer5_fck",
2344         .parent         = &syc_clk_div_ck,
2345         .clksel         = timer5_sync_mux_sel,
2346         .init           = &omap2_init_clksel_parent,
2347         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2348         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2349         .ops            = &clkops_omap2_dflt,
2350         .recalc         = &omap2_clksel_recalc,
2351         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2352         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2353         .clkdm_name     = "abe_clkdm",
2354 };
2355
2356 /* Merged timer6_sync_mux into timer6 */
2357 static struct clk timer6_fck = {
2358         .name           = "timer6_fck",
2359         .parent         = &syc_clk_div_ck,
2360         .clksel         = timer5_sync_mux_sel,
2361         .init           = &omap2_init_clksel_parent,
2362         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2363         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2364         .ops            = &clkops_omap2_dflt,
2365         .recalc         = &omap2_clksel_recalc,
2366         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2367         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2368         .clkdm_name     = "abe_clkdm",
2369 };
2370
2371 /* Merged timer7_sync_mux into timer7 */
2372 static struct clk timer7_fck = {
2373         .name           = "timer7_fck",
2374         .parent         = &syc_clk_div_ck,
2375         .clksel         = timer5_sync_mux_sel,
2376         .init           = &omap2_init_clksel_parent,
2377         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2378         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2379         .ops            = &clkops_omap2_dflt,
2380         .recalc         = &omap2_clksel_recalc,
2381         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2382         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2383         .clkdm_name     = "abe_clkdm",
2384 };
2385
2386 /* Merged timer8_sync_mux into timer8 */
2387 static struct clk timer8_fck = {
2388         .name           = "timer8_fck",
2389         .parent         = &syc_clk_div_ck,
2390         .clksel         = timer5_sync_mux_sel,
2391         .init           = &omap2_init_clksel_parent,
2392         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2393         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2394         .ops            = &clkops_omap2_dflt,
2395         .recalc         = &omap2_clksel_recalc,
2396         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2397         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2398         .clkdm_name     = "abe_clkdm",
2399 };
2400
2401 /* Merged cm2_dm9_mux into timer9 */
2402 static struct clk timer9_fck = {
2403         .name           = "timer9_fck",
2404         .parent         = &sys_clkin_ck,
2405         .clksel         = abe_dpll_bypass_clk_mux_sel,
2406         .init           = &omap2_init_clksel_parent,
2407         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2408         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2409         .ops            = &clkops_omap2_dflt,
2410         .recalc         = &omap2_clksel_recalc,
2411         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2412         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2413         .clkdm_name     = "l4_per_clkdm",
2414 };
2415
2416 static struct clk uart1_fck = {
2417         .name           = "uart1_fck",
2418         .ops            = &clkops_omap2_dflt,
2419         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2420         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2421         .clkdm_name     = "l4_per_clkdm",
2422         .parent         = &func_48m_fclk,
2423         .recalc         = &followparent_recalc,
2424 };
2425
2426 static struct clk uart2_fck = {
2427         .name           = "uart2_fck",
2428         .ops            = &clkops_omap2_dflt,
2429         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2430         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2431         .clkdm_name     = "l4_per_clkdm",
2432         .parent         = &func_48m_fclk,
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk uart3_fck = {
2437         .name           = "uart3_fck",
2438         .ops            = &clkops_omap2_dflt,
2439         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2440         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2441         .clkdm_name     = "l4_per_clkdm",
2442         .parent         = &func_48m_fclk,
2443         .recalc         = &followparent_recalc,
2444 };
2445
2446 static struct clk uart4_fck = {
2447         .name           = "uart4_fck",
2448         .ops            = &clkops_omap2_dflt,
2449         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2450         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2451         .clkdm_name     = "l4_per_clkdm",
2452         .parent         = &func_48m_fclk,
2453         .recalc         = &followparent_recalc,
2454 };
2455
2456 static struct clk usb_host_fs_fck = {
2457         .name           = "usb_host_fs_fck",
2458         .ops            = &clkops_omap2_dflt,
2459         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2460         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2461         .clkdm_name     = "l3_init_clkdm",
2462         .parent         = &func_48mc_fclk,
2463         .recalc         = &followparent_recalc,
2464 };
2465
2466 static const struct clksel utmi_p1_gfclk_sel[] = {
2467         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2468         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2469         { .parent = NULL },
2470 };
2471
2472 static struct clk utmi_p1_gfclk = {
2473         .name           = "utmi_p1_gfclk",
2474         .parent         = &init_60m_fclk,
2475         .clksel         = utmi_p1_gfclk_sel,
2476         .init           = &omap2_init_clksel_parent,
2477         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2478         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2479         .ops            = &clkops_null,
2480         .recalc         = &omap2_clksel_recalc,
2481 };
2482
2483 static struct clk usb_host_hs_utmi_p1_clk = {
2484         .name           = "usb_host_hs_utmi_p1_clk",
2485         .ops            = &clkops_omap2_dflt,
2486         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2487         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2488         .clkdm_name     = "l3_init_clkdm",
2489         .parent         = &utmi_p1_gfclk,
2490         .recalc         = &followparent_recalc,
2491 };
2492
2493 static const struct clksel utmi_p2_gfclk_sel[] = {
2494         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2495         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2496         { .parent = NULL },
2497 };
2498
2499 static struct clk utmi_p2_gfclk = {
2500         .name           = "utmi_p2_gfclk",
2501         .parent         = &init_60m_fclk,
2502         .clksel         = utmi_p2_gfclk_sel,
2503         .init           = &omap2_init_clksel_parent,
2504         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2505         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2506         .ops            = &clkops_null,
2507         .recalc         = &omap2_clksel_recalc,
2508 };
2509
2510 static struct clk usb_host_hs_utmi_p2_clk = {
2511         .name           = "usb_host_hs_utmi_p2_clk",
2512         .ops            = &clkops_omap2_dflt,
2513         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2514         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2515         .clkdm_name     = "l3_init_clkdm",
2516         .parent         = &utmi_p2_gfclk,
2517         .recalc         = &followparent_recalc,
2518 };
2519
2520 static struct clk usb_host_hs_utmi_p3_clk = {
2521         .name           = "usb_host_hs_utmi_p3_clk",
2522         .ops            = &clkops_omap2_dflt,
2523         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2524         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2525         .clkdm_name     = "l3_init_clkdm",
2526         .parent         = &init_60m_fclk,
2527         .recalc         = &followparent_recalc,
2528 };
2529
2530 static struct clk usb_host_hs_hsic480m_p1_clk = {
2531         .name           = "usb_host_hs_hsic480m_p1_clk",
2532         .ops            = &clkops_omap2_dflt,
2533         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2534         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2535         .clkdm_name     = "l3_init_clkdm",
2536         .parent         = &dpll_usb_m2_ck,
2537         .recalc         = &followparent_recalc,
2538 };
2539
2540 static struct clk usb_host_hs_hsic60m_p1_clk = {
2541         .name           = "usb_host_hs_hsic60m_p1_clk",
2542         .ops            = &clkops_omap2_dflt,
2543         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2544         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2545         .clkdm_name     = "l3_init_clkdm",
2546         .parent         = &init_60m_fclk,
2547         .recalc         = &followparent_recalc,
2548 };
2549
2550 static struct clk usb_host_hs_hsic60m_p2_clk = {
2551         .name           = "usb_host_hs_hsic60m_p2_clk",
2552         .ops            = &clkops_omap2_dflt,
2553         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2554         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2555         .clkdm_name     = "l3_init_clkdm",
2556         .parent         = &init_60m_fclk,
2557         .recalc         = &followparent_recalc,
2558 };
2559
2560 static struct clk usb_host_hs_hsic480m_p2_clk = {
2561         .name           = "usb_host_hs_hsic480m_p2_clk",
2562         .ops            = &clkops_omap2_dflt,
2563         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2564         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2565         .clkdm_name     = "l3_init_clkdm",
2566         .parent         = &dpll_usb_m2_ck,
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static struct clk usb_host_hs_func48mclk = {
2571         .name           = "usb_host_hs_func48mclk",
2572         .ops            = &clkops_omap2_dflt,
2573         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2574         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2575         .clkdm_name     = "l3_init_clkdm",
2576         .parent         = &func_48mc_fclk,
2577         .recalc         = &followparent_recalc,
2578 };
2579
2580 static struct clk usb_host_hs_fck = {
2581         .name           = "usb_host_hs_fck",
2582         .ops            = &clkops_omap2_dflt,
2583         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2584         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2585         .clkdm_name     = "l3_init_clkdm",
2586         .parent         = &init_60m_fclk,
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static const struct clksel otg_60m_gfclk_sel[] = {
2591         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2592         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2593         { .parent = NULL },
2594 };
2595
2596 static struct clk otg_60m_gfclk = {
2597         .name           = "otg_60m_gfclk",
2598         .parent         = &utmi_phy_clkout_ck,
2599         .clksel         = otg_60m_gfclk_sel,
2600         .init           = &omap2_init_clksel_parent,
2601         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2602         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2603         .ops            = &clkops_null,
2604         .recalc         = &omap2_clksel_recalc,
2605 };
2606
2607 static struct clk usb_otg_hs_xclk = {
2608         .name           = "usb_otg_hs_xclk",
2609         .ops            = &clkops_omap2_dflt,
2610         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2611         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2612         .clkdm_name     = "l3_init_clkdm",
2613         .parent         = &otg_60m_gfclk,
2614         .recalc         = &followparent_recalc,
2615 };
2616
2617 static struct clk usb_otg_hs_ick = {
2618         .name           = "usb_otg_hs_ick",
2619         .ops            = &clkops_omap2_dflt,
2620         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2621         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2622         .clkdm_name     = "l3_init_clkdm",
2623         .parent         = &l3_div_ck,
2624         .recalc         = &followparent_recalc,
2625 };
2626
2627 static struct clk usb_phy_cm_clk32k = {
2628         .name           = "usb_phy_cm_clk32k",
2629         .ops            = &clkops_omap2_dflt,
2630         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2631         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2632         .clkdm_name     = "l4_ao_clkdm",
2633         .parent         = &sys_32k_ck,
2634         .recalc         = &followparent_recalc,
2635 };
2636
2637 static struct clk usb_tll_hs_usb_ch2_clk = {
2638         .name           = "usb_tll_hs_usb_ch2_clk",
2639         .ops            = &clkops_omap2_dflt,
2640         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2641         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2642         .clkdm_name     = "l3_init_clkdm",
2643         .parent         = &init_60m_fclk,
2644         .recalc         = &followparent_recalc,
2645 };
2646
2647 static struct clk usb_tll_hs_usb_ch0_clk = {
2648         .name           = "usb_tll_hs_usb_ch0_clk",
2649         .ops            = &clkops_omap2_dflt,
2650         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2651         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2652         .clkdm_name     = "l3_init_clkdm",
2653         .parent         = &init_60m_fclk,
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk usb_tll_hs_usb_ch1_clk = {
2658         .name           = "usb_tll_hs_usb_ch1_clk",
2659         .ops            = &clkops_omap2_dflt,
2660         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2661         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2662         .clkdm_name     = "l3_init_clkdm",
2663         .parent         = &init_60m_fclk,
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static struct clk usb_tll_hs_ick = {
2668         .name           = "usb_tll_hs_ick",
2669         .ops            = &clkops_omap2_dflt,
2670         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2671         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2672         .clkdm_name     = "l3_init_clkdm",
2673         .parent         = &l4_div_ck,
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static const struct clksel_rate div2_14to18_rates[] = {
2678         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2679         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2680         { .div = 0 },
2681 };
2682
2683 static const struct clksel usim_fclk_div[] = {
2684         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2685         { .parent = NULL },
2686 };
2687
2688 static struct clk usim_ck = {
2689         .name           = "usim_ck",
2690         .parent         = &dpll_per_m4x2_ck,
2691         .clksel         = usim_fclk_div,
2692         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2693         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2694         .ops            = &clkops_null,
2695         .recalc         = &omap2_clksel_recalc,
2696         .round_rate     = &omap2_clksel_round_rate,
2697         .set_rate       = &omap2_clksel_set_rate,
2698 };
2699
2700 static struct clk usim_fclk = {
2701         .name           = "usim_fclk",
2702         .ops            = &clkops_omap2_dflt,
2703         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2704         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2705         .clkdm_name     = "l4_wkup_clkdm",
2706         .parent         = &usim_ck,
2707         .recalc         = &followparent_recalc,
2708 };
2709
2710 static struct clk usim_fck = {
2711         .name           = "usim_fck",
2712         .ops            = &clkops_omap2_dflt,
2713         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2714         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2715         .clkdm_name     = "l4_wkup_clkdm",
2716         .parent         = &sys_32k_ck,
2717         .recalc         = &followparent_recalc,
2718 };
2719
2720 static struct clk wd_timer2_fck = {
2721         .name           = "wd_timer2_fck",
2722         .ops            = &clkops_omap2_dflt,
2723         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2724         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2725         .clkdm_name     = "l4_wkup_clkdm",
2726         .parent         = &sys_32k_ck,
2727         .recalc         = &followparent_recalc,
2728 };
2729
2730 static struct clk wd_timer3_fck = {
2731         .name           = "wd_timer3_fck",
2732         .ops            = &clkops_omap2_dflt,
2733         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2734         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2735         .clkdm_name     = "abe_clkdm",
2736         .parent         = &sys_32k_ck,
2737         .recalc         = &followparent_recalc,
2738 };
2739
2740 /* Remaining optional clocks */
2741 static const struct clksel stm_clk_div_div[] = {
2742         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2743         { .parent = NULL },
2744 };
2745
2746 static struct clk stm_clk_div_ck = {
2747         .name           = "stm_clk_div_ck",
2748         .parent         = &pmd_stm_clock_mux_ck,
2749         .clksel         = stm_clk_div_div,
2750         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2751         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2752         .ops            = &clkops_null,
2753         .recalc         = &omap2_clksel_recalc,
2754         .round_rate     = &omap2_clksel_round_rate,
2755         .set_rate       = &omap2_clksel_set_rate,
2756 };
2757
2758 static const struct clksel trace_clk_div_div[] = {
2759         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2760         { .parent = NULL },
2761 };
2762
2763 static struct clk trace_clk_div_ck = {
2764         .name           = "trace_clk_div_ck",
2765         .parent         = &pmd_trace_clk_mux_ck,
2766         .clksel         = trace_clk_div_div,
2767         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2768         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2769         .ops            = &clkops_null,
2770         .recalc         = &omap2_clksel_recalc,
2771         .round_rate     = &omap2_clksel_round_rate,
2772         .set_rate       = &omap2_clksel_set_rate,
2773 };
2774
2775 /* SCRM aux clk nodes */
2776
2777 static const struct clksel auxclk_sel[] = {
2778         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2779         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2780         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2781         { .parent = NULL },
2782 };
2783
2784 static struct clk auxclk0_ck = {
2785         .name           = "auxclk0_ck",
2786         .parent         = &sys_clkin_ck,
2787         .init           = &omap2_init_clksel_parent,
2788         .ops            = &clkops_omap2_dflt,
2789         .clksel         = auxclk_sel,
2790         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2791         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2792         .recalc         = &omap2_clksel_recalc,
2793         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2794         .enable_bit     = OMAP4_ENABLE_SHIFT,
2795 };
2796
2797 static struct clk auxclk1_ck = {
2798         .name           = "auxclk1_ck",
2799         .parent         = &sys_clkin_ck,
2800         .init           = &omap2_init_clksel_parent,
2801         .ops            = &clkops_omap2_dflt,
2802         .clksel         = auxclk_sel,
2803         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2804         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2805         .recalc         = &omap2_clksel_recalc,
2806         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2807         .enable_bit     = OMAP4_ENABLE_SHIFT,
2808 };
2809
2810 static struct clk auxclk2_ck = {
2811         .name           = "auxclk2_ck",
2812         .parent         = &sys_clkin_ck,
2813         .init           = &omap2_init_clksel_parent,
2814         .ops            = &clkops_omap2_dflt,
2815         .clksel         = auxclk_sel,
2816         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2817         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2818         .recalc         = &omap2_clksel_recalc,
2819         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2820         .enable_bit     = OMAP4_ENABLE_SHIFT,
2821 };
2822
2823 static struct clk auxclk3_ck = {
2824         .name           = "auxclk3_ck",
2825         .parent         = &sys_clkin_ck,
2826         .init           = &omap2_init_clksel_parent,
2827         .ops            = &clkops_omap2_dflt,
2828         .clksel         = auxclk_sel,
2829         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2830         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2831         .recalc         = &omap2_clksel_recalc,
2832         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2833         .enable_bit     = OMAP4_ENABLE_SHIFT,
2834 };
2835
2836 static struct clk auxclk4_ck = {
2837         .name           = "auxclk4_ck",
2838         .parent         = &sys_clkin_ck,
2839         .init           = &omap2_init_clksel_parent,
2840         .ops            = &clkops_omap2_dflt,
2841         .clksel         = auxclk_sel,
2842         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2843         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2844         .recalc         = &omap2_clksel_recalc,
2845         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2846         .enable_bit     = OMAP4_ENABLE_SHIFT,
2847 };
2848
2849 static struct clk auxclk5_ck = {
2850         .name           = "auxclk5_ck",
2851         .parent         = &sys_clkin_ck,
2852         .init           = &omap2_init_clksel_parent,
2853         .ops            = &clkops_omap2_dflt,
2854         .clksel         = auxclk_sel,
2855         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2856         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2857         .recalc         = &omap2_clksel_recalc,
2858         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2859         .enable_bit     = OMAP4_ENABLE_SHIFT,
2860 };
2861
2862 static const struct clksel auxclkreq_sel[] = {
2863         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2864         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2865         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2866         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2867         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2868         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2869         { .parent = NULL },
2870 };
2871
2872 static struct clk auxclkreq0_ck = {
2873         .name           = "auxclkreq0_ck",
2874         .parent         = &auxclk0_ck,
2875         .init           = &omap2_init_clksel_parent,
2876         .ops            = &clkops_null,
2877         .clksel         = auxclkreq_sel,
2878         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2879         .clksel_mask    = OMAP4_MAPPING_MASK,
2880         .recalc         = &omap2_clksel_recalc,
2881 };
2882
2883 static struct clk auxclkreq1_ck = {
2884         .name           = "auxclkreq1_ck",
2885         .parent         = &auxclk1_ck,
2886         .init           = &omap2_init_clksel_parent,
2887         .ops            = &clkops_null,
2888         .clksel         = auxclkreq_sel,
2889         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2890         .clksel_mask    = OMAP4_MAPPING_MASK,
2891         .recalc         = &omap2_clksel_recalc,
2892 };
2893
2894 static struct clk auxclkreq2_ck = {
2895         .name           = "auxclkreq2_ck",
2896         .parent         = &auxclk2_ck,
2897         .init           = &omap2_init_clksel_parent,
2898         .ops            = &clkops_null,
2899         .clksel         = auxclkreq_sel,
2900         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
2901         .clksel_mask    = OMAP4_MAPPING_MASK,
2902         .recalc         = &omap2_clksel_recalc,
2903 };
2904
2905 static struct clk auxclkreq3_ck = {
2906         .name           = "auxclkreq3_ck",
2907         .parent         = &auxclk3_ck,
2908         .init           = &omap2_init_clksel_parent,
2909         .ops            = &clkops_null,
2910         .clksel         = auxclkreq_sel,
2911         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
2912         .clksel_mask    = OMAP4_MAPPING_MASK,
2913         .recalc         = &omap2_clksel_recalc,
2914 };
2915
2916 static struct clk auxclkreq4_ck = {
2917         .name           = "auxclkreq4_ck",
2918         .parent         = &auxclk4_ck,
2919         .init           = &omap2_init_clksel_parent,
2920         .ops            = &clkops_null,
2921         .clksel         = auxclkreq_sel,
2922         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
2923         .clksel_mask    = OMAP4_MAPPING_MASK,
2924         .recalc         = &omap2_clksel_recalc,
2925 };
2926
2927 static struct clk auxclkreq5_ck = {
2928         .name           = "auxclkreq5_ck",
2929         .parent         = &auxclk5_ck,
2930         .init           = &omap2_init_clksel_parent,
2931         .ops            = &clkops_null,
2932         .clksel         = auxclkreq_sel,
2933         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
2934         .clksel_mask    = OMAP4_MAPPING_MASK,
2935         .recalc         = &omap2_clksel_recalc,
2936 };
2937
2938 /*
2939  * clkdev
2940  */
2941
2942 static struct omap_clk omap44xx_clks[] = {
2943         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
2944         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
2945         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
2946         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
2947         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
2948         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
2949         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
2950         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
2951         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
2952         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
2953         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
2954         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
2955         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
2956         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
2957         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
2958         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
2959         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
2960         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
2961         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
2962         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
2963         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
2964         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
2965         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
2966         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
2967         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
2968         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
2969         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
2970         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
2971         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
2972         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
2973         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
2974         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
2975         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
2976         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
2977         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
2978         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
2979         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
2980         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
2981         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
2982         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
2983         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
2984         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
2985         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
2986         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
2987         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
2988         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
2989         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
2990         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
2991         CLK(