arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  53 #define DPLL_LOW_POWER_STOP             0x1
  54 #define DPLL_LOW_POWER_BYPASS           0x5
  55 #define DPLL_LOCKED                     0x7
  56
  57 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  58         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  59
  60 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  61         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  62
  63 #define OMAP3430_PRM_CLKSEL                                             \
  64         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  65
  66 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  67         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  68
  69 /* PRM CLOCKS */
  70
  71 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  72 static struct clk omap_32k_fck = {
  73         .name           = "omap_32k_fck",
  74         .rate           = 32768,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .clkdm          = { .name = "prm_clkdm" },
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk secure_32k_fck = {
  82         .name           = "secure_32k_fck",
  83         .rate           = 32768,
  84         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  85                                 ALWAYS_ENABLED,
  86         .clkdm          = { .name = "prm_clkdm" },
  87         .recalc         = &propagate_rate,
  88 };
  89
  90 /* Virtual source clocks for osc_sys_ck */
  91 static struct clk virt_12m_ck = {
  92         .name           = "virt_12m_ck",
  93         .rate           = 12000000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .clkdm          = { .name = "prm_clkdm" },
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_13m_ck = {
 101         .name           = "virt_13m_ck",
 102         .rate           = 13000000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .clkdm          = { .name = "prm_clkdm" },
 106         .recalc         = &propagate_rate,
 107 };
 108
 109 static struct clk virt_16_8m_ck = {
 110         .name           = "virt_16_8m_ck",
 111         .rate           = 16800000,
 112         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 113                                 ALWAYS_ENABLED,
 114         .clkdm          = { .name = "prm_clkdm" },
 115         .recalc         = &propagate_rate,
 116 };
 117
 118 static struct clk virt_19_2m_ck = {
 119         .name           = "virt_19_2m_ck",
 120         .rate           = 19200000,
 121         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 122                                 ALWAYS_ENABLED,
 123         .clkdm          = { .name = "prm_clkdm" },
 124         .recalc         = &propagate_rate,
 125 };
 126
 127 static struct clk virt_26m_ck = {
 128         .name           = "virt_26m_ck",
 129         .rate           = 26000000,
 130         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 131                                 ALWAYS_ENABLED,
 132         .clkdm          = { .name = "prm_clkdm" },
 133         .recalc         = &propagate_rate,
 134 };
 135
 136 static struct clk virt_38_4m_ck = {
 137         .name           = "virt_38_4m_ck",
 138         .rate           = 38400000,
 139         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 140                                 ALWAYS_ENABLED,
 141         .clkdm          = { .name = "prm_clkdm" },
 142         .recalc         = &propagate_rate,
 143 };
 144
 145 static const struct clksel_rate osc_sys_12m_rates[] = {
 146         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 147         { .div = 0 }
 148 };
 149
 150 static const struct clksel_rate osc_sys_13m_rates[] = {
 151         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 152         { .div = 0 }
 153 };
 154
 155 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 161         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 162         { .div = 0 }
 163 };
 164
 165 static const struct clksel_rate osc_sys_26m_rates[] = {
 166         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 167         { .div = 0 }
 168 };
 169
 170 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 171         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel osc_sys_clksel[] = {
 176         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 177         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 178         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 179         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 180         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 181         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 182         { .parent = NULL },
 183 };
 184
 185 /* Oscillator clock */
 186 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 187 static struct clk osc_sys_ck = {
 188         .name           = "osc_sys_ck",
 189         .init           = &omap2_init_clksel_parent,
 190         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 191         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 192         .clksel         = osc_sys_clksel,
 193         /* REVISIT: deal with autoextclkmode? */
 194         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 195                                 ALWAYS_ENABLED,
 196         .clkdm          = { .name = "prm_clkdm" },
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static const struct clksel_rate div2_rates[] = {
 201         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 202         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 203         { .div = 0 }
 204 };
 205
 206 static const struct clksel sys_clksel[] = {
 207         { .parent = &osc_sys_ck, .rates = div2_rates },
 208         { .parent = NULL }
 209 };
 210
 211 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 212 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 213 static struct clk sys_ck = {
 214         .name           = "sys_ck",
 215         .parent         = &osc_sys_ck,
 216         .init           = &omap2_init_clksel_parent,
 217         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 218         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 219         .clksel         = sys_clksel,
 220         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 221         .clkdm          = { .name = "prm_clkdm" },
 222         .recalc         = &omap2_clksel_recalc,
 223 };
 224
 225 static struct clk sys_altclk = {
 226         .name           = "sys_altclk",
 227         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 228         .clkdm          = { .name = "cm_clkdm" },
 229         .recalc         = &propagate_rate,
 230 };
 231
 232 /*
 233  * Optional external clock input for some McBSPs
 234  * Apparently this is not really in prm_clkdm, but rather is fed into
 235  * both CORE and PER separately.
 236  */
 237 static struct clk mcbsp_clks = {
 238         .name           = "mcbsp_clks",
 239         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 240         .clkdm          = { .name = "prm_clkdm" },
 241         .recalc         = &propagate_rate,
 242 };
 243
 244 /* PRM EXTERNAL CLOCK OUTPUT */
 245
 246 static struct clk sys_clkout1 = {
 247         .name           = "sys_clkout1",
 248         .parent         = &osc_sys_ck,
 249         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 250         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 251         .flags          = CLOCK_IN_OMAP343X,
 252         .clkdm          = { .name = "prm_clkdm" },
 253         .recalc         = &followparent_recalc,
 254 };
 255
 256 /* DPLLS */
 257
 258 /* CM CLOCKS */
 259
 260 static const struct clksel_rate dpll_bypass_rates[] = {
 261         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 262         { .div = 0 }
 263 };
 264
 265 static const struct clksel_rate dpll_locked_rates[] = {
 266         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 267         { .div = 0 }
 268 };
 269
 270 static const struct clksel_rate div16_dpll_rates[] = {
 271         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 272         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 273         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 274         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 275         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 276         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 277         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 278         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 279         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 280         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 281         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 282         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 283         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 284         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 285         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 286         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 287         { .div = 0 }
 288 };
 289
 290 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 291         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 292
 293 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 294         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 295
 296 /* DPLL1 */
 297 /* MPU clock source */
 298 /* Type: DPLL */
 299 static struct dpll_data dpll1_dd = {
 300         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 301         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 302         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 303         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 304         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 305         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 306         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 307         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 308         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 309         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 310         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 311         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 312         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 313         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 314         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 315         .max_divider    = OMAP3_MAX_DPLL_DIV,
 316         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 317 };
 318
 319 static struct clk dpll1_ck = {
 320         .name           = "dpll1_ck",
 321         .parent         = &sys_ck,
 322         .dpll_data      = &dpll1_dd,
 323         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 324         .round_rate     = &omap2_dpll_round_rate,
 325         .set_rate       = &omap3_noncore_dpll_set_rate,
 326         .clkdm          = { .name = "dpll1_clkdm" },
 327         .recalc         = &omap3_dpll_recalc,
 328 };
 329
 330 /*
 331  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 332  * DPLL isn't bypassed.
 333  */
 334 static struct clk dpll1_x2_ck = {
 335         .name           = "dpll1_x2_ck",
 336         .parent         = &dpll1_ck,
 337         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 338                                 PARENT_CONTROLS_CLOCK,
 339         .clkdm          = { .name = "dpll1_clkdm" },
 340         .recalc         = &omap3_clkoutx2_recalc,
 341 };
 342
 343 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 344 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 345         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 346         { .parent = NULL }
 347 };
 348
 349 /*
 350  * Does not exist in the TRM - needed to separate the M2 divider from
 351  * bypass selection in mpu_ck
 352  */
 353 static struct clk dpll1_x2m2_ck = {
 354         .name           = "dpll1_x2m2_ck",
 355         .parent         = &dpll1_x2_ck,
 356         .init           = &omap2_init_clksel_parent,
 357         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 358         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 359         .clksel         = div16_dpll1_x2m2_clksel,
 360         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 361                                 PARENT_CONTROLS_CLOCK,
 362         .clkdm          = { .name = "dpll1_clkdm" },
 363         .recalc         = &omap2_clksel_recalc,
 364 };
 365
 366 /* DPLL2 */
 367 /* IVA2 clock source */
 368 /* Type: DPLL */
 369
 370 static struct dpll_data dpll2_dd = {
 371         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 372         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 373         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 374         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 375         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 376         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 377         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 378                                 (1 << DPLL_LOW_POWER_BYPASS),
 379         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 380         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 381         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 382         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 383         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 384         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 385         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 386         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 387         .max_divider    = OMAP3_MAX_DPLL_DIV,
 388         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 389 };
 390
 391 static struct clk dpll2_ck = {
 392         .name           = "dpll2_ck",
 393         .parent         = &sys_ck,
 394         .dpll_data      = &dpll2_dd,
 395         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 396         .enable         = &omap3_noncore_dpll_enable,
 397         .disable        = &omap3_noncore_dpll_disable,
 398         .round_rate     = &omap2_dpll_round_rate,
 399         .set_rate       = &omap3_noncore_dpll_set_rate,
 400         .clkdm          = { .name = "dpll2_clkdm" },
 401         .recalc         = &omap3_dpll_recalc,
 402 };
 403
 404 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 405         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 406         { .parent = NULL }
 407 };
 408
 409 /*
 410  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 411  * or CLKOUTX2. CLKOUT seems most plausible.
 412  */
 413 static struct clk dpll2_m2_ck = {
 414         .name           = "dpll2_m2_ck",
 415         .parent         = &dpll2_ck,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 418                                           OMAP3430_CM_CLKSEL2_PLL),
 419         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 420         .clksel         = div16_dpll2_m2x2_clksel,
 421         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 422                                 PARENT_CONTROLS_CLOCK,
 423         .clkdm          = { .name = "dpll2_clkdm" },
 424         .recalc         = &omap2_clksel_recalc,
 425 };
 426
 427 /*
 428  * DPLL3
 429  * Source clock for all interfaces and for some device fclks
 430  * REVISIT: Also supports fast relock bypass - not included below
 431  */
 432 static struct dpll_data dpll3_dd = {
 433         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 434         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 435         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 436         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 437         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 438         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 439         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 440         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 441         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 442         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 443         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 444         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 445         .max_divider    = OMAP3_MAX_DPLL_DIV,
 446         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 447 };
 448
 449 static struct clk dpll3_ck = {
 450         .name           = "dpll3_ck",
 451         .parent         = &sys_ck,
 452         .dpll_data      = &dpll3_dd,
 453         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 454         .round_rate     = &omap2_dpll_round_rate,
 455         .clkdm          = { .name = "dpll3_clkdm" },
 456         .recalc         = &omap3_dpll_recalc,
 457 };
 458
 459 /*
 460  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 461  * DPLL isn't bypassed
 462  */
 463 static struct clk dpll3_x2_ck = {
 464         .name           = "dpll3_x2_ck",
 465         .parent         = &dpll3_ck,
 466         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 467                                 PARENT_CONTROLS_CLOCK,
 468         .clkdm          = { .name = "dpll3_clkdm" },
 469         .recalc         = &omap3_clkoutx2_recalc,
 470 };
 471
 472 static const struct clksel_rate div31_dpll3_rates[] = {
 473         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 474         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 475         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 476         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 477         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 478         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 479         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 480         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 481         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 482         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 483         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 484         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 485         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 486         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 487         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 488         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 489         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 490         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 491         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 492         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 493         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 494         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 495         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 496         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 497         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 498         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 499         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 500         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 501         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 502         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 503         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 504         { .div = 0 },
 505 };
 506
 507 static const struct clksel div31_dpll3m2_clksel[] = {
 508         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 509         { .parent = NULL }
 510 };
 511
 512 /* DPLL3 output M2 - primary control point for CORE speed */
 513 static struct clk dpll3_m2_ck = {
 514         .name           = "dpll3_m2_ck",
 515         .parent         = &dpll3_ck,
 516         .init           = &omap2_init_clksel_parent,
 517         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 518         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 519         .clksel         = div31_dpll3m2_clksel,
 520         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 521                                 PARENT_CONTROLS_CLOCK,
 522         .clkdm          = { .name = "dpll3_clkdm" },
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap3_core_dpll_m2_set_rate,
 525         .recalc         = &omap2_clksel_recalc,
 526 };
 527
 528 static const struct clksel core_ck_clksel[] = {
 529         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 530         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 531         { .parent = NULL }
 532 };
 533
 534 static struct clk core_ck = {
 535         .name           = "core_ck",
 536         .init           = &omap2_init_clksel_parent,
 537         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 538         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 539         .clksel         = core_ck_clksel,
 540         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 541                                 PARENT_CONTROLS_CLOCK,
 542         .clkdm          = { .name = "cm_clkdm" },
 543         .recalc         = &omap2_clksel_recalc,
 544 };
 545
 546 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 547         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 548         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 549         { .parent = NULL }
 550 };
 551
 552 static struct clk dpll3_m2x2_ck = {
 553         .name           = "dpll3_m2x2_ck",
 554         .init           = &omap2_init_clksel_parent,
 555         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 556         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 557         .clksel         = dpll3_m2x2_ck_clksel,
 558         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 559                                 PARENT_CONTROLS_CLOCK,
 560         .clkdm          = { .name = "dpll3_clkdm" },
 561         .recalc         = &omap2_clksel_recalc,
 562 };
 563
 564 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 565 static const struct clksel div16_dpll3_clksel[] = {
 566         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 567         { .parent = NULL }
 568 };
 569
 570 /* This virtual clock is the source for dpll3_m3x2_ck */
 571 static struct clk dpll3_m3_ck = {
 572         .name           = "dpll3_m3_ck",
 573         .parent         = &dpll3_ck,
 574         .init           = &omap2_init_clksel_parent,
 575         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 576         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 577         .clksel         = div16_dpll3_clksel,
 578         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 579                                 PARENT_CONTROLS_CLOCK,
 580         .clkdm          = { .name = "dpll3_clkdm" },
 581         .recalc         = &omap2_clksel_recalc,
 582 };
 583
 584 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 585 static struct clk dpll3_m3x2_ck = {
 586         .name           = "dpll3_m3x2_ck",
 587         .parent         = &dpll3_m3_ck,
 588         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 589         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 590         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 591         .clkdm          = { .name = "dpll3_clkdm" },
 592         .recalc         = &omap3_clkoutx2_recalc,
 593 };
 594
 595 static const struct clksel emu_core_alwon_ck_clksel[] = {
 596         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 597         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 598         { .parent = NULL }
 599 };
 600
 601 static struct clk emu_core_alwon_ck = {
 602         .name           = "emu_core_alwon_ck",
 603         .parent         = &dpll3_m3x2_ck,
 604         .init           = &omap2_init_clksel_parent,
 605         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 606         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 607         .clksel         = emu_core_alwon_ck_clksel,
 608         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 609                                 PARENT_CONTROLS_CLOCK,
 610         .clkdm          = { .name = "dpll3_clkdm" },
 611         .recalc         = &omap2_clksel_recalc,
 612 };
 613
 614 /* DPLL4 */
 615 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 616 /* Type: DPLL */
 617 static struct dpll_data dpll4_dd = {
 618         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 619         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 620         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 621         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 622         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 623         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 624         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 625         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 626         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 627         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 628         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 629         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 630         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 631         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 632         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 633         .max_divider    = OMAP3_MAX_DPLL_DIV,
 634         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 635 };
 636
 637 static struct clk dpll4_ck = {
 638         .name           = "dpll4_ck",
 639         .parent         = &sys_ck,
 640         .dpll_data      = &dpll4_dd,
 641         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 642         .enable         = &omap3_noncore_dpll_enable,
 643         .disable        = &omap3_noncore_dpll_disable,
 644         .round_rate     = &omap2_dpll_round_rate,
 645         .set_rate       = &omap3_noncore_dpll_set_rate,
 646         .clkdm          = { .name = "dpll4_clkdm" },
 647         .recalc         = &omap3_dpll_recalc,
 648 };
 649
 650 /*
 651  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 652  * DPLL isn't bypassed --
 653  * XXX does this serve any downstream clocks?
 654  */
 655 static struct clk dpll4_x2_ck = {
 656         .name           = "dpll4_x2_ck",
 657         .parent         = &dpll4_ck,
 658         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 659                                 PARENT_CONTROLS_CLOCK,
 660         .clkdm          = { .name = "dpll4_clkdm" },
 661         .recalc         = &omap3_clkoutx2_recalc,
 662 };
 663
 664 static const struct clksel div16_dpll4_clksel[] = {
 665         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 666         { .parent = NULL }
 667 };
 668
 669 /* This virtual clock is the source for dpll4_m2x2_ck */
 670 static struct clk dpll4_m2_ck = {
 671         .name           = "dpll4_m2_ck",
 672         .parent         = &dpll4_ck,
 673         .init           = &omap2_init_clksel_parent,
 674         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 675         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 676         .clksel         = div16_dpll4_clksel,
 677         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 678                                 PARENT_CONTROLS_CLOCK,
 679         .clkdm          = { .name = "dpll4_clkdm" },
 680         .recalc         = &omap2_clksel_recalc,
 681 };
 682
 683 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 684 static struct clk dpll4_m2x2_ck = {
 685         .name           = "dpll4_m2x2_ck",
 686         .parent         = &dpll4_m2_ck,
 687         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 688         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 689         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 690         .clkdm          = { .name = "dpll4_clkdm" },
 691         .recalc         = &omap3_clkoutx2_recalc,
 692 };
 693
 694 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 695         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 696         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 697         { .parent = NULL }
 698 };
 699
 700 /*
 701  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 702  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 703  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 704  * CM_96K_(F)CLK.
 705  */
 706 static struct clk omap_96m_alwon_fck = {
 707         .name           = "omap_96m_alwon_fck",
 708         .parent         = &dpll4_m2x2_ck,
 709         .init           = &omap2_init_clksel_parent,
 710         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 711         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 712         .clksel         = omap_96m_alwon_fck_clksel,
 713         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 714                                 PARENT_CONTROLS_CLOCK,
 715         .clkdm          = { .name = "prm_clkdm" },
 716         .recalc         = &omap2_clksel_recalc,
 717 };
 718
 719 static struct clk cm_96m_fck = {
 720         .name           = "cm_96m_fck",
 721         .parent         = &omap_96m_alwon_fck,
 722         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 723                                 PARENT_CONTROLS_CLOCK,
 724         .clkdm          = { .name = "cm_clkdm" },
 725         .recalc         = &followparent_recalc,
 726 };
 727
 728 static const struct clksel_rate omap_96m_dpll_rates[] = {
 729         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 730         { .div = 0 }
 731 };
 732
 733 static const struct clksel_rate omap_96m_sys_rates[] = {
 734         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 735         { .div = 0 }
 736 };
 737
 738 static const struct clksel omap_96m_fck_clksel[] = {
 739         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 740         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 741         { .parent = NULL }
 742 };
 743
 744 static struct clk omap_96m_fck = {
 745         .name           = "omap_96m_fck",
 746         .parent         = &sys_ck,
 747         .init           = &omap2_init_clksel_parent,
 748         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 749         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 750         .clksel         = omap_96m_fck_clksel,
 751         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 752                                 PARENT_CONTROLS_CLOCK,
 753         .clkdm          = { .name = "cm_clkdm" },
 754         .recalc         = &omap2_clksel_recalc,
 755 };
 756
 757 /* This virtual clock is the source for dpll4_m3x2_ck */
 758 static struct clk dpll4_m3_ck = {
 759         .name           = "dpll4_m3_ck",
 760         .parent         = &dpll4_ck,
 761         .init           = &omap2_init_clksel_parent,
 762         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 763         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 764         .clksel         = div16_dpll4_clksel,
 765         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 766                                 PARENT_CONTROLS_CLOCK,
 767         .clkdm          = { .name = "dpll4_clkdm" },
 768         .recalc         = &omap2_clksel_recalc,
 769 };
 770
 771 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 772 static struct clk dpll4_m3x2_ck = {
 773         .name           = "dpll4_m3x2_ck",
 774         .parent         = &dpll4_m3_ck,
 775         .init           = &omap2_init_clksel_parent,
 776         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 777         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 778         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 779         .clkdm          = { .name = "dpll4_clkdm" },
 780         .recalc         = &omap3_clkoutx2_recalc,
 781 };
 782
 783 static const struct clksel virt_omap_54m_fck_clksel[] = {
 784         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 785         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 786         { .parent = NULL }
 787 };
 788
 789 static struct clk virt_omap_54m_fck = {
 790         .name           = "virt_omap_54m_fck",
 791         .parent         = &dpll4_m3x2_ck,
 792         .init           = &omap2_init_clksel_parent,
 793         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 794         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 795         .clksel         = virt_omap_54m_fck_clksel,
 796         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 797                                 PARENT_CONTROLS_CLOCK,
 798         .clkdm          = { .name = "dpll4_clkdm" },
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 803         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 804         { .div = 0 }
 805 };
 806
 807 static const struct clksel_rate omap_54m_alt_rates[] = {
 808         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 809         { .div = 0 }
 810 };
 811
 812 static const struct clksel omap_54m_clksel[] = {
 813         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 814         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 815         { .parent = NULL }
 816 };
 817
 818 static struct clk omap_54m_fck = {
 819         .name           = "omap_54m_fck",
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 822         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 823         .clksel         = omap_54m_clksel,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .clkdm          = { .name = "cm_clkdm" },
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 831         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 832         { .div = 0 }
 833 };
 834
 835 static const struct clksel_rate omap_48m_alt_rates[] = {
 836         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 837         { .div = 0 }
 838 };
 839
 840 static const struct clksel omap_48m_clksel[] = {
 841         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 842         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 843         { .parent = NULL }
 844 };
 845
 846 static struct clk omap_48m_fck = {
 847         .name           = "omap_48m_fck",
 848         .init           = &omap2_init_clksel_parent,
 849         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 850         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 851         .clksel         = omap_48m_clksel,
 852         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 853                                 PARENT_CONTROLS_CLOCK,
 854         .clkdm          = { .name = "cm_clkdm" },
 855         .recalc         = &omap2_clksel_recalc,
 856 };
 857
 858 static struct clk omap_12m_fck = {
 859         .name           = "omap_12m_fck",
 860         .parent         = &omap_48m_fck,
 861         .fixed_div      = 4,
 862         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 863                                 PARENT_CONTROLS_CLOCK,
 864         .clkdm          = { .name = "cm_clkdm" },
 865         .recalc         = &omap2_fixed_divisor_recalc,
 866 };
 867
 868 /* This virstual clock is the source for dpll4_m4x2_ck */
 869 static struct clk dpll4_m4_ck = {
 870         .name           = "dpll4_m4_ck",
 871         .parent         = &dpll4_ck,
 872         .init           = &omap2_init_clksel_parent,
 873         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 874         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 875         .clksel         = div16_dpll4_clksel,
 876         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 877                                 PARENT_CONTROLS_CLOCK,
 878         .clkdm          = { .name = "dpll4_clkdm" },
 879         .recalc         = &omap2_clksel_recalc,
 880 };
 881
 882 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 883 static struct clk dpll4_m4x2_ck = {
 884         .name           = "dpll4_m4x2_ck",
 885         .parent         = &dpll4_m4_ck,
 886         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 887         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 888         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 889         .clkdm          = { .name = "dpll4_clkdm" },
 890         .recalc         = &omap3_clkoutx2_recalc,
 891 };
 892
 893 /* This virtual clock is the source for dpll4_m5x2_ck */
 894 static struct clk dpll4_m5_ck = {
 895         .name           = "dpll4_m5_ck",
 896         .parent         = &dpll4_ck,
 897         .init           = &omap2_init_clksel_parent,
 898         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 899         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 900         .clksel         = div16_dpll4_clksel,
 901         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 902                                 PARENT_CONTROLS_CLOCK,
 903         .clkdm          = { .name = "dpll4_clkdm" },
 904         .recalc         = &omap2_clksel_recalc,
 905 };
 906
 907 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 908 static struct clk dpll4_m5x2_ck = {
 909         .name           = "dpll4_m5x2_ck",
 910         .parent         = &dpll4_m5_ck,
 911         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 912         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 913         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 914         .clkdm          = { .name = "dpll4_clkdm" },
 915         .recalc         = &omap3_clkoutx2_recalc,
 916 };
 917
 918 /* This virtual clock is the source for dpll4_m6x2_ck */
 919 static struct clk dpll4_m6_ck = {
 920         .name           = "dpll4_m6_ck",
 921         .parent         = &dpll4_ck,
 922         .init           = &omap2_init_clksel_parent,
 923         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 924         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 925         .clksel         = div16_dpll4_clksel,
 926         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 927                                 PARENT_CONTROLS_CLOCK,
 928         .clkdm          = { .name = "dpll4_clkdm" },
 929         .recalc         = &omap2_clksel_recalc,
 930 };
 931
 932 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 933 static struct clk dpll4_m6x2_ck = {
 934         .name           = "dpll4_m6x2_ck",
 935         .parent         = &dpll4_m6_ck,
 936         .init           = &omap2_init_clksel_parent,
 937         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 938         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 939         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 940         .clkdm          = { .name = "dpll4_clkdm" },
 941         .recalc         = &omap3_clkoutx2_recalc,
 942 };
 943
 944 static struct clk emu_per_alwon_ck = {
 945         .name           = "emu_per_alwon_ck",
 946         .parent         = &dpll4_m6x2_ck,
 947         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 948                                 PARENT_CONTROLS_CLOCK,
 949         .clkdm          = { .name = "dpll4_clkdm" },
 950         .recalc         = &followparent_recalc,
 951 };
 952
 953 /* DPLL5 */
 954 /* Supplies 120MHz clock, USIM source clock */
 955 /* Type: DPLL */
 956 /* 3430ES2 only */
 957 static struct dpll_data dpll5_dd = {
 958         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 959         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 960         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 961         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 962         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 963         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 964         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 965         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 966         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 967         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 968         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 969         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 970         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 971         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 972         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 973         .max_divider    = OMAP3_MAX_DPLL_DIV,
 974         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 975 };
 976
 977 static struct clk dpll5_ck = {
 978         .name           = "dpll5_ck",
 979         .parent         = &sys_ck,
 980         .dpll_data      = &dpll5_dd,
 981         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 982         .enable         = &omap3_noncore_dpll_enable,
 983         .disable        = &omap3_noncore_dpll_disable,
 984         .round_rate     = &omap2_dpll_round_rate,
 985         .set_rate       = &omap3_noncore_dpll_set_rate,
 986         .clkdm          = { .name = "dpll5_clkdm" },
 987         .recalc         = &omap3_dpll_recalc,
 988 };
 989
 990 static const struct clksel div16_dpll5_clksel[] = {
 991         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 992         { .parent = NULL }
 993 };
 994
 995 static struct clk dpll5_m2_ck = {
 996         .name           = "dpll5_m2_ck",
 997         .parent         = &dpll5_ck,
 998         .init           = &omap2_init_clksel_parent,
 999         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1000         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
1001         .clksel         = div16_dpll5_clksel,
1002         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1003                                 PARENT_CONTROLS_CLOCK,
1004         .clkdm          = { .name = "dpll5_clkdm" },
1005         .recalc         = &omap2_clksel_recalc,
1006 };
1007
1008 static const struct clksel omap_120m_fck_clksel[] = {
1009         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
1010         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
1011         { .parent = NULL }
1012 };
1013
1014 static struct clk omap_120m_fck = {
1015         .name           = "omap_120m_fck",
1016         .parent         = &dpll5_m2_ck,
1017         .init           = &omap2_init_clksel_parent,
1018         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1019         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1020         .clksel         = omap_120m_fck_clksel,
1021         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1022                                 PARENT_CONTROLS_CLOCK,
1023         .clkdm          = { .name = "dpll5_clkdm" },
1024         .recalc         = &omap2_clksel_recalc,
1025 };
1026
1027 /* CM EXTERNAL CLOCK OUTPUTS */
1028
1029 static const struct clksel_rate clkout2_src_core_rates[] = {
1030         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1031         { .div = 0 }
1032 };
1033
1034 static const struct clksel_rate clkout2_src_sys_rates[] = {
1035         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1036         { .div = 0 }
1037 };
1038
1039 static const struct clksel_rate clkout2_src_96m_rates[] = {
1040         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1041         { .div = 0 }
1042 };
1043
1044 static const struct clksel_rate clkout2_src_54m_rates[] = {
1045         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1046         { .div = 0 }
1047 };
1048
1049 static const struct clksel clkout2_src_clksel[] = {
1050         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1051         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1052         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1053         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1054         { .parent = NULL }
1055 };
1056
1057 static struct clk clkout2_src_ck = {
1058         .name           = "clkout2_src_ck",
1059         .init           = &omap2_init_clksel_parent,
1060         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1061         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1062         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1063         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1064         .clksel         = clkout2_src_clksel,
1065         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1066         .clkdm          = { .name = "cm_clkdm" },
1067         .recalc         = &omap2_clksel_recalc,
1068 };
1069
1070 static const struct clksel_rate sys_clkout2_rates[] = {
1071         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1072         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1073         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1074         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1075         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1076         { .div = 0 },
1077 };
1078
1079 static const struct clksel sys_clkout2_clksel[] = {
1080         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1081         { .parent = NULL },
1082 };
1083
1084 static struct clk sys_clkout2 = {
1085         .name           = "sys_clkout2",
1086         .init           = &omap2_init_clksel_parent,
1087         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1088         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1089         .clksel         = sys_clkout2_clksel,
1090         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1091         .clkdm          = { .name = "cm_clkdm" },
1092         .recalc         = &omap2_clksel_recalc,
1093 };
1094
1095 /* CM OUTPUT CLOCKS */
1096
1097 static struct clk corex2_fck = {
1098         .name           = "corex2_fck",
1099         .parent         = &dpll3_m2x2_ck,
1100         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1101                                 PARENT_CONTROLS_CLOCK,
1102         .clkdm          = { .name = "cm_clkdm" },
1103         .recalc         = &followparent_recalc,
1104 };
1105
1106 /* DPLL power domain clock controls */
1107
1108 static const struct clksel_rate div4_rates[] = {
1109         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1110         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1111         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1112         { .div = 0 }
1113 };
1114
1115 static const struct clksel div4_core_clksel[] = {
1116         { .parent = &core_ck, .rates = div4_rates },
1117         { .parent = NULL }
1118 };
1119
1120 static struct clk dpll1_fck = {
1121         .name           = "dpll1_fck",
1122         .parent         = &core_ck,
1123         .init           = &omap2_init_clksel_parent,
1124         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1125         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1126         .clksel         = div4_core_clksel,
1127         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1128                                 PARENT_CONTROLS_CLOCK,
1129         .clkdm          = { .name = "cm_clkdm" },
1130         .recalc         = &omap2_clksel_recalc,
1131 };
1132
1133 /*
1134  * MPU clksel:
1135  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1136  * derives from the high-frequency bypass clock originating from DPLL3,
1137  * called 'dpll1_fck'
1138  */
1139 static const struct clksel mpu_clksel[] = {
1140         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1141         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1142         { .parent = NULL }
1143 };
1144
1145 static struct clk mpu_ck = {
1146         .name           = "mpu_ck",
1147         .parent         = &dpll1_x2m2_ck,
1148         .init           = &omap2_init_clksel_parent,
1149         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1150         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1151         .clksel         = mpu_clksel,
1152         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1153                                 PARENT_CONTROLS_CLOCK,
1154         .clkdm          = { .name = "mpu_clkdm" },
1155         .recalc         = &omap2_clksel_recalc,
1156 };
1157
1158 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1159 static const struct clksel_rate arm_fck_rates[] = {
1160         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1161         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1162         { .div = 0 },
1163 };
1164
1165 static const struct clksel arm_fck_clksel[] = {
1166         { .parent = &mpu_ck, .rates = arm_fck_rates },
1167         { .parent = NULL }
1168 };
1169
1170 static struct clk arm_fck = {
1171         .name           = "arm_fck",
1172         .parent         = &mpu_ck,
1173         .init           = &omap2_init_clksel_parent,
1174         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1175         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1176         .clksel         = arm_fck_clksel,
1177         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1178                                 PARENT_CONTROLS_CLOCK,
1179         .clkdm          = { .name = "mpu_clkdm" },
1180         .recalc         = &omap2_clksel_recalc,
1181 };
1182
1183 /* XXX What about neon_clkdm ? */
1184
1185 /*
1186  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1187  * although it is referenced - so this is a guess
1188  */
1189 static struct clk emu_mpu_alwon_ck = {
1190         .name           = "emu_mpu_alwon_ck",
1191         .parent         = &mpu_ck,
1192         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1193                                 PARENT_CONTROLS_CLOCK,
1194         .clkdm          = { .name = "mpu_clkdm" },
1195         .recalc         = &followparent_recalc,
1196 };
1197
1198 static struct clk dpll2_fck = {
1199         .name           = "dpll2_fck",
1200         .parent         = &core_ck,
1201         .init           = &omap2_init_clksel_parent,
1202         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1203         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1204         .clksel         = div4_core_clksel,
1205         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1206                                 PARENT_CONTROLS_CLOCK,
1207         .clkdm          = { .name = "cm_clkdm" },
1208         .recalc         = &omap2_clksel_recalc,
1209 };
1210
1211 /*
1212  * IVA2 clksel:
1213  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1214  * derives from the high-frequency bypass clock originating from DPLL3,
1215  * called 'dpll2_fck'
1216  */
1217
1218 static const struct clksel iva2_clksel[] = {
1219         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1220         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1221         { .parent = NULL }
1222 };
1223
1224 static struct clk iva2_ck = {
1225         .name           = "iva2_ck",
1226         .parent         = &dpll2_m2_ck,
1227         .init           = &omap2_init_clksel_parent,
1228         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1229         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1230         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1231                                           OMAP3430_CM_IDLEST_PLL),
1232         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1233         .clksel         = iva2_clksel,
1234         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1235         .clkdm          = { .name = "iva2_clkdm" },
1236         .recalc         = &omap2_clksel_recalc,
1237 };
1238
1239 /* Common interface clocks */
1240
1241 static const struct clksel div2_core_clksel[] = {
1242         { .parent = &core_ck, .rates = div2_rates },
1243         { .parent = NULL }
1244 };
1245
1246 static struct clk l3_ick = {
1247         .name           = "l3_ick",
1248         .parent         = &core_ck,
1249         .init           = &omap2_init_clksel_parent,
1250         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1251         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1252         .clksel         = div2_core_clksel,
1253         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1254                                 PARENT_CONTROLS_CLOCK,
1255         .clkdm          = { .name = "core_l3_clkdm" },
1256         .recalc         = &omap2_clksel_recalc,
1257 };
1258
1259 static const struct clksel div2_l3_clksel[] = {
1260         { .parent = &l3_ick, .rates = div2_rates },
1261         { .parent = NULL }
1262 };
1263
1264 static struct clk l4_ick = {
1265         .name           = "l4_ick",
1266         .parent         = &l3_ick,
1267         .init           = &omap2_init_clksel_parent,
1268         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1269         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1270         .clksel         = div2_l3_clksel,
1271         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1272                                 PARENT_CONTROLS_CLOCK,
1273         .clkdm          = { .name = "core_l4_clkdm" },
1274         .recalc         = &omap2_clksel_recalc,
1275
1276 };
1277
1278 static const struct clksel div2_l4_clksel[] = {
1279         { .parent = &l4_ick, .rates = div2_rates },
1280         { .parent = NULL }
1281 };
1282
1283 static struct clk rm_ick = {
1284         .name           = "rm_ick",
1285         .parent         = &l4_ick,
1286         .init           = &omap2_init_clksel_parent,
1287         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1288         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1289         .clksel         = div2_l4_clksel,
1290         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1291         .clkdm          = { .name = "cm_clkdm" },
1292         .recalc         = &omap2_clksel_recalc,
1293 };
1294
1295 /* GFX power domain */
1296
1297 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1298
1299 static const struct clksel gfx_l3_clksel[] = {
1300         { .parent = &l3_ick, .rates = gfx_l3_rates },
1301         { .parent = NULL }
1302 };
1303
1304 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1305 static struct clk gfx_l3_ck = {
1306         .name           = "gfx_l3_ck",
1307         .parent         = &l3_ick,
1308         .init           = &omap2_init_clksel_parent,
1309         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1310         .enable_bit     = OMAP_EN_GFX_SHIFT,
1311         .flags          = CLOCK_IN_OMAP3430ES1,
1312         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1313         .recalc         = &followparent_recalc,
1314 };
1315
1316 static struct clk gfx_l3_fck = {
1317         .name           = "gfx_l3_fck",
1318         .parent         = &gfx_l3_ck,
1319         .init           = &omap2_init_clksel_parent,
1320         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1321         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1322         .clksel         = gfx_l3_clksel,
1323         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1324                                 PARENT_CONTROLS_CLOCK,
1325         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1326         .recalc         = &omap2_clksel_recalc,
1327 };
1328
1329 static struct clk gfx_l3_ick = {
1330         .name           = "gfx_l3_ick",
1331         .parent         = &gfx_l3_ck,
1332         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1333         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk gfx_cg1_ck = {
1338         .name           = "gfx_cg1_ck",
1339         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1340         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1341         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1342         .flags          = CLOCK_IN_OMAP3430ES1,
1343         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static struct clk gfx_cg2_ck = {
1348         .name           = "gfx_cg2_ck",
1349         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1350         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1351         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1352         .flags          = CLOCK_IN_OMAP3430ES1,
1353         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 /* SGX power domain - 3430ES2 only */
1358
1359 static const struct clksel_rate sgx_core_rates[] = {
1360         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1361         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1362         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1363         { .div = 0 },
1364 };
1365
1366 static const struct clksel_rate sgx_96m_rates[] = {
1367         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1368         { .div = 0 },
1369 };
1370
1371 static const struct clksel sgx_clksel[] = {
1372         { .parent = &core_ck,    .rates = sgx_core_rates },
1373         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1374         { .parent = NULL },
1375 };
1376
1377 static struct clk sgx_fck = {
1378         .name           = "sgx_fck",
1379         .init           = &omap2_init_clksel_parent,
1380         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1381         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1382         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1383         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1384         .clksel         = sgx_clksel,
1385         .flags          = CLOCK_IN_OMAP3430ES2,
1386         .clkdm          = { .name = "sgx_clkdm" },
1387         .recalc         = &omap2_clksel_recalc,
1388 };
1389
1390 static struct clk sgx_ick = {
1391         .name           = "sgx_ick",
1392         .parent         = &l3_ick,
1393         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1394         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1395         .flags          = CLOCK_IN_OMAP3430ES2,
1396         .clkdm          = { .name = "sgx_clkdm" },
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 /* CORE power domain */
1401
1402 static struct clk d2d_26m_fck = {
1403         .name           = "d2d_26m_fck",
1404         .parent         = &sys_ck,
1405         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1407         .flags          = CLOCK_IN_OMAP3430ES1,
1408         .clkdm          = { .name = "d2d_clkdm" },
1409         .recalc         = &followparent_recalc,
1410 };
1411
1412 static const struct clksel omap343x_gpt_clksel[] = {
1413         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1414         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1415         { .parent = NULL}
1416 };
1417
1418 static struct clk gpt10_fck = {
1419         .name           = "gpt10_fck",
1420         .parent         = &sys_ck,
1421         .init           = &omap2_init_clksel_parent,
1422         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1423         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1424         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1425         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1426         .clksel         = omap343x_gpt_clksel,
1427         .flags          = CLOCK_IN_OMAP343X,
1428         .clkdm          = { .name = "core_l4_clkdm" },
1429         .recalc         = &omap2_clksel_recalc,
1430 };
1431
1432 static struct clk gpt11_fck = {
1433         .name           = "gpt11_fck",
1434         .parent         = &sys_ck,
1435         .init           = &omap2_init_clksel_parent,
1436         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1438         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1439         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1440         .clksel         = omap343x_gpt_clksel,
1441         .flags          = CLOCK_IN_OMAP343X,
1442         .clkdm          = { .name = "core_l4_clkdm" },
1443         .recalc         = &omap2_clksel_recalc,
1444 };
1445
1446 static struct clk cpefuse_fck = {
1447         .name           = "cpefuse_fck",
1448         .parent         = &sys_ck,
1449         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1450         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1451         .flags          = CLOCK_IN_OMAP3430ES2,
1452         .clkdm          = { .name = "cm_clkdm" },
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 static struct clk ts_fck = {
1457         .name           = "ts_fck",
1458         .parent         = &omap_32k_fck,
1459         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1460         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1461         .flags          = CLOCK_IN_OMAP3430ES2,
1462         .clkdm          = { .name = "core_l4_clkdm" },
1463         .recalc         = &followparent_recalc,
1464 };
1465
1466 static struct clk usbtll_fck = {
1467         .name           = "usbtll_fck",
1468         .parent         = &omap_120m_fck,
1469         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1470         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1471         .flags          = CLOCK_IN_OMAP3430ES2,
1472         .clkdm          = { .name = "core_l4_clkdm" },
1473         .recalc         = &followparent_recalc,
1474 };
1475
1476 /* CORE 96M FCLK-derived clocks */
1477
1478 static struct clk core_96m_fck = {
1479         .name           = "core_96m_fck",
1480         .parent         = &omap_96m_fck,
1481         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1482                                 PARENT_CONTROLS_CLOCK,
1483         .clkdm          = { .name = "core_l4_clkdm" },
1484         .recalc         = &followparent_recalc,
1485 };
1486
1487 static struct clk mmchs3_fck = {
1488         .name           = "mmchs_fck",
1489         .id             = 3,
1490         .parent         = &core_96m_fck,
1491         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1493         .flags          = CLOCK_IN_OMAP3430ES2,
1494         .clkdm          = { .name = "core_l4_clkdm" },
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk mmchs2_fck = {
1499         .name           = "mmchs_fck",
1500         .id             = 2,
1501         .parent         = &core_96m_fck,
1502         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1503         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1504         .flags          = CLOCK_IN_OMAP343X,
1505         .clkdm          = { .name = "core_l4_clkdm" },
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 static struct clk mspro_fck = {
1510         .name           = "mspro_fck",
1511         .parent         = &core_96m_fck,
1512         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1513         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1514         .flags          = CLOCK_IN_OMAP343X,
1515         .clkdm          = { .name = "core_l4_clkdm" },
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk mmchs1_fck = {
1520         .name           = "mmchs_fck",
1521         .id             = 1,
1522         .parent         = &core_96m_fck,
1523         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1525         .flags          = CLOCK_IN_OMAP343X,
1526         .clkdm          = { .name = "core_l4_clkdm" },
1527         .recalc         = &followparent_recalc,
1528 };
1529
1530 static struct clk i2c3_fck = {
1531         .name           = "i2c_fck",
1532         .id             = 3,
1533         .parent         = &core_96m_fck,
1534         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1535         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1536         .flags          = CLOCK_IN_OMAP343X,
1537         .clkdm          = { .name = "core_l4_clkdm" },
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk i2c2_fck = {
1542         .name           = "i2c_fck",
1543         .id             = 2,
1544         .parent         = &core_96m_fck,
1545         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1547         .flags          = CLOCK_IN_OMAP343X,
1548         .clkdm          = { .name = "core_l4_clkdm" },
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk i2c1_fck = {
1553         .name           = "i2c_fck",
1554         .id             = 1,
1555         .parent         = &core_96m_fck,
1556         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1558         .flags          = CLOCK_IN_OMAP343X,
1559         .clkdm          = { .name = "core_l4_clkdm" },
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 /*
1564  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1565  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1566  */
1567 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1568         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1569         { .div = 0 }
1570 };
1571
1572 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1573         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1574         { .div = 0 }
1575 };
1576
1577 static const struct clksel mcbsp_15_clksel[] = {
1578         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1579         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1580         { .parent = NULL }
1581 };
1582
1583 static struct clk mcbsp5_fck = {
1584         .name           = "mcbsp_fck",
1585         .id             = 5,
1586         .init           = &omap2_init_clksel_parent,
1587         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1589         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1590         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1591         .clksel         = mcbsp_15_clksel,
1592         .flags          = CLOCK_IN_OMAP343X,
1593         .clkdm          = { .name = "core_l4_clkdm" },
1594         .recalc         = &omap2_clksel_recalc,
1595 };
1596
1597 static struct clk mcbsp1_fck = {
1598         .name           = "mcbsp_fck",
1599         .id             = 1,
1600         .init           = &omap2_init_clksel_parent,
1601         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1603         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1604         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1605         .clksel         = mcbsp_15_clksel,
1606         .flags          = CLOCK_IN_OMAP343X,
1607         .clkdm          = { .name = "core_l4_clkdm" },
1608         .recalc         = &omap2_clksel_recalc,
1609 };
1610
1611 /* CORE_48M_FCK-derived clocks */
1612
1613 static struct clk core_48m_fck = {
1614         .name           = "core_48m_fck",
1615         .parent         = &omap_48m_fck,
1616         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1617                                 PARENT_CONTROLS_CLOCK,
1618         .clkdm          = { .name = "core_l4_clkdm" },
1619         .recalc         = &followparent_recalc,
1620 };
1621
1622 static struct clk mcspi4_fck = {
1623         .name           = "mcspi_fck",
1624         .id             = 4,
1625         .parent         = &core_48m_fck,
1626         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1627         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1628         .flags          = CLOCK_IN_OMAP343X,
1629         .clkdm          = { .name = "core_l4_clkdm" },
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 static struct clk mcspi3_fck = {
1634         .name           = "mcspi_fck",
1635         .id             = 3,
1636         .parent         = &core_48m_fck,
1637         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1639         .flags          = CLOCK_IN_OMAP343X,
1640         .clkdm          = { .name = "core_l4_clkdm" },
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 static struct clk mcspi2_fck = {
1645         .name           = "mcspi_fck",
1646         .id             = 2,
1647         .parent         = &core_48m_fck,
1648         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1649         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1650         .flags          = CLOCK_IN_OMAP343X,
1651         .clkdm          = { .name = "core_l4_clkdm" },
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk mcspi1_fck = {
1656         .name           = "mcspi_fck",
1657         .id             = 1,
1658         .parent         = &core_48m_fck,
1659         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1661         .flags          = CLOCK_IN_OMAP343X,
1662         .clkdm          = { .name = "core_l4_clkdm" },
1663         .recalc         = &followparent_recalc,
1664 };
1665
1666 static struct clk uart2_fck = {
1667         .name           = "uart2_fck",
1668         .parent         = &core_48m_fck,
1669         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1670         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1671         .flags          = CLOCK_IN_OMAP343X,
1672         .clkdm          = { .name = "core_l4_clkdm" },
1673         .recalc         = &followparent_recalc,
1674 };
1675
1676 static struct clk uart1_fck = {
1677         .name           = "uart1_fck",
1678         .parent         = &core_48m_fck,
1679         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1681         .flags          = CLOCK_IN_OMAP343X,
1682         .clkdm          = { .name = "core_l4_clkdm" },
1683         .recalc         = &followparent_recalc,
1684 };
1685
1686 static struct clk fshostusb_fck = {
1687         .name           = "fshostusb_fck",
1688         .parent         = &core_48m_fck,
1689         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1690         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1691         .flags          = CLOCK_IN_OMAP3430ES1,
1692         .clkdm          = { .name = "core_l4_clkdm" },
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 /* CORE_12M_FCK based clocks */
1697
1698 static struct clk core_12m_fck = {
1699         .name           = "core_12m_fck",
1700         .parent         = &omap_12m_fck,
1701         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1702                                 PARENT_CONTROLS_CLOCK,
1703         .clkdm          = { .name = "core_l4_clkdm" },
1704         .recalc         = &followparent_recalc,
1705 };
1706
1707 static struct clk hdq_fck = {
1708         .name           = "hdq_fck",
1709         .parent         = &core_12m_fck,
1710         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1711         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1712         .flags          = CLOCK_IN_OMAP343X,
1713         .clkdm          = { .name = "core_l4_clkdm" },
1714         .recalc         = &followparent_recalc,
1715 };
1716
1717 /* DPLL3-derived clock */
1718
1719 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1720         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1721         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1722         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1723         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1724         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1725         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1726         { .div = 0 }
1727 };
1728
1729 static const struct clksel ssi_ssr_clksel[] = {
1730         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1731         { .parent = NULL }
1732 };
1733
1734 static struct clk ssi_ssr_fck = {
1735         .name           = "ssi_ssr_fck",
1736         .init           = &omap2_init_clksel_parent,
1737         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1738         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1739         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1740         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1741         .clksel         = ssi_ssr_clksel,
1742         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1743         .clkdm          = { .name = "core_l4_clkdm" },
1744         .recalc         = &omap2_clksel_recalc,
1745 };
1746
1747 static struct clk ssi_sst_fck = {
1748         .name           = "ssi_sst_fck",
1749         .parent         = &ssi_ssr_fck,
1750         .fixed_div      = 2,
1751         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1752         .clkdm          = { .name = "core_l4_clkdm" },
1753         .recalc         = &omap2_fixed_divisor_recalc,
1754 };
1755
1756
1757
1758 /* CORE_L3_ICK based clocks */
1759
1760 /*
1761  * XXX must add clk_enable/clk_disable for these if standard code won't
1762  * handle it
1763  */
1764 static struct clk core_l3_ick = {
1765         .name           = "core_l3_ick",
1766         .parent         = &l3_ick,
1767         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1768                                 PARENT_CONTROLS_CLOCK,
1769         .clkdm          = { .name = "core_l3_clkdm" },
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk hsotgusb_ick = {
1774         .name           = "hsotgusb_ick",
1775         .parent         = &core_l3_ick,
1776         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1778         .flags          = CLOCK_IN_OMAP343X,
1779         .clkdm          = { .name = "core_l3_clkdm" },
1780         .recalc         = &followparent_recalc,
1781 };
1782
1783 static struct clk sdrc_ick = {
1784         .name           = "sdrc_ick",
1785         .parent         = &core_l3_ick,
1786         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1787         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1788         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1789         .clkdm          = { .name = "core_l3_clkdm" },
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk gpmc_fck = {
1794         .name           = "gpmc_fck",
1795         .parent         = &core_l3_ick,
1796         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1797                                 ENABLE_ON_INIT,
1798         .clkdm          = { .name = "core_l3_clkdm" },
1799         .recalc         = &followparent_recalc,
1800 };
1801
1802 /* SECURITY_L3_ICK based clocks */
1803
1804 static struct clk security_l3_ick = {
1805         .name           = "security_l3_ick",
1806         .parent         = &l3_ick,
1807         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1808                                 PARENT_CONTROLS_CLOCK,
1809         .clkdm          = { .name = "core_l3_clkdm" },
1810         .recalc         = &followparent_recalc,
1811 };
1812
1813 static struct clk pka_ick = {
1814         .name           = "pka_ick",
1815         .parent         = &security_l3_ick,
1816         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1817         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1818         .flags          = CLOCK_IN_OMAP343X,
1819         .clkdm          = { .name = "core_l3_clkdm" },
1820         .recalc         = &followparent_recalc,
1821 };
1822
1823 /* CORE_L4_ICK based clocks */
1824
1825 static struct clk core_l4_ick = {
1826         .name           = "core_l4_ick",
1827         .parent         = &l4_ick,
1828         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1829                                 PARENT_CONTROLS_CLOCK,
1830         .clkdm          = { .name = "core_l4_clkdm" },
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 static struct clk usbtll_ick = {
1835         .name           = "usbtll_ick",
1836         .parent         = &core_l4_ick,
1837         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1838         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1839         .flags          = CLOCK_IN_OMAP3430ES2,
1840         .clkdm          = { .name = "core_l4_clkdm" },
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk mmchs3_ick = {
1845         .name           = "mmchs_ick",
1846         .id             = 3,
1847         .parent         = &core_l4_ick,
1848         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1849         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1850         .flags          = CLOCK_IN_OMAP3430ES2,
1851         .clkdm          = { .name = "core_l4_clkdm" },
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 /* Intersystem Communication Registers - chassis mode only */
1856 static struct clk icr_ick = {
1857         .name           = "icr_ick",
1858         .parent         = &core_l4_ick,
1859         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1860         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1861         .flags          = CLOCK_IN_OMAP343X,
1862         .clkdm          = { .name = "core_l4_clkdm" },
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk aes2_ick = {
1867         .name           = "aes2_ick",
1868         .parent         = &core_l4_ick,
1869         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1870         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1871         .flags          = CLOCK_IN_OMAP343X,
1872         .clkdm          = { .name = "core_l4_clkdm" },
1873         .recalc         = &followparent_recalc,
1874 };
1875
1876 static struct clk sha12_ick = {
1877         .name           = "sha12_ick",
1878         .parent         = &core_l4_ick,
1879         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1880         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1881         .flags          = CLOCK_IN_OMAP343X,
1882         .clkdm          = { .name = "core_l4_clkdm" },
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk des2_ick = {
1887         .name           = "des2_ick",
1888         .parent         = &core_l4_ick,
1889         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1891         .flags          = CLOCK_IN_OMAP343X,
1892         .clkdm          = { .name = "core_l4_clkdm" },
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mmchs2_ick = {
1897         .name           = "mmchs_ick",
1898         .id             = 2,
1899         .parent         = &core_l4_ick,
1900         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1902         .flags          = CLOCK_IN_OMAP343X,
1903         .clkdm          = { .name = "core_l4_clkdm" },
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mmchs1_ick = {
1908         .name           = "mmchs_ick",
1909         .id             = 1,
1910         .parent         = &core_l4_ick,
1911         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X,
1914         .clkdm          = { .name = "core_l4_clkdm" },
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk mspro_ick = {
1919         .name           = "mspro_ick",
1920         .parent         = &core_l4_ick,
1921         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1923         .flags          = CLOCK_IN_OMAP343X,
1924         .clkdm          = { .name = "core_l4_clkdm" },
1925         .recalc         = &followparent_recalc,
1926 };
1927
1928 static struct clk hdq_ick = {
1929         .name           = "hdq_ick",
1930         .parent         = &core_l4_ick,
1931         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1932         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1933         .flags          = CLOCK_IN_OMAP343X,
1934         .clkdm          = { .name = "core_l4_clkdm" },
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk mcspi4_ick = {
1939         .name           = "mcspi_ick",
1940         .id             = 4,
1941         .parent         = &core_l4_ick,
1942         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1944         .flags          = CLOCK_IN_OMAP343X,
1945         .clkdm          = { .name = "core_l4_clkdm" },
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk mcspi3_ick = {
1950         .name           = "mcspi_ick",
1951         .id             = 3,
1952         .parent         = &core_l4_ick,
1953         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1954         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1955         .flags          = CLOCK_IN_OMAP343X,
1956         .clkdm          = { .name = "core_l4_clkdm" },
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk mcspi2_ick = {
1961         .name           = "mcspi_ick",
1962         .id             = 2,
1963         .parent         = &core_l4_ick,
1964         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1966         .flags          = CLOCK_IN_OMAP343X,
1967         .clkdm          = { .name = "core_l4_clkdm" },
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk mcspi1_ick = {
1972         .name           = "mcspi_ick",
1973         .id             = 1,
1974         .parent         = &core_l4_ick,
1975         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1977         .flags          = CLOCK_IN_OMAP343X,
1978         .clkdm          = { .name = "core_l4_clkdm" },
1979         .recalc         = &followparent_recalc,
1980 };
1981
1982 static struct clk i2c3_ick = {
1983         .name           = "i2c_ick",
1984         .id             = 3,
1985         .parent         = &core_l4_ick,
1986         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1988         .flags          = CLOCK_IN_OMAP343X,
1989         .clkdm          = { .name = "core_l4_clkdm" },
1990         .recalc         = &followparent_recalc,
1991 };
1992
1993 static struct clk i2c2_ick = {
1994         .name           = "i2c_ick",
1995         .id             = 2,
1996         .parent         = &core_l4_ick,
1997         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1999         .flags          = CLOCK_IN_OMAP343X,
2000         .clkdm          = { .name = "core_l4_clkdm" },
2001         .recalc         = &followparent_recalc,
2002 };
2003
2004 static struct clk i2c1_ick = {
2005         .name           = "i2c_ick",
2006         .id             = 1,
2007         .parent         = &core_l4_ick,
2008         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2009         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2010         .flags          = CLOCK_IN_OMAP343X,
2011         .clkdm          = { .name = "core_l4_clkdm" },
2012         .recalc         = &followparent_recalc,
2013 };
2014
2015 static struct clk uart2_ick = {
2016         .name           = "uart2_ick",
2017         .parent         = &core_l4_ick,
2018         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2020         .flags          = CLOCK_IN_OMAP343X,
2021         .clkdm          = { .name = "core_l4_clkdm" },
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk uart1_ick = {
2026         .name           = "uart1_ick",
2027         .parent         = &core_l4_ick,
2028         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2029         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2030         .flags          = CLOCK_IN_OMAP343X,
2031         .clkdm          = { .name = "core_l4_clkdm" },
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk gpt11_ick = {
2036         .name           = "gpt11_ick",
2037         .parent         = &core_l4_ick,
2038         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2040         .flags          = CLOCK_IN_OMAP343X,
2041         .clkdm          = { .name = "core_l4_clkdm" },
2042         .recalc         = &followparent_recalc,
2043 };
2044
2045 static struct clk gpt10_ick = {
2046         .name           = "gpt10_ick",
2047         .parent         = &core_l4_ick,
2048         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2050         .flags          = CLOCK_IN_OMAP343X,
2051         .clkdm          = { .name = "core_l4_clkdm" },
2052         .recalc         = &followparent_recalc,
2053 };
2054
2055 static struct clk mcbsp5_ick = {
2056         .name           = "mcbsp_ick",
2057         .id             = 5,
2058         .parent         = &core_l4_ick,
2059         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2060         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2061         .flags          = CLOCK_IN_OMAP343X,
2062         .clkdm          = { .name = "core_l4_clkdm" },
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk mcbsp1_ick = {
2067         .name           = "mcbsp_ick",
2068         .id             = 1,
2069         .parent         = &core_l4_ick,
2070         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2072         .flags          = CLOCK_IN_OMAP343X,
2073         .clkdm          = { .name = "core_l4_clkdm" },
2074         .recalc         = &followparent_recalc,
2075 };
2076
2077 static struct clk fac_ick = {
2078         .name           = "fac_ick",
2079         .parent         = &core_l4_ick,
2080         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2081         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2082         .flags          = CLOCK_IN_OMAP3430ES1,
2083         .clkdm          = { .name = "core_l4_clkdm" },
2084         .recalc         = &followparent_recalc,
2085 };
2086
2087 static struct clk mailboxes_ick = {
2088         .name           = "mailboxes_ick",
2089         .parent         = &core_l4_ick,
2090         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2091         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2092         .flags          = CLOCK_IN_OMAP343X,
2093         .clkdm          = { .name = "core_l4_clkdm" },
2094         .recalc         = &followparent_recalc,
2095 };
2096
2097 static struct clk omapctrl_ick = {
2098         .name           = "omapctrl_ick",
2099         .parent         = &core_l4_ick,
2100         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2101         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2102         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2103         .clkdm          = { .name = "core_l4_clkdm" },
2104         .recalc         = &followparent_recalc,
2105 };
2106
2107 /* SSI_L4_ICK based clocks */
2108
2109 static struct clk ssi_l4_ick = {
2110         .name           = "ssi_l4_ick",
2111         .parent         = &l4_ick,
2112         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2113                                 PARENT_CONTROLS_CLOCK,
2114         .clkdm          = { .name = "core_l4_clkdm" },
2115         .recalc         = &followparent_recalc,
2116 };
2117
2118 static struct clk ssi_ick = {
2119         .name           = "ssi_ick",
2120         .parent         = &ssi_l4_ick,
2121         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2122         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2123         .flags          = CLOCK_IN_OMAP343X,
2124         .clkdm          = { .name = "core_l4_clkdm" },
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2129  * but l4_ick makes more sense to me */
2130
2131 static const struct clksel usb_l4_clksel[] = {
2132         { .parent = &l4_ick, .rates = div2_rates },
2133         { .parent = NULL },
2134 };
2135
2136 static struct clk usb_l4_ick = {
2137         .name           = "usb_l4_ick",
2138         .parent         = &l4_ick,
2139         .init           = &omap2_init_clksel_parent,
2140         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2141         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2142         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2143         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2144         .clksel         = usb_l4_clksel,
2145         .flags          = CLOCK_IN_OMAP3430ES1,
2146         .clkdm          = { .name = "core_l4_clkdm" },
2147         .recalc         = &omap2_clksel_recalc,
2148 };
2149
2150 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2151
2152 /* SECURITY_L4_ICK2 based clocks */
2153
2154 static struct clk security_l4_ick2 = {
2155         .name           = "security_l4_ick2",
2156         .parent         = &l4_ick,
2157         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2158                                 PARENT_CONTROLS_CLOCK,
2159         .clkdm          = { .name = "core_l4_clkdm" },
2160         .recalc         = &followparent_recalc,
2161 };
2162
2163 static struct clk aes1_ick = {
2164         .name           = "aes1_ick",
2165         .parent         = &security_l4_ick2,
2166         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2167         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2168         .flags          = CLOCK_IN_OMAP343X,
2169         .clkdm          = { .name = "core_l4_clkdm" },
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk rng_ick = {
2174         .name           = "rng_ick",
2175         .parent         = &security_l4_ick2,
2176         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2177         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2178         .flags          = CLOCK_IN_OMAP343X,
2179         .clkdm          = { .name = "core_l4_clkdm" },
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk sha11_ick = {
2184         .name           = "sha11_ick",
2185         .parent         = &security_l4_ick2,
2186         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2187         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2188         .flags          = CLOCK_IN_OMAP343X,
2189         .clkdm          = { .name = "core_l4_clkdm" },
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk des1_ick = {
2194         .name           = "des1_ick",
2195         .parent         = &security_l4_ick2,
2196         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2197         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2198         .flags          = CLOCK_IN_OMAP343X,
2199         .clkdm          = { .name = "core_l4_clkdm" },
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 /* DSS */
2204 static const struct clksel dss1_alwon_fck_clksel[] = {
2205         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2206         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2207         { .parent = NULL }
2208 };
2209
2210 static struct clk dss1_alwon_fck = {
2211         .name           = "dss1_alwon_fck",
2212         .parent         = &dpll4_m4x2_ck,
2213         .init           = &omap2_init_clksel_parent,
2214         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2215         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2216         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2217         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2218         .clksel         = dss1_alwon_fck_clksel,
2219         .flags          = CLOCK_IN_OMAP343X,
2220         .clkdm          = { .name = "dss_clkdm" },
2221         .recalc         = &omap2_clksel_recalc,
2222 };
2223
2224 static struct clk dss_tv_fck = {
2225         .name           = "dss_tv_fck",
2226         .parent         = &omap_54m_fck,
2227         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2228         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2229         .flags          = CLOCK_IN_OMAP343X,
2230         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2231         .recalc         = &followparent_recalc,
2232 };
2233
2234 static struct clk dss_96m_fck = {
2235         .name           = "dss_96m_fck",
2236         .parent         = &omap_96m_fck,
2237         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2238         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2239         .flags          = CLOCK_IN_OMAP343X,
2240         .clkdm          = { .name = "dss_clkdm" },
2241         .recalc         = &followparent_recalc,
2242 };
2243
2244 static struct clk dss2_alwon_fck = {
2245         .name           = "dss2_alwon_fck",
2246         .parent         = &sys_ck,
2247         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2248         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2249         .flags          = CLOCK_IN_OMAP343X,
2250         .clkdm          = { .name = "dss_clkdm" },
2251         .recalc         = &followparent_recalc,
2252 };
2253
2254 static struct clk dss_ick = {
2255         /* Handles both L3 and L4 clocks */
2256         .name           = "dss_ick",
2257         .parent         = &l4_ick,
2258         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2259         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2260         .flags          = CLOCK_IN_OMAP343X,
2261         .clkdm          = { .name = "dss_clkdm" },
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 /* CAM */
2266
2267 static const struct clksel cam_mclk_clksel[] = {
2268         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2269         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2270         { .parent = NULL }
2271 };
2272
2273 static struct clk cam_mclk = {
2274         .name           = "cam_mclk",
2275         .parent         = &dpll4_m5x2_ck,
2276         .init           = &omap2_init_clksel_parent,
2277         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2278         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2279         .clksel         = cam_mclk_clksel,
2280         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2281         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2282         .flags          = CLOCK_IN_OMAP343X,
2283         .clkdm          = { .name = "cam_clkdm" },
2284         .recalc         = &omap2_clksel_recalc,
2285 };
2286
2287 static struct clk cam_ick = {
2288         /* Handles both L3 and L4 clocks */
2289         .name           = "cam_ick",
2290         .parent         = &l4_ick,
2291         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2292         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2293         .flags          = CLOCK_IN_OMAP343X,
2294         .clkdm          = { .name = "cam_clkdm" },
2295         .recalc         = &followparent_recalc,
2296 };
2297
2298 static struct clk csi2_96m_fck = {
2299         .name           = "csi2_96m_fck",
2300         .parent         = &core_96m_fck,
2301         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2302         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2303         .flags          = CLOCK_IN_OMAP343X,
2304         .clkdm          = { .name = "cam_clkdm" },
2305         .recalc         = &followparent_recalc,
2306 };
2307
2308 /* USBHOST - 3430ES2 only */
2309
2310 static struct clk usbhost_120m_fck = {
2311         .name           = "usbhost_120m_fck",
2312         .parent         = &omap_120m_fck,
2313         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2314         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2315         .flags          = CLOCK_IN_OMAP3430ES2,
2316         .clkdm          = { .name = "usbhost_clkdm" },
2317         .recalc         = &followparent_recalc,
2318 };
2319
2320 static struct clk usbhost_48m_fck = {
2321         .name           = "usbhost_48m_fck",
2322         .parent         = &omap_48m_fck,
2323         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2324         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2325         .flags          = CLOCK_IN_OMAP3430ES2,
2326         .clkdm          = { .name = "usbhost_clkdm" },
2327         .recalc         = &followparent_recalc,
2328 };
2329
2330 static struct clk usbhost_ick = {
2331         /* Handles both L3 and L4 clocks */
2332         .name           = "usbhost_ick",
2333         .parent         = &l4_ick,
2334         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2335         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2336         .flags          = CLOCK_IN_OMAP3430ES2,
2337         .clkdm          = { .name = "usbhost_clkdm" },
2338         .recalc         = &followparent_recalc,
2339 };
2340
2341 /* WKUP */
2342
2343 static const struct clksel_rate usim_96m_rates[] = {
2344         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2345         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2346         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2347         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2348         { .div = 0 },
2349 };
2350
2351 static const struct clksel_rate usim_120m_rates[] = {
2352         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2353         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2354         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2355         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2356         { .div = 0 },
2357 };
2358
2359 static const struct clksel usim_clksel[] = {
2360         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2361         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2362         { .parent = &sys_ck,            .rates = div2_rates },
2363         { .parent = NULL },
2364 };
2365
2366 /* 3430ES2 only */
2367 static struct clk usim_fck = {
2368         .name           = "usim_fck",
2369         .init           = &omap2_init_clksel_parent,
2370         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2371         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2372         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2373         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2374         .clksel         = usim_clksel,
2375         .flags          = CLOCK_IN_OMAP3430ES2,
2376         .clkdm          = { .name = "prm_clkdm" },
2377         .recalc         = &omap2_clksel_recalc,
2378 };
2379
2380 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2381 static struct clk gpt1_fck = {
2382         .name           = "gpt1_fck",
2383         .init           = &omap2_init_clksel_parent,
2384         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2385         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2386         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2387         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2388         .clksel         = omap343x_gpt_clksel,
2389         .flags          = CLOCK_IN_OMAP343X,
2390         .clkdm          = { .name = "prm_clkdm" },
2391         .recalc         = &omap2_clksel_recalc,
2392 };
2393
2394 static struct clk wkup_32k_fck = {
2395         .name           = "wkup_32k_fck",
2396         .parent         = &omap_32k_fck,
2397         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2398         .clkdm          = { .name = "prm_clkdm" },
2399         .recalc         = &followparent_recalc,
2400 };
2401
2402 static struct clk gpio1_fck = {
2403         .name           = "gpio1_fck",
2404         .parent         = &wkup_32k_fck,
2405         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2406         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2407         .flags          = CLOCK_IN_OMAP343X,
2408         .clkdm          = { .name = "prm_clkdm" },
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412 static struct clk wdt2_fck = {
2413         .name           = "wdt2_fck",
2414         .parent         = &wkup_32k_fck,
2415         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2416         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2417         .flags          = CLOCK_IN_OMAP343X,
2418         .clkdm          = { .name = "prm_clkdm" },
2419         .recalc         = &followparent_recalc,
2420 };
2421
2422 static struct clk wkup_l4_ick = {
2423         .name           = "wkup_l4_ick",
2424         .parent         = &sys_ck,
2425         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2426         .clkdm          = { .name = "prm_clkdm" },
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 /* 3430ES2 only */
2431 /* Never specifically named in the TRM, so we have to infer a likely name */
2432 static struct clk usim_ick = {
2433         .name           = "usim_ick",
2434         .parent         = &wkup_l4_ick,
2435         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2436         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2437         .flags          = CLOCK_IN_OMAP3430ES2,
2438         .clkdm          = { .name = "prm_clkdm" },
2439         .recalc         = &followparent_recalc,
2440 };
2441
2442 static struct clk wdt2_ick = {
2443         .name           = "wdt2_ick",
2444         .parent         = &wkup_l4_ick,
2445         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2446         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2447         .flags          = CLOCK_IN_OMAP343X,
2448         .clkdm          = { .name = "prm_clkdm" },
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452 static struct clk wdt1_ick = {
2453         .name           = "wdt1_ick",
2454         .parent         = &wkup_l4_ick,
2455         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2456         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2457         .flags          = CLOCK_IN_OMAP343X,
2458         .clkdm          = { .name = "prm_clkdm" },
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 static struct clk gpio1_ick = {
2463         .name           = "gpio1_ick",
2464         .parent         = &wkup_l4_ick,
2465         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2466         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2467         .flags          = CLOCK_IN_OMAP343X,
2468         .clkdm          = { .name = "prm_clkdm" },
2469         .recalc         = &followparent_recalc,
2470 };
2471
2472 static struct clk omap_32ksync_ick = {
2473         .name           = "omap_32ksync_ick",
2474         .parent         = &wkup_l4_ick,
2475         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2476         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2477         .flags          = CLOCK_IN_OMAP343X,
2478         .clkdm          = { .name = "prm_clkdm" },
2479         .recalc         = &followparent_recalc,
2480 };
2481
2482 static struct clk gpt12_ick = {
2483         .name           = "gpt12_ick",
2484         .parent         = &wkup_l4_ick,
2485         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2486         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2487         .flags          = CLOCK_IN_OMAP343X,
2488         .clkdm          = { .name = "prm_clkdm" },
2489         .recalc         = &followparent_recalc,
2490 };
2491
2492 static struct clk gpt1_ick = {
2493         .name           = "gpt1_ick",
2494         .parent         = &wkup_l4_ick,
2495         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2496         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2497         .flags          = CLOCK_IN_OMAP343X,
2498         .clkdm          = { .name = "prm_clkdm" },
2499         .recalc         = &followparent_recalc,
2500 };
2501
2502
2503
2504 /* PER clock domain */
2505
2506 static struct clk per_96m_fck = {
2507         .name           = "per_96m_fck",
2508         .parent         = &omap_96m_alwon_fck,
2509         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2510                                 PARENT_CONTROLS_CLOCK,
2511         .clkdm          = { .name = "per_clkdm" },
2512         .recalc         = &followparent_recalc,
2513 };
2514
2515 static struct clk per_48m_fck = {
2516         .name           = "per_48m_fck",
2517         .parent         = &omap_48m_fck,
2518         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2519                                 PARENT_CONTROLS_CLOCK,
2520         .clkdm          = { .name = "per_clkdm" },
2521         .recalc         = &followparent_recalc,
2522 };
2523
2524 static struct clk uart3_fck = {
2525         .name           = "uart3_fck",
2526         .parent         = &per_48m_fck,
2527         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2528         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2529         .flags          = CLOCK_IN_OMAP343X,
2530         .clkdm          = { .name = "per_clkdm" },
2531         .recalc         = &followparent_recalc,
2532 };
2533
2534 static struct clk gpt2_fck = {
2535         .name           = "gpt2_fck",
2536         .init           = &omap2_init_clksel_parent,
2537         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2538         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2539         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2540         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2541         .clksel         = omap343x_gpt_clksel,
2542         .flags          = CLOCK_IN_OMAP343X,
2543         .clkdm          = { .name = "per_clkdm" },
2544         .recalc         = &omap2_clksel_recalc,
2545 };
2546
2547 static struct clk gpt3_fck = {
2548         .name           = "gpt3_fck",
2549         .init           = &omap2_init_clksel_parent,
2550         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2551         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2552         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2553         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2554         .clksel         = omap343x_gpt_clksel,
2555         .flags          = CLOCK_IN_OMAP343X,
2556         .clkdm          = { .name = "per_clkdm" },
2557         .recalc         = &omap2_clksel_recalc,
2558 };
2559
2560 static struct clk gpt4_fck = {
2561         .name           = "gpt4_fck",
2562         .init           = &omap2_init_clksel_parent,
2563         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2565         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2566         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2567         .clksel         = omap343x_gpt_clksel,
2568         .flags          = CLOCK_IN_OMAP343X,
2569         .clkdm          = { .name = "per_clkdm" },
2570         .recalc         = &omap2_clksel_recalc,
2571 };
2572
2573 static struct clk gpt5_fck = {
2574         .name           = "gpt5_fck",
2575         .init           = &omap2_init_clksel_parent,
2576         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2578         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2579         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2580         .clksel         = omap343x_gpt_clksel,
2581         .flags          = CLOCK_IN_OMAP343X,
2582         .clkdm          = { .name = "per_clkdm" },
2583         .recalc         = &omap2_clksel_recalc,
2584 };
2585
2586 static struct clk gpt6_fck = {
2587         .name           = "gpt6_fck",
2588         .init           = &omap2_init_clksel_parent,
2589         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2591         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2592         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2593         .clksel         = omap343x_gpt_clksel,
2594         .flags          = CLOCK_IN_OMAP343X,
2595         .clkdm          = { .name = "per_clkdm" },
2596         .recalc         = &omap2_clksel_recalc,
2597 };
2598
2599 static struct clk gpt7_fck = {
2600         .name           = "gpt7_fck",
2601         .init           = &omap2_init_clksel_parent,
2602         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2603         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2604         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2605         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2606         .clksel         = omap343x_gpt_clksel,
2607         .flags          = CLOCK_IN_OMAP343X,
2608         .clkdm          = { .name = "per_clkdm" },
2609         .recalc         = &omap2_clksel_recalc,
2610 };
2611
2612 static struct clk gpt8_fck = {
2613         .name           = "gpt8_fck",
2614         .init           = &omap2_init_clksel_parent,
2615         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2616         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2617         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2618         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2619         .clksel         = omap343x_gpt_clksel,
2620         .flags          = CLOCK_IN_OMAP343X,
2621         .clkdm          = { .name = "per_clkdm" },
2622         .recalc         = &omap2_clksel_recalc,
2623 };
2624
2625 static struct clk gpt9_fck = {
2626         .name           = "gpt9_fck",
2627         .init           = &omap2_init_clksel_parent,
2628         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2629         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2630         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2631         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2632         .clksel         = omap343x_gpt_clksel,
2633         .flags          = CLOCK_IN_OMAP343X,
2634         .clkdm          = { .name = "per_clkdm" },
2635         .recalc         = &omap2_clksel_recalc,
2636 };
2637
2638 static struct clk per_32k_alwon_fck = {
2639         .name           = "per_32k_alwon_fck",
2640         .parent         = &omap_32k_fck,
2641         .clkdm          = { .name = "per_clkdm" },
2642         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2643         .recalc         = &followparent_recalc,
2644 };
2645
2646 static struct clk gpio6_fck = {
2647         .name           = "gpio6_fck",
2648         .parent         = &per_32k_alwon_fck,
2649         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2650         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2651         .flags          = CLOCK_IN_OMAP343X,
2652         .clkdm          = { .name = "per_clkdm" },
2653         .recalc         = &followparent_recalc,
2654 };
2655
2656 static struct clk gpio5_fck = {
2657         .name           = "gpio5_fck",
2658         .parent         = &per_32k_alwon_fck,
2659         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2660         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2661         .flags          = CLOCK_IN_OMAP343X,
2662         .clkdm          = { .name = "per_clkdm" },
2663         .recalc         = &followparent_recalc,
2664 };
2665
2666 static struct clk gpio4_fck = {
2667         .name           = "gpio4_fck",
2668         .parent         = &per_32k_alwon_fck,
2669         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2670         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2671         .flags          = CLOCK_IN_OMAP343X,
2672         .clkdm          = { .name = "per_clkdm" },
2673         .recalc         = &followparent_recalc,
2674 };
2675
2676 static struct clk gpio3_fck = {
2677         .name           = "gpio3_fck",
2678         .parent         = &per_32k_alwon_fck,
2679         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2680         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2681         .flags          = CLOCK_IN_OMAP343X,
2682         .clkdm          = { .name = "per_clkdm" },
2683         .recalc         = &followparent_recalc,
2684 };
2685
2686 static struct clk gpio2_fck = {
2687         .name           = "gpio2_fck",
2688         .parent         = &per_32k_alwon_fck,
2689         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2690         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2691         .flags          = CLOCK_IN_OMAP343X,
2692         .clkdm          = { .name = "per_clkdm" },
2693         .recalc         = &followparent_recalc,
2694 };
2695
2696 static struct clk wdt3_fck = {
2697         .name           = "wdt3_fck",
2698         .parent         = &per_32k_alwon_fck,
2699         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2700         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2701         .flags          = CLOCK_IN_OMAP343X,
2702         .clkdm          = { .name = "per_clkdm" },
2703         .recalc         = &followparent_recalc,
2704 };
2705
2706 static struct clk per_l4_ick = {
2707         .name           = "per_l4_ick",
2708         .parent         = &l4_ick,
2709         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2710                                 PARENT_CONTROLS_CLOCK,
2711         .clkdm          = { .name = "per_clkdm" },
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk gpio6_ick = {
2716         .name           = "gpio6_ick",
2717         .parent         = &per_l4_ick,
2718         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2720         .flags          = CLOCK_IN_OMAP343X,
2721         .clkdm          = { .name = "per_clkdm" },
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk gpio5_ick = {
2726         .name           = "gpio5_ick",
2727         .parent         = &per_l4_ick,
2728         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2730         .flags          = CLOCK_IN_OMAP343X,
2731         .clkdm          = { .name = "per_clkdm" },
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static struct clk gpio4_ick = {
2736         .name           = "gpio4_ick",
2737         .parent         = &per_l4_ick,
2738         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2740         .flags          = CLOCK_IN_OMAP343X,
2741         .clkdm          = { .name = "per_clkdm" },
2742         .recalc         = &followparent_recalc,
2743 };
2744
2745 static struct clk gpio3_ick = {
2746         .name           = "gpio3_ick",
2747         .parent         = &per_l4_ick,
2748         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2750         .flags          = CLOCK_IN_OMAP343X,
2751         .clkdm          = { .name = "per_clkdm" },
2752         .recalc         = &followparent_recalc,
2753 };
2754
2755 static struct clk gpio2_ick = {
2756         .name           = "gpio2_ick",
2757         .parent         = &per_l4_ick,
2758         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2760         .flags          = CLOCK_IN_OMAP343X,
2761         .clkdm          = { .name = "per_clkdm" },
2762         .recalc         = &followparent_recalc,
2763 };
2764
2765 static struct clk wdt3_ick = {
2766         .name           = "wdt3_ick",
2767         .parent         = &per_l4_ick,
2768         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2770         .flags          = CLOCK_IN_OMAP343X,
2771         .clkdm          = { .name = "per_clkdm" },
2772         .recalc         = &followparent_recalc,
2773 };
2774
2775 static struct clk uart3_ick = {
2776         .name           = "uart3_ick",
2777         .parent         = &per_l4_ick,
2778         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2780         .flags          = CLOCK_IN_OMAP343X,
2781         .clkdm          = { .name = "per_clkdm" },
2782         .recalc         = &followparent_recalc,
2783 };
2784
2785 static struct clk gpt9_ick = {
2786         .name           = "gpt9_ick",
2787         .parent         = &per_l4_ick,
2788         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2790         .flags          = CLOCK_IN_OMAP343X,
2791         .clkdm          = { .name = "per_clkdm" },
2792         .recalc         = &followparent_recalc,
2793 };
2794
2795 static struct clk gpt8_ick = {
2796         .name           = "gpt8_ick",
2797         .parent         = &per_l4_ick,
2798         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2799         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2800         .flags          = CLOCK_IN_OMAP343X,
2801         .clkdm          = { .name = "per_clkdm" },
2802         .recalc         = &followparent_recalc,
2803 };
2804
2805 static struct clk gpt7_ick = {
2806         .name           = "gpt7_ick",
2807         .parent         = &per_l4_ick,
2808         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2809         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2810         .flags          = CLOCK_IN_OMAP343X,
2811         .clkdm          = { .name = "per_clkdm" },
2812         .recalc         = &followparent_recalc,
2813 };
2814
2815 static struct clk gpt6_ick = {
2816         .name           = "gpt6_ick",
2817         .parent         = &per_l4_ick,
2818         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2820         .flags          = CLOCK_IN_OMAP343X,
2821         .clkdm          = { .name = "per_clkdm" },
2822         .recalc         = &followparent_recalc,
2823 };
2824
2825 static struct clk gpt5_ick = {
2826         .name           = "gpt5_ick",
2827         .parent         = &per_l4_ick,
2828         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2829         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2830         .flags          = CLOCK_IN_OMAP343X,
2831         .clkdm          = { .name = "per_clkdm" },
2832         .recalc         = &followparent_recalc,
2833 };
2834
2835 static struct clk gpt4_ick = {
2836         .name           = "gpt4_ick",
2837         .parent         = &per_l4_ick,
2838         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2839         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2840         .flags          = CLOCK_IN_OMAP343X,
2841         .clkdm          = { .name = "per_clkdm" },
2842         .recalc         = &followparent_recalc,
2843 };
2844
2845 static struct clk gpt3_ick = {
2846         .name           = "gpt3_ick",
2847         .parent         = &per_l4_ick,
2848         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2849         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2850         .flags          = CLOCK_IN_OMAP343X,
2851         .clkdm          = { .name = "per_clkdm" },
2852         .recalc         = &followparent_recalc,
2853 };
2854
2855 static struct clk gpt2_ick = {
2856         .name           = "gpt2_ick",
2857         .parent         = &per_l4_ick,
2858         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2859         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2860         .flags          = CLOCK_IN_OMAP343X,
2861         .clkdm          = { .name = "per_clkdm" },
2862         .recalc         = &followparent_recalc,
2863 };
2864
2865 static struct clk mcbsp2_ick = {
2866         .name           = "mcbsp_ick",
2867         .id             = 2,
2868         .parent         = &per_l4_ick,
2869         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2870         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2871         .flags          = CLOCK_IN_OMAP343X,
2872         .clkdm          = { .name = "per_clkdm" },
2873         .recalc         = &followparent_recalc,
2874 };
2875
2876 static struct clk mcbsp3_ick = {
2877         .name           = "mcbsp_ick",
2878         .id             = 3,
2879         .parent         = &per_l4_ick,
2880         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2881         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2882         .flags          = CLOCK_IN_OMAP343X,
2883         .clkdm          = { .name = "per_clkdm" },
2884         .recalc         = &followparent_recalc,
2885 };
2886
2887 static struct clk mcbsp4_ick = {
2888         .name           = "mcbsp_ick",
2889         .id             = 4,
2890         .parent         = &per_l4_ick,
2891         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2892         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2893         .flags          = CLOCK_IN_OMAP343X,
2894         .clkdm          = { .name = "per_clkdm" },
2895         .recalc         = &followparent_recalc,
2896 };
2897
2898 static const struct clksel mcbsp_234_clksel[] = {
2899         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2900         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2901         { .parent = NULL }
2902 };
2903
2904 static struct clk mcbsp2_fck = {
2905         .name           = "mcbsp_fck",
2906         .id             = 2,
2907         .init           = &omap2_init_clksel_parent,
2908         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2909         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2910         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2911         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2912         .clksel         = mcbsp_234_clksel,
2913         .flags          = CLOCK_IN_OMAP343X,
2914         .clkdm          = { .name = "per_clkdm" },
2915         .recalc         = &omap2_clksel_recalc,
2916 };
2917
2918 static struct clk mcbsp3_fck = {
2919         .name           = "mcbsp_fck",
2920         .id             = 3,
2921         .init           = &omap2_init_clksel_parent,
2922         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2923         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2924         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2925         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2926         .clksel         = mcbsp_234_clksel,
2927         .flags          = CLOCK_IN_OMAP343X,
2928         .clkdm          = { .name = "per_clkdm" },
2929         .recalc         = &omap2_clksel_recalc,
2930 };
2931
2932 static struct clk mcbsp4_fck = {
2933         .name           = "mcbsp_fck",
2934         .id             = 4,
2935         .init           = &omap2_init_clksel_parent,
2936         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2937         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2938         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2939         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2940         .clksel         = mcbsp_234_clksel,
2941         .flags          = CLOCK_IN_OMAP343X,
2942         .clkdm          = { .name = "per_clkdm" },
2943         .recalc         = &omap2_clksel_recalc,
2944 };
2945
2946 /* EMU clocks */
2947
2948 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2949
2950 static const struct clksel_rate emu_src_sys_rates[] = {
2951         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2952         { .div = 0 },
2953 };
2954
2955 static const struct clksel_rate emu_src_core_rates[] = {
2956         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2957         { .div = 0 },
2958 };
2959
2960 static const struct clksel_rate emu_src_per_rates[] = {
2961         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2962         { .div = 0 },
2963 };
2964
2965 static const struct clksel_rate emu_src_mpu_rates[] = {
2966         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2967         { .div = 0 },
2968 };
2969
2970 static const struct clksel emu_src_clksel[] = {
2971         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2972         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2973         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2974         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2975         { .parent = NULL },
2976 };
2977
2978 /*
2979  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2980  * to switch the source of some of the EMU clocks.
2981  * XXX Are there CLKEN bits for these EMU clks?
2982  */
2983 static struct clk emu_src_ck = {
2984         .name           = "emu_src_ck",
2985         .init           = &omap2_init_clksel_parent,
2986         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2987         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2988         .clksel         = emu_src_clksel,
2989         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2990         .clkdm          = { .name = "emu_clkdm" },
2991         .recalc         = &omap2_clksel_recalc,
2992 };
2993
2994 static const struct clksel_rate pclk_emu_rates[] = {
2995         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2996         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2997         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2998         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2999         { .div = 0 },
3000 };
3001
3002 static const struct clksel pclk_emu_clksel[] = {
3003         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3004         { .parent = NULL },
3005 };
3006
3007 static struct clk pclk_fck = {
3008         .name           = "pclk_fck",
3009         .init           = &omap2_init_clksel_parent,
3010         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3011         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3012         .clksel         = pclk_emu_clksel,
3013         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3014         .clkdm          = { .name = "emu_clkdm" },
3015         .recalc         = &omap2_clksel_recalc,
3016 };
3017
3018 static const struct clksel_rate pclkx2_emu_rates[] = {
3019         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3020         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3021         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3022         { .div = 0 },
3023 };
3024
3025 static const struct clksel pclkx2_emu_clksel[] = {
3026         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3027         { .parent = NULL },
3028 };
3029
3030 static struct clk pclkx2_fck = {
3031         .name           = "pclkx2_fck",
3032         .init           = &omap2_init_clksel_parent,
3033         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3034         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3035         .clksel         = pclkx2_emu_clksel,
3036         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3037         .clkdm          = { .name = "emu_clkdm" },
3038         .recalc         = &omap2_clksel_recalc,
3039 };
3040
3041 static const struct clksel atclk_emu_clksel[] = {
3042         { .parent = &emu_src_ck, .rates = div2_rates },
3043         { .parent = NULL },
3044 };
3045
3046 static struct clk atclk_fck = {
3047         .name           = "atclk_fck",
3048         .init           = &omap2_init_clksel_parent,
3049         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3050         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3051         .clksel         = atclk_emu_clksel,
3052         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3053         .clkdm          = { .name = "emu_clkdm" },
3054         .recalc         = &omap2_clksel_recalc,
3055 };
3056
3057 static struct clk traceclk_src_fck = {
3058         .name           = "traceclk_src_fck",
3059         .init           = &omap2_init_clksel_parent,
3060         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3061         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3062         .clksel         = emu_src_clksel,
3063         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3064         .clkdm          = { .name = "emu_clkdm" },
3065         .recalc         = &omap2_clksel_recalc,
3066 };
3067
3068 static const struct clksel_rate traceclk_rates[] = {
3069         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3070         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3071         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3072         { .div = 0 },
3073 };
3074
3075 static const struct clksel traceclk_clksel[] = {
3076         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3077         { .parent = NULL },
3078 };
3079
3080 static struct clk traceclk_fck = {
3081         .name           = "traceclk_fck",
3082         .init           = &omap2_init_clksel_parent,
3083         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3084         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3085         .clksel         = traceclk_clksel,
3086         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3087         .clkdm          = { .name = "emu_clkdm" },
3088         .recalc         = &omap2_clksel_recalc,
3089 };
3090
3091 /* SR clocks */
3092
3093 /* SmartReflex fclk (VDD1) */
3094 static struct clk sr1_fck = {
3095         .name           = "sr1_fck",
3096         .parent         = &sys_ck,
3097         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3098         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3099         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3100         .clkdm          = { .name = "prm_clkdm" },
3101         .recalc         = &followparent_recalc,
3102 };
3103
3104 /* SmartReflex fclk (VDD2) */
3105 static struct clk sr2_fck = {
3106         .name           = "sr2_fck",
3107         .parent         = &sys_ck,
3108         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3109         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3110         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3111         .clkdm          = { .name = "prm_clkdm" },
3112         .recalc         = &followparent_recalc,
3113 };
3114
3115 static struct clk sr_l4_ick = {
3116         .name           = "sr_l4_ick",
3117         .parent         = &l4_ick,
3118         .flags          = CLOCK_IN_OMAP343X,
3119         .clkdm          = { .name = "core_l4_clkdm" },
3120         .recalc         = &followparent_recalc,
3121 };
3122
3123 /* SECURE_32K_FCK clocks */
3124
3125 /* XXX This clock no longer exists in 3430 TRM rev F */
3126 static struct clk gpt12_fck = {
3127         .name           = "gpt12_fck",
3128         .parent         = &secure_32k_fck,
3129         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3130         .clkdm          = { .name = "prm_clkdm" },
3131         .recalc         = &followparent_recalc,
3132 };
3133
3134 static struct clk wdt1_fck = {
3135         .name           = "wdt1_fck",
3136         .parent         = &secure_32k_fck,
3137         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3138         .clkdm          = { .name = "prm_clkdm" },
3139         .recalc         = &followparent_recalc,
3140 };
3141
3142 static struct clk *onchip_34xx_clks[] __initdata = {
3143         &omap_32k_fck,
3144         &virt_12m_ck,
3145         &virt_13m_ck,
3146         &virt_16_8m_ck,
3147         &virt_19_2m_ck,
3148         &virt_26m_ck,
3149         &virt_38_4m_ck,
3150         &osc_sys_ck,
3151         &sys_ck,
3152         &sys_altclk,
3153         &mcbsp_clks,
3154         &sys_clkout1,
3155         &dpll1_ck,
3156         &dpll1_x2_ck,
3157         &dpll1_x2m2_ck,
3158         &dpll2_ck,
3159         &dpll2_m2_ck,
3160         &dpll3_ck,
3161         &core_ck,
3162         &dpll3_x2_ck,
3163         &dpll3_m2_ck,
3164         &dpll3_m2x2_ck,
3165         &dpll3_m3_ck,
3166         &dpll3_m3x2_ck,
3167         &emu_core_alwon_ck,
3168         &dpll4_ck,
3169         &dpll4_x2_ck,
3170         &omap_96m_alwon_fck,
3171         &omap_96m_fck,
3172         &cm_96m_fck,
3173         &virt_omap_54m_fck,
3174         &omap_54m_fck,
3175         &omap_48m_fck,
3176         &omap_12m_fck,
3177         &dpll4_m2_ck,
3178         &dpll4_m2x2_ck,
3179         &dpll4_m3_ck,
3180         &dpll4_m3x2_ck,
3181         &dpll4_m4_ck,
3182         &dpll4_m4x2_ck,
3183         &dpll4_m5_ck,
3184         &dpll4_m5x2_ck,
3185         &dpll4_m6_ck,
3186         &dpll4_m6x2_ck,
3187         &emu_per_alwon_ck,
3188         &dpll5_ck,
3189         &dpll5_m2_ck,
3190         &omap_120m_fck,
3191         &clkout2_src_ck,
3192         &sys_clkout2,
3193         &corex2_fck,
3194         &dpll1_fck,
3195         &mpu_ck,
3196         &arm_fck,
3197         &emu_mpu_alwon_ck,
3198         &dpll2_fck,
3199         &iva2_ck,
3200         &l3_ick,
3201         &l4_ick,
3202         &rm_ick,
3203         &gfx_l3_ck,
3204         &gfx_l3_fck,
3205         &gfx_l3_ick,
3206         &gfx_cg1_ck,
3207         &gfx_cg2_ck,
3208         &sgx_fck,
3209         &sgx_ick,
3210         &d2d_26m_fck,
3211         &gpt10_fck,
3212         &gpt11_fck,
3213         &cpefuse_fck,
3214         &ts_fck,
3215         &usbtll_fck,
3216         &core_96m_fck,
3217         &mmchs3_fck,
3218         &mmchs2_fck,
3219         &mspro_fck,
3220         &mmchs1_fck,
3221         &i2c3_fck,
3222         &i2c2_fck,
3223         &i2c1_fck,
3224         &mcbsp5_fck,
3225         &mcbsp1_fck,
3226         &core_48m_fck,
3227         &mcspi4_fck,
3228         &mcspi3_fck,
3229         &mcspi2_fck,
3230         &mcspi1_fck,
3231         &uart2_fck,
3232         &uart1_fck,
3233         &fshostusb_fck,
3234         &core_12m_fck,
3235         &hdq_fck,
3236         &ssi_ssr_fck,
3237         &ssi_sst_fck,
3238         &core_l3_ick,
3239         &hsotgusb_ick,
3240         &sdrc_ick,
3241         &gpmc_fck,
3242         &security_l3_ick,
3243         &pka_ick,
3244         &core_l4_ick,
3245         &usbtll_ick,
3246         &mmchs3_ick,
3247         &icr_ick,
3248         &aes2_ick,
3249         &sha12_ick,
3250         &des2_ick,
3251         &mmchs2_ick,
3252         &mmchs1_ick,
3253         &mspro_ick,
3254         &hdq_ick,
3255         &mcspi4_ick,
3256         &mcspi3_ick,
3257         &mcspi2_ick,
3258         &mcspi1_ick,
3259         &i2c3_ick,
3260         &i2c2_ick,
3261         &i2c1_ick,
3262         &uart2_ick,
3263         &uart1_ick,
3264         &gpt11_ick,
3265         &gpt10_ick,
3266         &mcbsp5_ick,
3267         &mcbsp1_ick,
3268         &fac_ick,
3269         &mailboxes_ick,
3270         &omapctrl_ick,
3271         &ssi_l4_ick,
3272         &ssi_ick,
3273         &usb_l4_ick,
3274         &security_l4_ick2,
3275         &aes1_ick,
3276         &rng_ick,
3277         &sha11_ick,
3278         &des1_ick,
3279         &dss1_alwon_fck,
3280         &dss_tv_fck,
3281         &dss_96m_fck,
3282         &dss2_alwon_fck,
3283         &dss_ick,
3284         &cam_mclk,
3285         &cam_ick,
3286         &csi2_96m_fck,
3287         &usbhost_120m_fck,
3288         &usbhost_48m_fck,
3289         &usbhost_ick,
3290         &usim_fck,
3291         &gpt1_fck,
3292         &wkup_32k_fck,
3293         &gpio1_fck,
3294         &wdt2_fck,
3295         &wkup_l4_ick,
3296         &usim_ick,
3297         &wdt2_ick,
3298         &wdt1_ick,
3299         &gpio1_ick,
3300         &omap_32ksync_ick,
3301         &gpt12_ick,
3302         &gpt1_ick,
3303         &per_96m_fck,
3304         &per_48m_fck,
3305         &uart3_fck,
3306         &gpt2_fck,
3307         &gpt3_fck,
3308         &gpt4_fck,
3309         &gpt5_fck,
3310         &gpt6_fck,
3311         &gpt7_fck,
3312         &gpt8_fck,
3313         &gpt9_fck,
3314         &per_32k_alwon_fck,
3315         &gpio6_fck,
3316         &gpio5_fck,
3317         &gpio4_fck,
3318         &gpio3_fck,
3319         &gpio2_fck,
3320         &wdt3_fck,
3321         &per_l4_ick,
3322         &gpio6_ick,
3323         &gpio5_ick,
3324         &gpio4_ick,
3325         &gpio3_ick,
3326         &gpio2_ick,
3327         &wdt3_ick,
3328         &uart3_ick,
3329         &gpt9_ick,
3330         &gpt8_ick,
3331         &gpt7_ick,
3332         &gpt6_ick,
3333         &gpt5_ick,
3334         &gpt4_ick,
3335         &gpt3_ick,
3336         &gpt2_ick,
3337         &mcbsp2_ick,
3338         &mcbsp3_ick,
3339         &mcbsp4_ick,
3340         &mcbsp2_fck,
3341         &mcbsp3_fck,
3342         &mcbsp4_fck,
3343         &emu_src_ck,
3344         &pclk_fck,
3345         &pclkx2_fck,
3346         &atclk_fck,
3347         &traceclk_src_fck,
3348         &traceclk_fck,
3349         &sr1_fck,
3350         &sr2_fck,
3351         &sr_l4_ick,
3352         &secure_32k_fck,
3353         &gpt12_fck,
3354         &wdt1_fck,
3355 };
3356
3357 #endif