2 * arch/arm/mach-at91/at572d940hf_devices.c
4 * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
6 * Copyright (C) 2005 David Brownell
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
30 #include <mach/board.h>
31 #include <mach/gpio.h>
32 #include <mach/at572d940hf.h>
33 #include <mach/at572d940hf_matrix.h>
34 #include <mach/at91sam9_smc.h>
40 /* --------------------------------------------------------------------
42 * -------------------------------------------------------------------- */
44 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
45 static u64 ohci_dmamask = DMA_BIT_MASK(32);
46 static struct at91_usbh_data usbh_data;
48 static struct resource usbh_resources[] = {
50 .start = AT572D940HF_UHP_BASE,
51 .end = AT572D940HF_UHP_BASE + SZ_1M - 1,
52 .flags = IORESOURCE_MEM,
55 .start = AT572D940HF_ID_UHP,
56 .end = AT572D940HF_ID_UHP,
57 .flags = IORESOURCE_IRQ,
61 static struct platform_device at572d940hf_usbh_device = {
65 .dma_mask = &ohci_dmamask,
66 .coherent_dma_mask = DMA_BIT_MASK(32),
67 .platform_data = &usbh_data,
69 .resource = usbh_resources,
70 .num_resources = ARRAY_SIZE(usbh_resources),
73 void __init at91_add_device_usbh(struct at91_usbh_data *data)
79 platform_device_register(&at572d940hf_usbh_device);
83 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
87 /* --------------------------------------------------------------------
89 * -------------------------------------------------------------------- */
91 #ifdef CONFIG_USB_GADGET_AT91
92 static struct at91_udc_data udc_data;
94 static struct resource udc_resources[] = {
96 .start = AT572D940HF_BASE_UDP,
97 .end = AT572D940HF_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
101 .start = AT572D940HF_ID_UDP,
102 .end = AT572D940HF_ID_UDP,
103 .flags = IORESOURCE_IRQ,
107 static struct platform_device at572d940hf_udc_device = {
111 .platform_data = &udc_data,
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
117 void __init at91_add_device_udc(struct at91_udc_data *data)
122 if (data->vbus_pin) {
123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
127 /* Pullup pin is handled internally */
130 platform_device_register(&at572d940hf_udc_device);
133 void __init at91_add_device_udc(struct at91_udc_data *data) {}
137 /* --------------------------------------------------------------------
139 * -------------------------------------------------------------------- */
141 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
142 static u64 eth_dmamask = DMA_BIT_MASK(32);
143 static struct at91_eth_data eth_data;
145 static struct resource eth_resources[] = {
147 .start = AT572D940HF_BASE_EMAC,
148 .end = AT572D940HF_BASE_EMAC + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
152 .start = AT572D940HF_ID_EMAC,
153 .end = AT572D940HF_ID_EMAC,
154 .flags = IORESOURCE_IRQ,
158 static struct platform_device at572d940hf_eth_device = {
162 .dma_mask = ð_dmamask,
163 .coherent_dma_mask = DMA_BIT_MASK(32),
164 .platform_data = ð_data,
166 .resource = eth_resources,
167 .num_resources = ARRAY_SIZE(eth_resources),
170 void __init at91_add_device_eth(struct at91_eth_data *data)
175 if (data->phy_irq_pin) {
176 at91_set_gpio_input(data->phy_irq_pin, 0);
177 at91_set_deglitch(data->phy_irq_pin, 1);
180 /* Only RMII is supported */
183 /* Pins used for RMII */
184 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */
185 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
186 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */
187 at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */
188 at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */
189 at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */
190 at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */
191 at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */
192 at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */
193 at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */
196 platform_device_register(&at572d940hf_eth_device);
199 void __init at91_add_device_eth(struct at91_eth_data *data) {}
203 /* --------------------------------------------------------------------
205 * -------------------------------------------------------------------- */
207 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
208 static u64 mmc_dmamask = DMA_BIT_MASK(32);
209 static struct at91_mmc_data mmc_data;
211 static struct resource mmc_resources[] = {
213 .start = AT572D940HF_BASE_MCI,
214 .end = AT572D940HF_BASE_MCI + SZ_16K - 1,
215 .flags = IORESOURCE_MEM,
218 .start = AT572D940HF_ID_MCI,
219 .end = AT572D940HF_ID_MCI,
220 .flags = IORESOURCE_IRQ,
224 static struct platform_device at572d940hf_mmc_device = {
228 .dma_mask = &mmc_dmamask,
229 .coherent_dma_mask = DMA_BIT_MASK(32),
230 .platform_data = &mmc_data,
232 .resource = mmc_resources,
233 .num_resources = ARRAY_SIZE(mmc_resources),
236 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
243 at91_set_gpio_input(data->det_pin, 1);
244 at91_set_deglitch(data->det_pin, 1);
247 at91_set_gpio_input(data->wp_pin, 1);
249 at91_set_gpio_output(data->vcc_pin, 0);
252 at91_set_A_periph(AT91_PIN_PC22, 0);
255 at91_set_A_periph(AT91_PIN_PC23, 1);
257 /* DAT0, maybe DAT1..DAT3 */
258 at91_set_A_periph(AT91_PIN_PC24, 1);
260 at91_set_A_periph(AT91_PIN_PC25, 1);
261 at91_set_A_periph(AT91_PIN_PC26, 1);
262 at91_set_A_periph(AT91_PIN_PC27, 1);
266 platform_device_register(&at572d940hf_mmc_device);
269 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
273 /* --------------------------------------------------------------------
275 * -------------------------------------------------------------------- */
277 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
278 static struct atmel_nand_data nand_data;
280 #define NAND_BASE AT91_CHIPSELECT_3
282 static struct resource nand_resources[] = {
285 .end = NAND_BASE + SZ_256M - 1,
286 .flags = IORESOURCE_MEM,
290 static struct platform_device at572d940hf_nand_device = {
291 .name = "atmel_nand",
294 .platform_data = &nand_data,
296 .resource = nand_resources,
297 .num_resources = ARRAY_SIZE(nand_resources),
300 void __init at91_add_device_nand(struct atmel_nand_data *data)
307 csa = at91_sys_read(AT91_MATRIX_EBICSA);
308 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
311 if (data->enable_pin)
312 at91_set_gpio_output(data->enable_pin, 1);
316 at91_set_gpio_input(data->rdy_pin, 1);
318 /* card detect pin */
320 at91_set_gpio_input(data->det_pin, 1);
322 at91_set_A_periph(AT91_PIN_PB28, 0); /* A[22] */
323 at91_set_B_periph(AT91_PIN_PA28, 0); /* NANDOE */
324 at91_set_B_periph(AT91_PIN_PA29, 0); /* NANDWE */
327 platform_device_register(&at572d940hf_nand_device);
331 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
335 /* --------------------------------------------------------------------
337 * -------------------------------------------------------------------- */
340 * Prefer the GPIO code since the TWI controller isn't robust
341 * (gets overruns and underruns under load) and can only issue
342 * repeated STARTs in one scenario (the driver doesn't yet handle them).
345 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
347 static struct i2c_gpio_platform_data pdata = {
348 .sda_pin = AT91_PIN_PC7,
349 .sda_is_open_drain = 1,
350 .scl_pin = AT91_PIN_PC8,
351 .scl_is_open_drain = 1,
352 .udelay = 2, /* ~100 kHz */
355 static struct platform_device at572d940hf_twi_device {
358 .dev.platform_data = &pdata,
361 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
363 at91_set_GPIO_periph(AT91_PIN_PC7, 1); /* TWD (SDA) */
364 at91_set_multi_drive(AT91_PIN_PC7, 1);
366 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
367 at91_set_multi_drive(AT91_PIN_PC8, 1);
369 i2c_register_board_info(0, devices, nr_devices);
370 platform_device_register(&at572d940hf_twi_device);
373 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
375 static struct resource twi0_resources[] = {
377 .start = AT572D940HF_BASE_TWI0,
378 .end = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
379 .flags = IORESOURCE_MEM,
382 .start = AT572D940HF_ID_TWI0,
383 .end = AT572D940HF_ID_TWI0,
384 .flags = IORESOURCE_IRQ,
388 static struct platform_device at572d940hf_twi0_device = {
391 .resource = twi0_resources,
392 .num_resources = ARRAY_SIZE(twi0_resources),
395 static struct resource twi1_resources[] = {
397 .start = AT572D940HF_BASE_TWI1,
398 .end = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
399 .flags = IORESOURCE_MEM,
402 .start = AT572D940HF_ID_TWI1,
403 .end = AT572D940HF_ID_TWI1,
404 .flags = IORESOURCE_IRQ,
408 static struct platform_device at572d940hf_twi1_device = {
411 .resource = twi1_resources,
412 .num_resources = ARRAY_SIZE(twi1_resources),
415 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
417 /* pins used for TWI0 interface */
418 at91_set_A_periph(AT91_PIN_PC7, 0); /* TWD */
419 at91_set_multi_drive(AT91_PIN_PC7, 1);
421 at91_set_A_periph(AT91_PIN_PC8, 0); /* TWCK */
422 at91_set_multi_drive(AT91_PIN_PC8, 1);
424 /* pins used for TWI1 interface */
425 at91_set_A_periph(AT91_PIN_PC20, 0); /* TWD */
426 at91_set_multi_drive(AT91_PIN_PC20, 1);
428 at91_set_A_periph(AT91_PIN_PC21, 0); /* TWCK */
429 at91_set_multi_drive(AT91_PIN_PC21, 1);
431 i2c_register_board_info(0, devices, nr_devices);
432 platform_device_register(&at572d940hf_twi0_device);
433 platform_device_register(&at572d940hf_twi1_device);
436 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
440 /* --------------------------------------------------------------------
442 * -------------------------------------------------------------------- */
444 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
445 static u64 spi_dmamask = DMA_BIT_MASK(32);
447 static struct resource spi0_resources[] = {
449 .start = AT572D940HF_BASE_SPI0,
450 .end = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
451 .flags = IORESOURCE_MEM,
454 .start = AT572D940HF_ID_SPI0,
455 .end = AT572D940HF_ID_SPI0,
456 .flags = IORESOURCE_IRQ,
460 static struct platform_device at572d940hf_spi0_device = {
464 .dma_mask = &spi_dmamask,
465 .coherent_dma_mask = DMA_BIT_MASK(32),
467 .resource = spi0_resources,
468 .num_resources = ARRAY_SIZE(spi0_resources),
471 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
473 static struct resource spi1_resources[] = {
475 .start = AT572D940HF_BASE_SPI1,
476 .end = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
477 .flags = IORESOURCE_MEM,
480 .start = AT572D940HF_ID_SPI1,
481 .end = AT572D940HF_ID_SPI1,
482 .flags = IORESOURCE_IRQ,
486 static struct platform_device at572d940hf_spi1_device = {
490 .dma_mask = &spi_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(32),
493 .resource = spi1_resources,
494 .num_resources = ARRAY_SIZE(spi1_resources),
497 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
499 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
502 unsigned long cs_pin;
503 short enable_spi0 = 0;
504 short enable_spi1 = 0;
506 /* Choose SPI chip-selects */
507 for (i = 0; i < nr_devices; i++) {
508 if (devices[i].controller_data)
509 cs_pin = (unsigned long) devices[i].controller_data;
510 else if (devices[i].bus_num == 0)
511 cs_pin = spi0_standard_cs[devices[i].chip_select];
513 cs_pin = spi1_standard_cs[devices[i].chip_select];
515 if (devices[i].bus_num == 0)
520 /* enable chip-select pin */
521 at91_set_gpio_output(cs_pin, 1);
523 /* pass chip-select pin to driver */
524 devices[i].controller_data = (void *) cs_pin;
527 spi_register_board_info(devices, nr_devices);
529 /* Configure SPI bus(es) */
531 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
532 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
533 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
535 platform_device_register(&at572d940hf_spi0_device);
538 at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI1_MISO */
539 at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI1_MOSI */
540 at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI1_SPCK */
542 platform_device_register(&at572d940hf_spi1_device);
546 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
550 /* --------------------------------------------------------------------
551 * Timer/Counter blocks
552 * -------------------------------------------------------------------- */
554 #ifdef CONFIG_ATMEL_TCLIB
556 static struct resource tcb_resources[] = {
558 .start = AT572D940HF_BASE_TCB,
559 .end = AT572D940HF_BASE_TCB + SZ_16K - 1,
560 .flags = IORESOURCE_MEM,
563 .start = AT572D940HF_ID_TC0,
564 .end = AT572D940HF_ID_TC0,
565 .flags = IORESOURCE_IRQ,
568 .start = AT572D940HF_ID_TC1,
569 .end = AT572D940HF_ID_TC1,
570 .flags = IORESOURCE_IRQ,
573 .start = AT572D940HF_ID_TC2,
574 .end = AT572D940HF_ID_TC2,
575 .flags = IORESOURCE_IRQ,
579 static struct platform_device at572d940hf_tcb_device = {
582 .resource = tcb_resources,
583 .num_resources = ARRAY_SIZE(tcb_resources),
586 static void __init at91_add_device_tc(void)
588 platform_device_register(&at572d940hf_tcb_device);
591 static void __init at91_add_device_tc(void) { }
595 /* --------------------------------------------------------------------
597 * -------------------------------------------------------------------- */
599 static struct resource rtt_resources[] = {
601 .start = AT91_BASE_SYS + AT91_RTT,
602 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
603 .flags = IORESOURCE_MEM,
607 static struct platform_device at572d940hf_rtt_device = {
610 .resource = rtt_resources,
611 .num_resources = ARRAY_SIZE(rtt_resources),
614 static void __init at91_add_device_rtt(void)
616 platform_device_register(&at572d940hf_rtt_device);
620 /* --------------------------------------------------------------------
622 * -------------------------------------------------------------------- */
624 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
625 static struct platform_device at572d940hf_wdt_device = {
631 static void __init at91_add_device_watchdog(void)
633 platform_device_register(&at572d940hf_wdt_device);
636 static void __init at91_add_device_watchdog(void) {}
640 /* --------------------------------------------------------------------
642 * -------------------------------------------------------------------- */
644 #if defined(CONFIG_SERIAL_ATMEL)
645 static struct resource dbgu_resources[] = {
647 .start = AT91_VA_BASE_SYS + AT91_DBGU,
648 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
649 .flags = IORESOURCE_MEM,
652 .start = AT91_ID_SYS,
654 .flags = IORESOURCE_IRQ,
658 static struct atmel_uart_data dbgu_data = {
660 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
661 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
664 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
666 static struct platform_device at572d940hf_dbgu_device = {
667 .name = "atmel_usart",
670 .dma_mask = &dbgu_dmamask,
671 .coherent_dma_mask = DMA_BIT_MASK(32),
672 .platform_data = &dbgu_data,
674 .resource = dbgu_resources,
675 .num_resources = ARRAY_SIZE(dbgu_resources),
678 static inline void configure_dbgu_pins(void)
680 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
681 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
684 static struct resource uart0_resources[] = {
686 .start = AT572D940HF_BASE_US0,
687 .end = AT572D940HF_BASE_US0 + SZ_16K - 1,
688 .flags = IORESOURCE_MEM,
691 .start = AT572D940HF_ID_US0,
692 .end = AT572D940HF_ID_US0,
693 .flags = IORESOURCE_IRQ,
697 static struct atmel_uart_data uart0_data = {
702 static u64 uart0_dmamask = DMA_BIT_MASK(32);
704 static struct platform_device at572d940hf_uart0_device = {
705 .name = "atmel_usart",
708 .dma_mask = &uart0_dmamask,
709 .coherent_dma_mask = DMA_BIT_MASK(32),
710 .platform_data = &uart0_data,
712 .resource = uart0_resources,
713 .num_resources = ARRAY_SIZE(uart0_resources),
716 static inline void configure_usart0_pins(unsigned pins)
718 at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */
719 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
721 if (pins & ATMEL_UART_RTS)
722 at91_set_A_periph(AT91_PIN_PA10, 0); /* RTS0 */
723 if (pins & ATMEL_UART_CTS)
724 at91_set_A_periph(AT91_PIN_PA9, 0); /* CTS0 */
727 static struct resource uart1_resources[] = {
729 .start = AT572D940HF_BASE_US1,
730 .end = AT572D940HF_BASE_US1 + SZ_16K - 1,
731 .flags = IORESOURCE_MEM,
734 .start = AT572D940HF_ID_US1,
735 .end = AT572D940HF_ID_US1,
736 .flags = IORESOURCE_IRQ,
740 static struct atmel_uart_data uart1_data = {
745 static u64 uart1_dmamask = DMA_BIT_MASK(32);
747 static struct platform_device at572d940hf_uart1_device = {
748 .name = "atmel_usart",
751 .dma_mask = &uart1_dmamask,
752 .coherent_dma_mask = DMA_BIT_MASK(32),
753 .platform_data = &uart1_data,
755 .resource = uart1_resources,
756 .num_resources = ARRAY_SIZE(uart1_resources),
759 static inline void configure_usart1_pins(unsigned pins)
761 at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */
762 at91_set_A_periph(AT91_PIN_PC9 , 0); /* RXD1 */
764 if (pins & ATMEL_UART_RTS)
765 at91_set_A_periph(AT91_PIN_PC12, 0); /* RTS1 */
766 if (pins & ATMEL_UART_CTS)
767 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS1 */
770 static struct resource uart2_resources[] = {
772 .start = AT572D940HF_BASE_US2,
773 .end = AT572D940HF_BASE_US2 + SZ_16K - 1,
774 .flags = IORESOURCE_MEM,
777 .start = AT572D940HF_ID_US2,
778 .end = AT572D940HF_ID_US2,
779 .flags = IORESOURCE_IRQ,
783 static struct atmel_uart_data uart2_data = {
788 static u64 uart2_dmamask = DMA_BIT_MASK(32);
790 static struct platform_device at572d940hf_uart2_device = {
791 .name = "atmel_usart",
794 .dma_mask = &uart2_dmamask,
795 .coherent_dma_mask = DMA_BIT_MASK(32),
796 .platform_data = &uart2_data,
798 .resource = uart2_resources,
799 .num_resources = ARRAY_SIZE(uart2_resources),
802 static inline void configure_usart2_pins(unsigned pins)
804 at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */
805 at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */
807 if (pins & ATMEL_UART_RTS)
808 at91_set_A_periph(AT91_PIN_PC17, 0); /* RTS2 */
809 if (pins & ATMEL_UART_CTS)
810 at91_set_A_periph(AT91_PIN_PC16, 0); /* CTS2 */
813 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
814 struct platform_device *atmel_default_console_device; /* the serial console device */
816 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
818 struct platform_device *pdev;
819 struct atmel_uart_data *pdata;
823 pdev = &at572d940hf_dbgu_device;
824 configure_dbgu_pins();
826 case AT572D940HF_ID_US0:
827 pdev = &at572d940hf_uart0_device;
828 configure_usart0_pins(pins);
830 case AT572D940HF_ID_US1:
831 pdev = &at572d940hf_uart1_device;
832 configure_usart1_pins(pins);
834 case AT572D940HF_ID_US2:
835 pdev = &at572d940hf_uart2_device;
836 configure_usart2_pins(pins);
841 pdata = pdev->dev.platform_data;
842 pdata->num = portnr; /* update to mapped ID */
844 if (portnr < ATMEL_MAX_UART)
845 at91_uarts[portnr] = pdev;
848 void __init at91_set_serial_console(unsigned portnr)
850 if (portnr < ATMEL_MAX_UART) {
851 atmel_default_console_device = at91_uarts[portnr];
852 at572d940hf_set_console_clock(portnr);
856 void __init at91_add_device_serial(void)
860 for (i = 0; i < ATMEL_MAX_UART; i++) {
862 platform_device_register(at91_uarts[i]);
865 if (!atmel_default_console_device)
866 printk(KERN_INFO "AT91: No default serial console defined.\n");
870 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
871 void __init at91_set_serial_console(unsigned portnr) {}
872 void __init at91_add_device_serial(void) {}
876 /* --------------------------------------------------------------------
878 * -------------------------------------------------------------------- */
881 static struct resource mAgic_resources[] = {
883 .start = AT91_MAGIC_PM_BASE,
884 .end = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
885 .flags = IORESOURCE_MEM,
888 .start = AT91_MAGIC_DM_I_BASE,
889 .end = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
890 .flags = IORESOURCE_MEM,
893 .start = AT91_MAGIC_DM_F_BASE,
894 .end = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
895 .flags = IORESOURCE_MEM,
898 .start = AT91_MAGIC_DM_DB_BASE,
899 .end = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
900 .flags = IORESOURCE_MEM,
903 .start = AT91_MAGIC_REGS_BASE,
904 .end = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
905 .flags = IORESOURCE_MEM,
908 .start = AT91_MAGIC_EXTPAGE_BASE,
909 .end = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
910 .flags = IORESOURCE_MEM,
913 .start = AT572D940HF_ID_MSIRQ0,
914 .end = AT572D940HF_ID_MSIRQ0,
915 .flags = IORESOURCE_IRQ,
918 .start = AT572D940HF_ID_MHALT,
919 .end = AT572D940HF_ID_MHALT,
920 .flags = IORESOURCE_IRQ,
923 .start = AT572D940HF_ID_MEXC,
924 .end = AT572D940HF_ID_MEXC,
925 .flags = IORESOURCE_IRQ,
928 .start = AT572D940HF_ID_MEDMA,
929 .end = AT572D940HF_ID_MEDMA,
930 .flags = IORESOURCE_IRQ,
934 static struct platform_device mAgic_device = {
937 .num_resources = ARRAY_SIZE(mAgic_resources),
938 .resource = mAgic_resources,
941 void __init at91_add_device_mAgic(void)
943 platform_device_register(&mAgic_device);
946 void __init at91_add_device_mAgic(void) {}
950 /* -------------------------------------------------------------------- */
953 * These devices are always present and don't need any board-specific
956 static int __init at91_add_standard_devices(void)
958 at91_add_device_rtt();
959 at91_add_device_watchdog();
960 at91_add_device_tc();
964 arch_initcall(at91_add_standard_devices);