arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13
  14 / {
  15         model = "TI DRA742";
  16         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  17
  18         memory {
  19                 device_type = "memory";
  20                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  21         };
  22
  23         evm_3v3_sd: fixedregulator-sd {
  24                 compatible = "regulator-fixed";
  25                 regulator-name = "evm_3v3_sd";
  26                 regulator-min-microvolt = <3300000>;
  27                 regulator-max-microvolt = <3300000>;
  28                 enable-active-high;
  29                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  30         };
  31
  32         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "evm_3v3_sw";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37         };
  38
  39         aic_dvdd: fixedregulator-aic_dvdd {
  40                 /* TPS77018DBVT */
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "aic_dvdd";
  43                 vin-supply = <&evm_3v3_sw>;
  44                 regulator-min-microvolt = <1800000>;
  45                 regulator-max-microvolt = <1800000>;
  46         };
  47
  48         extcon_usb1: extcon_usb1 {
  49                 compatible = "linux,extcon-usb-gpio";
  50                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  51         };
  52
  53         extcon_usb2: extcon_usb2 {
  54                 compatible = "linux,extcon-usb-gpio";
  55                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  56         };
  57
  58         vtt_fixed: fixedregulator-vtt {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "vtt_fixed";
  61                 regulator-min-microvolt = <1350000>;
  62                 regulator-max-microvolt = <1350000>;
  63                 regulator-always-on;
  64                 regulator-boot-on;
  65                 enable-active-high;
  66                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  67         };
  68
  69         sound0: sound@0 {
  70                 compatible = "simple-audio-card";
  71                 simple-audio-card,name = "DRA7xx-EVM";
  72                 simple-audio-card,widgets =
  73                         "Headphone", "Headphone Jack",
  74                         "Line", "Line Out",
  75                         "Microphone", "Mic Jack",
  76                         "Line", "Line In";
  77                 simple-audio-card,routing =
  78                         "Headphone Jack",       "HPLOUT",
  79                         "Headphone Jack",       "HPROUT",
  80                         "Line Out",             "LLOUT",
  81                         "Line Out",             "RLOUT",
  82                         "MIC3L",                "Mic Jack",
  83                         "MIC3R",                "Mic Jack",
  84                         "Mic Jack",             "Mic Bias",
  85                         "LINE1L",               "Line In",
  86                         "LINE1R",               "Line In";
  87                 simple-audio-card,format = "dsp_b";
  88                 simple-audio-card,bitclock-master = <&sound0_master>;
  89                 simple-audio-card,frame-master = <&sound0_master>;
  90                 simple-audio-card,bitclock-inversion;
  91
  92                 sound0_master: simple-audio-card,cpu {
  93                         sound-dai = <&mcasp3>;
  94                         system-clock-frequency = <5644800>;
  95                 };
  96
  97                 simple-audio-card,codec {
  98                         sound-dai = <&tlv320aic3106>;
  99                         clocks = <&atl_clkin2_ck>;
 100                 };
 101         };
 102 };
 103
 104 &dra7_pmx_core {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&vtt_pin>;
 107
 108         vtt_pin: pinmux_vtt_pin {
 109                 pinctrl-single,pins = <
 110                         0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
 111                 >;
 112         };
 113
 114         i2c1_pins: pinmux_i2c1_pins {
 115                 pinctrl-single,pins = <
 116                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
 117                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
 118                 >;
 119         };
 120
 121         i2c2_pins: pinmux_i2c2_pins {
 122                 pinctrl-single,pins = <
 123                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
 124                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
 125                 >;
 126         };
 127
 128         i2c3_pins: pinmux_i2c3_pins {
 129                 pinctrl-single,pins = <
 130                         0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
 131                         0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
 132                 >;
 133         };
 134
 135         mcspi1_pins: pinmux_mcspi1_pins {
 136                 pinctrl-single,pins = <
 137                         0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
 138                         0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
 139                         0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
 140                         0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
 141                         0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
 142                         0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
 143                 >;
 144         };
 145
 146         mcspi2_pins: pinmux_mcspi2_pins {
 147                 pinctrl-single,pins = <
 148                         0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
 149                         0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 150                         0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 151                         0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
 152                 >;
 153         };
 154
 155         uart1_pins: pinmux_uart1_pins {
 156                 pinctrl-single,pins = <
 157                         0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
 158                         0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
 159                         0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
 160                         0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
 161                 >;
 162         };
 163
 164         uart2_pins: pinmux_uart2_pins {
 165                 pinctrl-single,pins = <
 166                         0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 167                         0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
 168                         0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 169                         0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 170                 >;
 171         };
 172
 173         uart3_pins: pinmux_uart3_pins {
 174                 pinctrl-single,pins = <
 175                         0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 176                         0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 177                 >;
 178         };
 179
 180         qspi1_pins: pinmux_qspi1_pins {
 181                 pinctrl-single,pins = <
 182                         0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 183                         0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 184                         0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 185                         0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 186                         0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 187                         0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 188                         0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 189                         0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 190                         0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 191                         0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 192                 >;
 193         };
 194
 195         usb1_pins: pinmux_usb1_pins {
 196                 pinctrl-single,pins = <
 197                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 198                 >;
 199         };
 200
 201         usb2_pins: pinmux_usb2_pins {
 202                 pinctrl-single,pins = <
 203                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 204                 >;
 205         };
 206
 207         nand_flash_x16: nand_flash_x16 {
 208                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 209                  * So NAND flash requires following switch settings:
 210                  * SW5.9 (GPMC_WPN) = LOW
 211                  * SW5.1 (NAND_BOOTn) = HIGH */
 212                 pinctrl-single,pins = <
 213                         0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
 214                         0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
 215                         0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
 216                         0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
 217                         0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
 218                         0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
 219                         0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
 220                         0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
 221                         0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
 222                         0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
 223                         0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
 224                         0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
 225                         0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
 226                         0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
 227                         0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
 228                         0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
 229                         0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
 230                         0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
 231                         0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
 232                         0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
 233                         0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
 234                         0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
 235                 >;
 236         };
 237
 238         cpsw_default: cpsw_default {
 239                 pinctrl-single,pins = <
 240                         /* Slave 1 */
 241                         0x250 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txc.rgmii0_txc */
 242                         0x254 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txctl.rgmii0_txctl */
 243                         0x258 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_td3.rgmii0_txd3 */
 244                         0x25c (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd2.rgmii0_txd2 */
 245                         0x260 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd1.rgmii0_txd1 */
 246                         0x264 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd0.rgmii0_txd0 */
 247                         0x268 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxc.rgmii0_rxc */
 248                         0x26c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxctl.rgmii0_rxctl */
 249                         0x270 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd3.rgmii0_rxd3 */
 250                         0x274 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd2.rgmii0_rxd2 */
 251                         0x278 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd1.rgmii0_rxd1 */
 252                         0x27c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd0.rgmii0_rxd0 */
 253
 254                         /* Slave 2 */
 255                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 256                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 257                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 258                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 259                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 260                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 261                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 262                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 263                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 264                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 265                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 266                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 267                 >;
 268
 269         };
 270
 271         cpsw_sleep: cpsw_sleep {
 272                 pinctrl-single,pins = <
 273                         /* Slave 1 */
 274                         0x250 (MUX_MODE15)
 275                         0x254 (MUX_MODE15)
 276                         0x258 (MUX_MODE15)
 277                         0x25c (MUX_MODE15)
 278                         0x260 (MUX_MODE15)
 279                         0x264 (MUX_MODE15)
 280                         0x268 (MUX_MODE15)
 281                         0x26c (MUX_MODE15)
 282                         0x270 (MUX_MODE15)
 283                         0x274 (MUX_MODE15)
 284                         0x278 (MUX_MODE15)
 285                         0x27c (MUX_MODE15)
 286
 287                         /* Slave 2 */
 288                         0x198 (MUX_MODE15)
 289                         0x19c (MUX_MODE15)
 290                         0x1a0 (MUX_MODE15)
 291                         0x1a4 (MUX_MODE15)
 292                         0x1a8 (MUX_MODE15)
 293                         0x1ac (MUX_MODE15)
 294                         0x1b0 (MUX_MODE15)
 295                         0x1b4 (MUX_MODE15)
 296                         0x1b8 (MUX_MODE15)
 297                         0x1bc (MUX_MODE15)
 298                         0x1c0 (MUX_MODE15)
 299                         0x1c4 (MUX_MODE15)
 300                 >;
 301         };
 302
 303         davinci_mdio_default: davinci_mdio_default {
 304                 pinctrl-single,pins = <
 305                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 306                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 307                 >;
 308         };
 309
 310         davinci_mdio_sleep: davinci_mdio_sleep {
 311                 pinctrl-single,pins = <
 312                         0x23c (MUX_MODE15)
 313                         0x240 (MUX_MODE15)
 314                 >;
 315         };
 316
 317         dcan1_pins_default: dcan1_pins_default {
 318                 pinctrl-single,pins = <
 319                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 320                         0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 321                 >;
 322         };
 323
 324         dcan1_pins_sleep: dcan1_pins_sleep {
 325                 pinctrl-single,pins = <
 326                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 327                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 328                 >;
 329         };
 330
 331         atl_pins: pinmux_atl_pins {
 332                 pinctrl-single,pins = <
 333                         0x298 (PIN_OUTPUT | MUX_MODE5)  /* xref_clk1.atl_clk1 */
 334                         0x29c (PIN_OUTPUT | MUX_MODE5)  /* xref_clk2.atl_clk2 */
 335                 >;
 336         };
 337
 338         mcasp3_pins: pinmux_mcasp3_pins {
 339                 pinctrl-single,pins = <
 340                         0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
 341                         0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
 342                         0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
 343                         0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp3_axr1 */
 344                 >;
 345         };
 346
 347         mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
 348                 pinctrl-single,pins = <
 349                         0x324 (MUX_MODE15)
 350                         0x328 (MUX_MODE15)
 351                         0x32c (MUX_MODE15)
 352                         0x330 (MUX_MODE15)
 353                 >;
 354         };
 355 };
 356
 357 &i2c1 {
 358         status = "okay";
 359         pinctrl-names = "default";
 360         pinctrl-0 = <&i2c1_pins>;
 361         clock-frequency = <400000>;
 362
 363         tps659038: tps659038@58 {
 364                 compatible = "ti,tps659038";
 365                 reg = <0x58>;
 366
 367                 tps659038_pmic {
 368                         compatible = "ti,tps659038-pmic";
 369
 370                         regulators {
 371                                 smps123_reg: smps123 {
 372                                         /* VDD_MPU */
 373                                         regulator-name = "smps123";
 374                                         regulator-min-microvolt = < 850000>;
 375                                         regulator-max-microvolt = <1250000>;
 376                                         regulator-always-on;
 377                                         regulator-boot-on;
 378                                 };
 379
 380                                 smps45_reg: smps45 {
 381                                         /* VDD_DSPEVE */
 382                                         regulator-name = "smps45";
 383                                         regulator-min-microvolt = < 850000>;
 384                                         regulator-max-microvolt = <1150000>;
 385                                         regulator-always-on;
 386                                         regulator-boot-on;
 387                                 };
 388
 389                                 smps6_reg: smps6 {
 390                                         /* VDD_GPU - over VDD_SMPS6 */
 391                                         regulator-name = "smps6";
 392                                         regulator-min-microvolt = <850000>;
 393                                         regulator-max-microvolt = <1250000>;
 394                                         regulator-always-on;
 395                                         regulator-boot-on;
 396                                 };
 397
 398                                 smps7_reg: smps7 {
 399                                         /* CORE_VDD */
 400                                         regulator-name = "smps7";
 401                                         regulator-min-microvolt = <850000>;
 402                                         regulator-max-microvolt = <1060000>;
 403                                         regulator-always-on;
 404                                         regulator-boot-on;
 405                                 };
 406
 407                                 smps8_reg: smps8 {
 408                                         /* VDD_IVAHD */
 409                                         regulator-name = "smps8";
 410                                         regulator-min-microvolt = < 850000>;
 411                                         regulator-max-microvolt = <1250000>;
 412                                         regulator-always-on;
 413                                         regulator-boot-on;
 414                                 };
 415
 416                                 smps9_reg: smps9 {
 417                                         /* VDDS1V8 */
 418                                         regulator-name = "smps9";
 419                                         regulator-min-microvolt = <1800000>;
 420                                         regulator-max-microvolt = <1800000>;
 421                                         regulator-always-on;
 422                                         regulator-boot-on;
 423                                 };
 424
 425                                 ldo1_reg: ldo1 {
 426                                         /* LDO1_OUT --> SDIO  */
 427                                         regulator-name = "ldo1";
 428                                         regulator-min-microvolt = <1800000>;
 429                                         regulator-max-microvolt = <3300000>;
 430                                         regulator-always-on;
 431                                         regulator-boot-on;
 432                                 };
 433
 434                                 ldo2_reg: ldo2 {
 435                                         /* VDD_RTCIO */
 436                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 437                                         regulator-name = "ldo2";
 438                                         regulator-min-microvolt = <3300000>;
 439                                         regulator-max-microvolt = <3300000>;
 440                                         regulator-always-on;
 441                                         regulator-boot-on;
 442                                 };
 443
 444                                 ldo3_reg: ldo3 {
 445                                         /* VDDA_1V8_PHY */
 446                                         regulator-name = "ldo3";
 447                                         regulator-min-microvolt = <1800000>;
 448                                         regulator-max-microvolt = <1800000>;
 449                                         regulator-always-on;
 450                                         regulator-boot-on;
 451                                 };
 452
 453                                 ldo9_reg: ldo9 {
 454                                         /* VDD_RTC */
 455                                         regulator-name = "ldo9";
 456                                         regulator-min-microvolt = <1050000>;
 457                                         regulator-max-microvolt = <1050000>;
 458                                         regulator-always-on;
 459                                         regulator-boot-on;
 460                                 };
 461
 462                                 ldoln_reg: ldoln {
 463                                         /* VDDA_1V8_PLL */
 464                                         regulator-name = "ldoln";
 465                                         regulator-min-microvolt = <1800000>;
 466                                         regulator-max-microvolt = <1800000>;
 467                                         regulator-always-on;
 468                                         regulator-boot-on;
 469                                 };
 470
 471                                 ldousb_reg: ldousb {
 472                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 473                                         regulator-name = "ldousb";
 474                                         regulator-min-microvolt = <3300000>;
 475                                         regulator-max-microvolt = <3300000>;
 476                                         regulator-boot-on;
 477                                 };
 478                         };
 479                 };
 480         };
 481
 482         pcf_lcd: gpio@20 {
 483                 compatible = "nxp,pcf8575";
 484                 reg = <0x20>;
 485                 gpio-controller;
 486                 #gpio-cells = <2>;
 487                 interrupt-parent = <&gpio6>;
 488                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 489                 interrupt-controller;
 490                 #interrupt-cells = <2>;
 491         };
 492
 493         pcf_gpio_21: gpio@21 {
 494                 compatible = "ti,pcf8575";
 495                 reg = <0x21>;
 496                 lines-initial-states = <0x1408>;
 497                 gpio-controller;
 498                 #gpio-cells = <2>;
 499                 interrupt-parent = <&gpio6>;
 500                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 501                 interrupt-controller;
 502                 #interrupt-cells = <2>;
 503         };
 504
 505         tlv320aic3106: tlv320aic3106@19 {
 506                 #sound-dai-cells = <0>;
 507                 compatible = "ti,tlv320aic3106";
 508                 reg = <0x19>;
 509                 adc-settle-ms = <40>;
 510                 ai3x-micbias-vg = <1>;          /* 2.0V */
 511                 status = "okay";
 512
 513                 /* Regulators */
 514                 AVDD-supply = <&evm_3v3_sw>;
 515                 IOVDD-supply = <&evm_3v3_sw>;
 516                 DRVDD-supply = <&evm_3v3_sw>;
 517                 DVDD-supply = <&aic_dvdd>;
 518         };
 519 };
 520
 521 &i2c2 {
 522         status = "okay";
 523         pinctrl-names = "default";
 524         pinctrl-0 = <&i2c2_pins>;
 525         clock-frequency = <400000>;
 526
 527         pcf_hdmi: gpio@26 {
 528                 compatible = "nxp,pcf8575";
 529                 reg = <0x26>;
 530                 gpio-controller;
 531                 #gpio-cells = <2>;
 532                 p1 {
 533                         /* vin6_sel_s0: high: VIN6, low: audio */
 534                         gpio-hog;
 535                         gpios = <1 GPIO_ACTIVE_HIGH>;
 536                         output-low;
 537                         line-name = "vin6_sel_s0";
 538                 };
 539         };
 540 };
 541
 542 &i2c3 {
 543         status = "okay";
 544         pinctrl-names = "default";
 545         pinctrl-0 = <&i2c3_pins>;
 546         clock-frequency = <400000>;
 547 };
 548
 549 &mcspi1 {
 550         status = "okay";
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&mcspi1_pins>;
 553 };
 554
 555 &mcspi2 {
 556         status = "okay";
 557         pinctrl-names = "default";
 558         pinctrl-0 = <&mcspi2_pins>;
 559 };
 560
 561 &uart1 {
 562         status = "okay";
 563         pinctrl-names = "default";
 564         pinctrl-0 = <&uart1_pins>;
 565         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 566                               <&dra7_pmx_core 0x3e0>;
 567 };
 568
 569 &uart2 {
 570         status = "okay";
 571         pinctrl-names = "default";
 572         pinctrl-0 = <&uart2_pins>;
 573 };
 574
 575 &uart3 {
 576         status = "okay";
 577         pinctrl-names = "default";
 578         pinctrl-0 = <&uart3_pins>;
 579 };
 580
 581 &mmc1 {
 582         status = "okay";
 583         vmmc-supply = <&evm_3v3_sd>;
 584         vmmc_aux-supply = <&ldo1_reg>;
 585         bus-width = <4>;
 586         /*
 587          * SDCD signal is not being used here - using the fact that GPIO mode
 588          * is always hardwired.
 589          */
 590         cd-gpios = <&gpio6 27 0>;
 591 };
 592
 593 &mmc2 {
 594         status = "okay";
 595         vmmc-supply = <&evm_3v3_sw>;
 596         bus-width = <8>;
 597 };
 598
 599 &cpu0 {
 600         cpu0-supply = <&smps123_reg>;
 601 };
 602
 603 &qspi {
 604         status = "okay";
 605         pinctrl-names = "default";
 606         pinctrl-0 = <&qspi1_pins>;
 607
 608         spi-max-frequency = <48000000>;
 609         m25p80@0 {
 610                 compatible = "s25fl256s1";
 611                 spi-max-frequency = <48000000>;
 612                 reg = <0>;
 613                 spi-tx-bus-width = <1>;
 614                 spi-rx-bus-width = <4>;
 615                 spi-cpol;
 616                 spi-cpha;
 617                 #address-cells = <1>;
 618                 #size-cells = <1>;
 619
 620                 /* MTD partition table.
 621                  * The ROM checks the first four physical blocks
 622                  * for a valid file to boot and the flash here is
 623                  * 64KiB block size.
 624                  */
 625                 partition@0 {
 626                         label = "QSPI.SPL";
 627                         reg = <0x00000000 0x000010000>;
 628                 };
 629                 partition@1 {
 630                         label = "QSPI.SPL.backup1";
 631                         reg = <0x00010000 0x00010000>;
 632                 };
 633                 partition@2 {
 634                         label = "QSPI.SPL.backup2";
 635                         reg = <0x00020000 0x00010000>;
 636                 };
 637                 partition@3 {
 638                         label = "QSPI.SPL.backup3";
 639                         reg = <0x00030000 0x00010000>;
 640                 };
 641                 partition@4 {
 642                         label = "QSPI.u-boot";
 643                         reg = <0x00040000 0x00100000>;
 644                 };
 645                 partition@5 {
 646                         label = "QSPI.u-boot-spl-os";
 647                         reg = <0x00140000 0x00080000>;
 648                 };
 649                 partition@6 {
 650                         label = "QSPI.u-boot-env";
 651                         reg = <0x001c0000 0x00010000>;
 652                 };
 653                 partition@7 {
 654                         label = "QSPI.u-boot-env.backup1";
 655                         reg = <0x001d0000 0x0010000>;
 656                 };
 657                 partition@8 {
 658                         label = "QSPI.kernel";
 659                         reg = <0x001e0000 0x0800000>;
 660                 };
 661                 partition@9 {
 662                         label = "QSPI.file-system";
 663                         reg = <0x009e0000 0x01620000>;
 664                 };
 665         };
 666 };
 667
 668 &omap_dwc3_1 {
 669         extcon = <&extcon_usb1>;
 670 };
 671
 672 &omap_dwc3_2 {
 673         extcon = <&extcon_usb2>;
 674 };
 675
 676 &usb1 {
 677         dr_mode = "peripheral";
 678         pinctrl-names = "default";
 679         pinctrl-0 = <&usb1_pins>;
 680 };
 681
 682 &usb2 {
 683         dr_mode = "host";
 684         pinctrl-names = "default";
 685         pinctrl-0 = <&usb2_pins>;
 686 };
 687
 688 &elm {
 689         status = "okay";
 690 };
 691
 692 &gpmc {
 693         status = "okay";
 694         pinctrl-names = "default";
 695         pinctrl-0 = <&nand_flash_x16>;
 696         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 697         nand@0,0 {
 698                 reg = <0 0 4>;          /* device IO registers */
 699                 ti,nand-ecc-opt = "bch8";
 700                 ti,elm-id = <&elm>;
 701                 nand-bus-width = <16>;
 702                 gpmc,device-width = <2>;
 703                 gpmc,sync-clk-ps = <0>;
 704                 gpmc,cs-on-ns = <0>;
 705                 gpmc,cs-rd-off-ns = <80>;
 706                 gpmc,cs-wr-off-ns = <80>;
 707                 gpmc,adv-on-ns = <0>;
 708                 gpmc,adv-rd-off-ns = <60>;
 709                 gpmc,adv-wr-off-ns = <60>;
 710                 gpmc,we-on-ns = <10>;
 711                 gpmc,we-off-ns = <50>;
 712                 gpmc,oe-on-ns = <4>;
 713                 gpmc,oe-off-ns = <40>;
 714                 gpmc,access-ns = <40>;
 715                 gpmc,wr-access-ns = <80>;
 716                 gpmc,rd-cycle-ns = <80>;
 717                 gpmc,wr-cycle-ns = <80>;
 718                 gpmc,bus-turnaround-ns = <0>;
 719                 gpmc,cycle2cycle-delay-ns = <0>;
 720                 gpmc,clk-activation-ns = <0>;
 721                 gpmc,wait-monitoring-ns = <0>;
 722                 gpmc,wr-data-mux-bus-ns = <0>;
 723                 /* MTD partition table */
 724                 /* All SPL-* partitions are sized to minimal length
 725                  * which can be independently programmable. For
 726                  * NAND flash this is equal to size of erase-block */
 727                 #address-cells = <1>;
 728                 #size-cells = <1>;
 729                 partition@0 {
 730                         label = "NAND.SPL";
 731                         reg = <0x00000000 0x000020000>;
 732                 };
 733                 partition@1 {
 734                         label = "NAND.SPL.backup1";
 735                         reg = <0x00020000 0x00020000>;
 736                 };
 737                 partition@2 {
 738                         label = "NAND.SPL.backup2";
 739                         reg = <0x00040000 0x00020000>;
 740                 };
 741                 partition@3 {
 742                         label = "NAND.SPL.backup3";
 743                         reg = <0x00060000 0x00020000>;
 744                 };
 745                 partition@4 {
 746                         label = "NAND.u-boot-spl-os";
 747                         reg = <0x00080000 0x00040000>;
 748                 };
 749                 partition@5 {
 750                         label = "NAND.u-boot";
 751                         reg = <0x000c0000 0x00100000>;
 752                 };
 753                 partition@6 {
 754                         label = "NAND.u-boot-env";
 755                         reg = <0x001c0000 0x00020000>;
 756                 };
 757                 partition@7 {
 758                         label = "NAND.u-boot-env.backup1";
 759                         reg = <0x001e0000 0x00020000>;
 760                 };
 761                 partition@8 {
 762                         label = "NAND.kernel";
 763                         reg = <0x00200000 0x00800000>;
 764                 };
 765                 partition@9 {
 766                         label = "NAND.file-system";
 767                         reg = <0x00a00000 0x0f600000>;
 768                 };
 769         };
 770 };
 771
 772 &usb2_phy1 {
 773         phy-supply = <&ldousb_reg>;
 774 };
 775
 776 &usb2_phy2 {
 777         phy-supply = <&ldousb_reg>;
 778 };
 779
 780 &gpio7 {
 781         ti,no-reset-on-init;
 782         ti,no-idle-on-init;
 783 };
 784
 785 &mac {
 786         status = "okay";
 787         pinctrl-names = "default", "sleep";
 788         pinctrl-0 = <&cpsw_default>;
 789         pinctrl-1 = <&cpsw_sleep>;
 790         dual_emac;
 791 };
 792
 793 &cpsw_emac0 {
 794         phy_id = <&davinci_mdio>, <2>;
 795         phy-mode = "rgmii";
 796         dual_emac_res_vlan = <1>;
 797 };
 798
 799 &cpsw_emac1 {
 800         phy_id = <&davinci_mdio>, <3>;
 801         phy-mode = "rgmii";
 802         dual_emac_res_vlan = <2>;
 803 };
 804
 805 &davinci_mdio {
 806         pinctrl-names = "default", "sleep";
 807         pinctrl-0 = <&davinci_mdio_default>;
 808         pinctrl-1 = <&davinci_mdio_sleep>;
 809 };
 810
 811 &dcan1 {
 812         status = "ok";
 813         pinctrl-names = "default", "sleep", "active";
 814         pinctrl-0 = <&dcan1_pins_sleep>;
 815         pinctrl-1 = <&dcan1_pins_sleep>;
 816         pinctrl-2 = <&dcan1_pins_default>;
 817 };
 818
 819 &atl {
 820         pinctrl-names = "default";
 821         pinctrl-0 = <&atl_pins>;
 822
 823         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 824                           <&atl_gfclk_mux>,
 825                           <&dpll_abe_ck>,
 826                           <&dpll_abe_m2x2_ck>,
 827                           <&atl_clkin2_ck>;
 828         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 829         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 830
 831         status = "okay";
 832
 833         atl2 {
 834                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 835                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 836         };
 837 };
 838
 839 &mcasp3 {
 840         #sound-dai-cells = <0>;
 841         pinctrl-names = "default", "sleep";
 842         pinctrl-0 = <&mcasp3_pins>;
 843         pinctrl-1 = <&mcasp3_sleep_pins>;
 844
 845         assigned-clocks = <&mcasp3_ahclkx_mux>;
 846         assigned-clock-parents = <&atl_clkin2_ck>;
 847
 848         status = "okay";
 849
 850         op-mode = <0>;          /* MCASP_IIS_MODE */
 851         tdm-slots = <2>;
 852         /* 4 serializer */
 853         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 854                 1 2 0 0
 855         >;
 856 };