| 2020-10-09 |
Chee Hong Ang | arm: socfpga: Use DM watchdog timer
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | arm: socfpga: soc64: Show reset state in SPL
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | arm: socfpga: soc64: Add SDM triggered warm reset bit...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | sysreset: socfpga: agilex: Enable sysreset support
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | arm: socfpga: soc64: Initialize timer in SPL only
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | arm: socfpga: soc64: Remove PHY interface setup from...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | clk: agilex: Additional membus writes for HPS PLL
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-10-09 |
Chee Hong Ang | clk: agilex: Handle clock configuration differently...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-09-03 |
Chee Hong Ang | arm: socfpga: soc64: Check FPGA Config status register...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2020-04-05 |
Chee Hong Ang | clk: socfpga: Read the clock parent's register base...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2019-05-06 |
Ang, Chee Hong | ARM: socfpga: stratix10: Probe FPGA status before bridge...
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2019-05-06 |
Ang, Chee Hong | ARM: socfpga: stratix10: Disable FPGA2SOC reset
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2019-04-22 |
Ang, Chee Hong | ARMv8: Disable fwcall when PSCI is enabled
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2019-04-22 |
Chee Hong Ang | ARMv8: Allow SiP service extensions on top of PSCI...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2019-02-18 |
Ang, Chee Hong | ARM: socfpga: stratix10: Return valid error code from...
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-12-20 |
Ang, Chee Hong | arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-12-20 |
Ang, Chee Hong | arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA...
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-12-20 |
Ang, Chee Hong | arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration...
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-12-20 |
Ang, Chee Hong | arm: socfpga: stratix10: Add macros for mailbox's arguments
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-12-20 |
Ang, Chee Hong | arm: socfpga: stratix10: Add generic FPGA reconfig...
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-11-16 |
Chee Hong Ang | ARMv8: SError exception handling in PSCI exception...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-11-16 |
Chee Hong Ang | ARMv8: Add EL3 exception handling for ARMv8's Kconfig
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
| 2018-11-16 |
Chee Hong Ang | ARMv8: Enable all asynchronous abort exceptions taken...
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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commit | commitdiff | tree |
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