[libata] sata_sx4: named constant cleanup

* convert tabs to spaces
* convert some hex numbers to (1 << n) preferred format
* document i2c and timer control register bits

Signed-off-by: Jeff Garzik <jeff@garzik.org>

diff --git a/drivers/ata/sata_sx4.c b/drivers/ata/sata_sx4.c
index 2d14f3d..ff0a78d 100644 (file)
--- a/drivers/ata/sata_sx4.c
+++ b/drivers/ata/sata_sx4.c
@@ -87,48 +87,59 @@ enum {
 
        board_20621             = 0,    /* FastTrak S150 SX4 */
 
-       PDC_RESET               = (1 << 11), /* HDMA reset */
+       PDC_MASK_INT            = (1 << 10), /* HDMA/ATA mask int */
+       PDC_RESET               = (1 << 11), /* HDMA/ATA reset */
 
        PDC_MAX_HDMA            = 32,
        PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
 
-       PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
-       PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
-       PDC_MAX_DIMM_MODULE           = 0x02,
-       PDC_I2C_CONTROL_OFFSET        = 0x48,
-       PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
-       PDC_DIMM0_CONTROL_OFFSET      = 0x80,
-       PDC_DIMM1_CONTROL_OFFSET      = 0x84,
-       PDC_SDRAM_CONTROL_OFFSET      = 0x88,
-       PDC_I2C_WRITE                 = 0x00000000,
-       PDC_I2C_READ                  = 0x00000040,
-       PDC_I2C_START                 = 0x00000080,
-       PDC_I2C_MASK_INT              = 0x00000020,
-       PDC_I2C_COMPLETE              = 0x00010000,
-       PDC_I2C_NO_ACK                = 0x00100000,
-       PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
-       PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
-       PDC_DIMM_SPD_ROW_NUM          = 3,
-       PDC_DIMM_SPD_COLUMN_NUM       = 4,
-       PDC_DIMM_SPD_MODULE_ROW       = 5,
-       PDC_DIMM_SPD_TYPE             = 11,
-       PDC_DIMM_SPD_FRESH_RATE       = 12,
-       PDC_DIMM_SPD_BANK_NUM         = 17,
-       PDC_DIMM_SPD_CAS_LATENCY      = 18,
-       PDC_DIMM_SPD_ATTRIBUTE        = 21,
-       PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
-       PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
-       PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
-       PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
-       PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
-       PDC_CTL_STATUS                = 0x08,
-       PDC_DIMM_WINDOW_CTLR          = 0x0C,
-       PDC_TIME_CONTROL              = 0x3C,
-       PDC_TIME_PERIOD               = 0x40,
-       PDC_TIME_COUNTER              = 0x44,
-       PDC_GENERAL_CTLR              = 0x484,
-       PCI_PLL_INIT                  = 0x8A531824,
-       PCI_X_TCOUNT                  = 0xEE1E5CFF
+       PDC_DIMM0_SPD_DEV_ADDRESS       = 0x50,
+       PDC_DIMM1_SPD_DEV_ADDRESS       = 0x51,
+       PDC_I2C_CONTROL                 = 0x48,
+       PDC_I2C_ADDR_DATA               = 0x4C,
+       PDC_DIMM0_CONTROL               = 0x80,
+       PDC_DIMM1_CONTROL               = 0x84,
+       PDC_SDRAM_CONTROL               = 0x88,
+       PDC_I2C_WRITE                   = 0,            /* master -> slave */
+       PDC_I2C_READ                    = (1 << 6),     /* master <- slave */
+       PDC_I2C_START                   = (1 << 7),     /* start I2C proto */
+       PDC_I2C_MASK_INT                = (1 << 5),     /* mask I2C interrupt */
+       PDC_I2C_COMPLETE                = (1 << 16),    /* I2C normal compl. */
+       PDC_I2C_NO_ACK                  = (1 << 20),    /* slave no-ack addr */
+       PDC_DIMM_SPD_SUBADDRESS_START   = 0x00,
+       PDC_DIMM_SPD_SUBADDRESS_END     = 0x7F,
+       PDC_DIMM_SPD_ROW_NUM            = 3,
+       PDC_DIMM_SPD_COLUMN_NUM         = 4,
+       PDC_DIMM_SPD_MODULE_ROW         = 5,
+       PDC_DIMM_SPD_TYPE               = 11,
+       PDC_DIMM_SPD_FRESH_RATE         = 12,
+       PDC_DIMM_SPD_BANK_NUM           = 17,
+       PDC_DIMM_SPD_CAS_LATENCY        = 18,
+       PDC_DIMM_SPD_ATTRIBUTE          = 21,
+       PDC_DIMM_SPD_ROW_PRE_CHARGE     = 27,
+       PDC_DIMM_SPD_ROW_ACTIVE_DELAY   = 28,
+       PDC_DIMM_SPD_RAS_CAS_DELAY      = 29,
+       PDC_DIMM_SPD_ACTIVE_PRECHARGE   = 30,
+       PDC_DIMM_SPD_SYSTEM_FREQ        = 126,
+       PDC_CTL_STATUS                  = 0x08,
+       PDC_DIMM_WINDOW_CTLR            = 0x0C,
+       PDC_TIME_CONTROL                = 0x3C,
+       PDC_TIME_PERIOD                 = 0x40,
+       PDC_TIME_COUNTER                = 0x44,
+       PDC_GENERAL_CTLR                = 0x484,
+       PCI_PLL_INIT                    = 0x8A531824,
+       PCI_X_TCOUNT                    = 0xEE1E5CFF,
+
+       /* PDC_TIME_CONTROL bits */
+       PDC_TIMER_BUZZER                = (1 << 10),
+       PDC_TIMER_MODE_PERIODIC         = 0,            /* bits 9:8 == 00 */
+       PDC_TIMER_MODE_ONCE             = (1 << 8),     /* bits 9:8 == 01 */
+       PDC_TIMER_ENABLE                = (1 << 7),
+       PDC_TIMER_MASK_INT              = (1 << 5),
+       PDC_TIMER_SEQ_MASK              = 0x1f,         /* SEQ ID for timer */
+       PDC_TIMER_DEFAULT               = PDC_TIMER_MODE_ONCE |
+                                         PDC_TIMER_ENABLE |
+                                         PDC_TIMER_MASK_INT,
 };
 
 
@@ -999,17 +1010,17 @@ static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
        i2creg |= subaddr << 16;
 
        /* Set the device and subaddress */
-       writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
-       readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
+       writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
+       readl(mmio + PDC_I2C_ADDR_DATA);
 
        /* Write Control to perform read operation, mask int */
        writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
-              mmio + PDC_I2C_CONTROL_OFFSET);
+              mmio + PDC_I2C_CONTROL);
 
        for (count = 0; count <= 1000; count ++) {
-               status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
+               status = readl(mmio + PDC_I2C_CONTROL);
                if (status & PDC_I2C_COMPLETE) {
-                       status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
+                       status = readl(mmio + PDC_I2C_ADDR_DATA);
                        break;
                } else if (count == 1000)
                        return 0;
@@ -1099,8 +1110,8 @@ static int pdc20621_prog_dimm0(struct ata_host *host)
        data |= (((size / 16) - 1) << 16);
        data |= (0 << 23);
        data |= 8;
-       writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
-       readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
+       writel(data, mmio + PDC_DIMM0_CONTROL);
+       readl(mmio + PDC_DIMM0_CONTROL);
        return size;
 }
 
@@ -1122,27 +1133,27 @@ static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
        */
 
        data = 0x022259F1;
-       writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
-       readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
+       writel(data, mmio + PDC_SDRAM_CONTROL);
+       readl(mmio + PDC_SDRAM_CONTROL);
 
        /* Turn on for ECC */
        pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
                          PDC_DIMM_SPD_TYPE, &spd0);
        if (spd0 == 0x02) {
                data |= (0x01 << 16);
-               writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
-               readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
+               writel(data, mmio + PDC_SDRAM_CONTROL);
+               readl(mmio + PDC_SDRAM_CONTROL);
                printk(KERN_ERR "Local DIMM ECC Enabled\n");
        }
 
        /* DIMM Initialization Select/Enable (bit 18/19) */
        data &= (~(1<<18));
        data |= (1<<19);
-       writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
+       writel(data, mmio + PDC_SDRAM_CONTROL);
 
        error = 1;
        for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
-               data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
+               data = readl(mmio + PDC_SDRAM_CONTROL);
                if (!(data & (1<<19))) {
                        error = 0;
                        break;
@@ -1176,7 +1187,7 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
        VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
 
        /* Enable timer */
-       writel(0x00001a0, mmio + PDC_TIME_CONTROL);
+       writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
        readl(mmio + PDC_TIME_CONTROL);
 
        /* Wait 3 seconds */