return TIMEOUT;
                }
        }
-       writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
-       writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
-               &mmc_base->capa);
+       reg_val = DTW_1_BITMODE | SDBP_PWROFF;
+       if (mmc->block_dev.dev == 0)
+               reg_val |= SDVS_3V0;
+       else
+               reg_val |= SDVS_1V8;
+       writel(reg_val, &mmc_base->hctl);
+
+       reg_val = readl(&mmc_base->capa) | VS18_1V8SUP;
+       if (mmc->block_dev.dev == 0)
+               reg_val |= VS30_3V0SUP;
+       writel(reg_val, &mmc_base->capa);
 
        reg_val = readl(&mmc_base->con) & RESERVED_MASK;