drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <twl6030.h>
  32 #include <twl6035.h>
  33 #include <asm/io.h>
  34 #include <asm/arch/mmc_host_def.h>
  35 #include <asm/arch/sys_proto.h>
  36
  37 /* common definitions for all OMAPs */
  38 #define SYSCTL_SRC      (1 << 25)
  39 #define SYSCTL_SRD      (1 << 26)
  40
  41 /* If we fail after 1 second wait, something is really bad */
  42 #define MAX_RETRY_MS    1000
  43
  44 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  45 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  46                         unsigned int siz);
  47 static struct mmc hsmmc_dev[2];
  48
  49 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  50 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  51 {
  52         u32 value = 0;
  53         struct omap_sys_ctrl_regs *const ctrl =
  54                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  55
  56
  57         value = readl(&ctrl->control_pbiaslite);
  58         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
  59         writel(value, &ctrl->control_pbiaslite);
  60         /* set VMMC to 3V */
  61         twl6030_power_mmc_init();
  62         value = readl(&ctrl->control_pbiaslite);
  63         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
  64         writel(value, &ctrl->control_pbiaslite);
  65 }
  66 #endif
  67
  68 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
  69 static void omap5_pbias_config(struct mmc *mmc)
  70 {
  71         u32 value = 0;
  72         struct omap_sys_ctrl_regs *const ctrl =
  73                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  74
  75         value = readl(&ctrl->control_pbias);
  76         value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
  77         value |= SDCARD_BIAS_HIZ_MODE;
  78         writel(value, &ctrl->control_pbias);
  79
  80         twl6035_mmc1_poweron_ldo();
  81
  82         value = readl(&ctrl->control_pbias);
  83         value &= ~SDCARD_BIAS_HIZ_MODE;
  84         value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
  85         writel(value, &ctrl->control_pbias);
  86
  87         value = readl(&ctrl->control_pbias);
  88         if (value & (1 << 23)) {
  89                 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
  90                 value |= SDCARD_BIAS_HIZ_MODE;
  91                 writel(value, &ctrl->control_pbias);
  92         }
  93 }
  94 #endif
  95
  96 unsigned char mmc_board_init(struct mmc *mmc)
  97 {
  98 #if defined(CONFIG_OMAP34XX)
  99         t2_t *t2_base = (t2_t *)T2_BASE;
 100         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 101         u32 pbias_lite;
 102
 103         pbias_lite = readl(&t2_base->pbias_lite);
 104         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 105         writel(pbias_lite, &t2_base->pbias_lite);
 106 #endif
 107 #if defined(CONFIG_TWL4030_POWER)
 108         twl4030_power_mmc_init();
 109         mdelay(100);    /* ramp-up delay from Linux code */
 110 #endif
 111 #if defined(CONFIG_OMAP34XX)
 112         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 113                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 114                 &t2_base->pbias_lite);
 115
 116         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 117                 &t2_base->devconf0);
 118 /*
 119         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 120                 &t2_base->devconf1);
 121 */
 122
 123         /* Change from default of 52MHz to 26MHz if necessary */
 124         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
 125                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 126                         &t2_base->ctl_prog_io1);
 127
 128         writel(readl(&prcm_base->fclken1_core) |
 129                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 130                 &prcm_base->fclken1_core);
 131
 132         writel(readl(&prcm_base->iclken1_core) |
 133                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 134                 &prcm_base->iclken1_core);
 135 #endif
 136
 137 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 138         /* PBIAS config needed for MMC1 only */
 139         if (mmc->block_dev.dev == 0)
 140                 omap4_vmmc_pbias_config(mmc);
 141 #endif
 142 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
 143         if (mmc->block_dev.dev == 0)
 144                 omap5_pbias_config(mmc);
 145 #endif
 146
 147         return 0;
 148 }
 149
 150 void mmc_init_stream(struct hsmmc *mmc_base)
 151 {
 152         ulong start;
 153
 154         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 155
 156         writel(MMC_CMD0, &mmc_base->cmd);
 157         start = get_timer(0);
 158         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 159                 if (get_timer(0) - start > MAX_RETRY_MS) {
 160                         printf("%s: timedout waiting for cc!\n", __func__);
 161                         return;
 162                 }
 163         }
 164         writel(CC_MASK, &mmc_base->stat)
 165                 ;
 166         writel(MMC_CMD0, &mmc_base->cmd)
 167                 ;
 168         start = get_timer(0);
 169         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 170                 if (get_timer(0) - start > MAX_RETRY_MS) {
 171                         printf("%s: timedout waiting for cc2!\n", __func__);
 172                         return;
 173                 }
 174         }
 175         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 176 }
 177
 178
 179 static int mmc_init_setup(struct mmc *mmc)
 180 {
 181         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 182         unsigned int reg_val;
 183         unsigned int dsor;
 184         ulong start;
 185
 186         mmc_board_init(mmc);
 187
 188         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 189                 &mmc_base->sysconfig);
 190         start = get_timer(0);
 191         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 192                 if (get_timer(0) - start > MAX_RETRY_MS) {
 193                         printf("%s: timedout waiting for cc2!\n", __func__);
 194                         return TIMEOUT;
 195                 }
 196         }
 197         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 198         start = get_timer(0);
 199         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 200                 if (get_timer(0) - start > MAX_RETRY_MS) {
 201                         printf("%s: timedout waiting for softresetall!\n",
 202                                 __func__);
 203                         return TIMEOUT;
 204                 }
 205         }
 206         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 207         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 208                 &mmc_base->capa);
 209
 210         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 211
 212         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 213                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 214                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 215
 216         dsor = 240;
 217         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 218                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 219         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 220                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 221         start = get_timer(0);
 222         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 223                 if (get_timer(0) - start > MAX_RETRY_MS) {
 224                         printf("%s: timedout waiting for ics!\n", __func__);
 225                         return TIMEOUT;
 226                 }
 227         }
 228         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 229
 230         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 231
 232         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 233                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 234                 &mmc_base->ie);
 235
 236         mmc_init_stream(mmc_base);
 237
 238         return 0;
 239 }
 240
 241 /*
 242  * MMC controller internal finite state machine reset
 243  *
 244  * Used to reset command or data internal state machines, using respectively
 245  * SRC or SRD bit of SYSCTL register
 246  */
 247 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 248 {
 249         ulong start;
 250
 251         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 252
 253         start = get_timer(0);
 254         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 255                 if (get_timer(0) - start > MAX_RETRY_MS) {
 256                         printf("%s: timedout waiting for sysctl %x to clear\n",
 257                                 __func__, bit);
 258                         return;
 259                 }
 260         }
 261 }
 262
 263 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 264                         struct mmc_data *data)
 265 {
 266         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 267         unsigned int flags, mmc_stat;
 268         ulong start;
 269
 270         start = get_timer(0);
 271         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 272                 if (get_timer(0) - start > MAX_RETRY_MS) {
 273                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 274                                         __func__);
 275                         return TIMEOUT;
 276                 }
 277         }
 278         writel(0xFFFFFFFF, &mmc_base->stat);
 279         start = get_timer(0);
 280         while (readl(&mmc_base->stat)) {
 281                 if (get_timer(0) - start > MAX_RETRY_MS) {
 282                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 283                                 __func__, readl(&mmc_base->stat));
 284                         return TIMEOUT;
 285                 }
 286         }
 287         /*
 288          * CMDREG
 289          * CMDIDX[13:8] : Command index
 290          * DATAPRNT[5]  : Data Present Select
 291          * ENCMDIDX[4]  : Command Index Check Enable
 292          * ENCMDCRC[3]  : Command CRC Check Enable
 293          * RSPTYP[1:0]
 294          *      00 = No Response
 295          *      01 = Length 136
 296          *      10 = Length 48
 297          *      11 = Length 48 Check busy after response
 298          */
 299         /* Delay added before checking the status of frq change
 300          * retry not supported by mmc.c(core file)
 301          */
 302         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 303                 udelay(50000); /* wait 50 ms */
 304
 305         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 306                 flags = 0;
 307         else if (cmd->resp_type & MMC_RSP_136)
 308                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 309         else if (cmd->resp_type & MMC_RSP_BUSY)
 310                 flags = RSP_TYPE_LGHT48B;
 311         else
 312                 flags = RSP_TYPE_LGHT48;
 313
 314         /* enable default flags */
 315         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 316                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 317
 318         if (cmd->resp_type & MMC_RSP_CRC)
 319                 flags |= CCCE_CHECK;
 320         if (cmd->resp_type & MMC_RSP_OPCODE)
 321                 flags |= CICE_CHECK;
 322
 323         if (data) {
 324                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 325                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 326                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 327                         data->blocksize = 512;
 328                         writel(data->blocksize | (data->blocks << 16),
 329                                                         &mmc_base->blk);
 330                 } else
 331                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 332
 333                 if (data->flags & MMC_DATA_READ)
 334                         flags |= (DP_DATA | DDIR_READ);
 335                 else
 336                         flags |= (DP_DATA | DDIR_WRITE);
 337         }
 338
 339         writel(cmd->cmdarg, &mmc_base->arg);
 340         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 341
 342         start = get_timer(0);
 343         do {
 344                 mmc_stat = readl(&mmc_base->stat);
 345                 if (get_timer(0) - start > MAX_RETRY_MS) {
 346                         printf("%s : timeout: No status update\n", __func__);
 347                         return TIMEOUT;
 348                 }
 349         } while (!mmc_stat);
 350
 351         if ((mmc_stat & IE_CTO) != 0) {
 352                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 353                 return TIMEOUT;
 354         } else if ((mmc_stat & ERRI_MASK) != 0)
 355                 return -1;
 356
 357         if (mmc_stat & CC_MASK) {
 358                 writel(CC_MASK, &mmc_base->stat);
 359                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 360                         if (cmd->resp_type & MMC_RSP_136) {
 361                                 /* response type 2 */
 362                                 cmd->response[3] = readl(&mmc_base->rsp10);
 363                                 cmd->response[2] = readl(&mmc_base->rsp32);
 364                                 cmd->response[1] = readl(&mmc_base->rsp54);
 365                                 cmd->response[0] = readl(&mmc_base->rsp76);
 366                         } else
 367                                 /* response types 1, 1b, 3, 4, 5, 6 */
 368                                 cmd->response[0] = readl(&mmc_base->rsp10);
 369                 }
 370         }
 371
 372         if (data && (data->flags & MMC_DATA_READ)) {
 373                 mmc_read_data(mmc_base, data->dest,
 374                                 data->blocksize * data->blocks);
 375         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 376                 mmc_write_data(mmc_base, data->src,
 377                                 data->blocksize * data->blocks);
 378         }
 379         return 0;
 380 }
 381
 382 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 383 {
 384         unsigned int *output_buf = (unsigned int *)buf;
 385         unsigned int mmc_stat;
 386         unsigned int count;
 387
 388         /*
 389          * Start Polled Read
 390          */
 391         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 392         count /= 4;
 393
 394         while (size) {
 395                 ulong start = get_timer(0);
 396                 do {
 397                         mmc_stat = readl(&mmc_base->stat);
 398                         if (get_timer(0) - start > MAX_RETRY_MS) {
 399                                 printf("%s: timedout waiting for status!\n",
 400                                                 __func__);
 401                                 return TIMEOUT;
 402                         }
 403                 } while (mmc_stat == 0);
 404
 405                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 406                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 407
 408                 if ((mmc_stat & ERRI_MASK) != 0)
 409                         return 1;
 410
 411                 if (mmc_stat & BRR_MASK) {
 412                         unsigned int k;
 413
 414                         writel(readl(&mmc_base->stat) | BRR_MASK,
 415                                 &mmc_base->stat);
 416                         for (k = 0; k < count; k++) {
 417                                 *output_buf = readl(&mmc_base->data);
 418                                 output_buf++;
 419                         }
 420                         size -= (count*4);
 421                 }
 422
 423                 if (mmc_stat & BWR_MASK)
 424                         writel(readl(&mmc_base->stat) | BWR_MASK,
 425                                 &mmc_base->stat);
 426
 427                 if (mmc_stat & TC_MASK) {
 428                         writel(readl(&mmc_base->stat) | TC_MASK,
 429                                 &mmc_base->stat);
 430                         break;
 431                 }
 432         }
 433         return 0;
 434 }
 435
 436 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 437                                 unsigned int size)
 438 {
 439         unsigned int *input_buf = (unsigned int *)buf;
 440         unsigned int mmc_stat;
 441         unsigned int count;
 442
 443         /*
 444          * Start Polled Read
 445          */
 446         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 447         count /= 4;
 448
 449         while (size) {
 450                 ulong start = get_timer(0);
 451                 do {
 452                         mmc_stat = readl(&mmc_base->stat);
 453                         if (get_timer(0) - start > MAX_RETRY_MS) {
 454                                 printf("%s: timedout waiting for status!\n",
 455                                                 __func__);
 456                                 return TIMEOUT;
 457                         }
 458                 } while (mmc_stat == 0);
 459
 460                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 461                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 462
 463                 if ((mmc_stat & ERRI_MASK) != 0)
 464                         return 1;
 465
 466                 if (mmc_stat & BWR_MASK) {
 467                         unsigned int k;
 468
 469                         writel(readl(&mmc_base->stat) | BWR_MASK,
 470                                         &mmc_base->stat);
 471                         for (k = 0; k < count; k++) {
 472                                 writel(*input_buf, &mmc_base->data);
 473                                 input_buf++;
 474                         }
 475                         size -= (count*4);
 476                 }
 477
 478                 if (mmc_stat & BRR_MASK)
 479                         writel(readl(&mmc_base->stat) | BRR_MASK,
 480                                 &mmc_base->stat);
 481
 482                 if (mmc_stat & TC_MASK) {
 483                         writel(readl(&mmc_base->stat) | TC_MASK,
 484                                 &mmc_base->stat);
 485                         break;
 486                 }
 487         }
 488         return 0;
 489 }
 490
 491 static void mmc_set_ios(struct mmc *mmc)
 492 {
 493         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 494         unsigned int dsor = 0;
 495         ulong start;
 496
 497         /* configue bus width */
 498         switch (mmc->bus_width) {
 499         case 8:
 500                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 501                         &mmc_base->con);
 502                 break;
 503
 504         case 4:
 505                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 506                         &mmc_base->con);
 507                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 508                         &mmc_base->hctl);
 509                 break;
 510
 511         case 1:
 512         default:
 513                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 514                         &mmc_base->con);
 515                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 516                         &mmc_base->hctl);
 517                 break;
 518         }
 519
 520         /* configure clock with 96Mhz system clock.
 521          */
 522         if (mmc->clock != 0) {
 523                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 524                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 525                         dsor++;
 526         }
 527
 528         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 529                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 530
 531         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 532                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 533
 534         start = get_timer(0);
 535         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 536                 if (get_timer(0) - start > MAX_RETRY_MS) {
 537                         printf("%s: timedout waiting for ics!\n", __func__);
 538                         return;
 539                 }
 540         }
 541         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 542 }
 543
 544 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
 545 {
 546         struct mmc *mmc;
 547
 548         mmc = &hsmmc_dev[dev_index];
 549
 550         sprintf(mmc->name, "OMAP SD/MMC");
 551         mmc->send_cmd = mmc_send_cmd;
 552         mmc->set_ios = mmc_set_ios;
 553         mmc->init = mmc_init_setup;
 554         mmc->getcd = NULL;
 555
 556         switch (dev_index) {
 557         case 0:
 558                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 559                 break;
 560 #ifdef OMAP_HSMMC2_BASE
 561         case 1:
 562                 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
 563                 break;
 564 #endif
 565 #ifdef OMAP_HSMMC3_BASE
 566         case 2:
 567                 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
 568                 break;
 569 #endif
 570         default:
 571                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 572                 return 1;
 573         }
 574         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 575         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 576                                 MMC_MODE_HC) & ~host_caps_mask;
 577
 578         mmc->f_min = 400000;
 579
 580         if (f_max != 0)
 581                 mmc->f_max = f_max;
 582         else {
 583                 if (mmc->host_caps & MMC_MODE_HS) {
 584                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
 585                                 mmc->f_max = 52000000;
 586                         else
 587                                 mmc->f_max = 26000000;
 588                 } else
 589                         mmc->f_max = 20000000;
 590         }
 591
 592         mmc->b_max = 0;
 593
 594 #if defined(CONFIG_OMAP34XX)
 595         /*
 596          * Silicon revs 2.1 and older do not support multiblock transfers.
 597          */
 598         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 599                 mmc->b_max = 1;
 600 #endif
 601
 602         mmc_register(mmc);
 603
 604         return 0;
 605 }