Removed the following cruft from .dts files:
* 32-bit in cpu node -- doesn't exist in any spec and not used by kernel
* removed built-in (chrp legacy)
* Removed #interrupt-cells in places they don't need to be set
* Fixed ranges on lite5200*
* Removed clock-frequency from i8259 pic node, not sure where this came from
* Removed big-endian from i8259 pic nodes, this was just bogus
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
25 files changed:
timebase-frequency = <2faf080>;
clock-frequency = <23c34600>;
bus-frequency = <bebc200>;
timebase-frequency = <2faf080>;
clock-frequency = <23c34600>;
bus-frequency = <bebc200>;
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = ""; // from bootloader
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = ""; // from bootloader
- #interrupt-cells = <3>;
- ranges = <0 f0000000 f0010000>;
- reg = <f0000000 00010000>;
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
};
gpt@600 { // General Purpose Timer
};
gpt@600 { // General Purpose Timer
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
model = "fsl,mpc5200b";
compatible = "mpc5200";
revision = ""; // from bootloader
model = "fsl,mpc5200b";
compatible = "mpc5200";
revision = ""; // from bootloader
- #interrupt-cells = <3>;
- ranges = <0 f0000000 f0010000>;
- reg = <f0000000 00010000>;
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
device_type = "interrupt-controller";
compatible = "mpc5200b-pic\0mpc5200-pic";
reg = <500 80>;
device_type = "interrupt-controller";
compatible = "mpc5200b-pic\0mpc5200-pic";
reg = <500 80>;
};
gpt@600 { // General Purpose Timer
};
gpt@600 { // General Purpose Timer
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
big-endian;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
big-endian;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <f8200000 f8200004>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <f8200000 f8200004>;
device_type = "pci-pic";
};
device_type = "pci-pic";
};
soc8272@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8272@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <00000000 f0000000 00053000>;
reg = <f0000000 10000>;
device_type = "soc";
ranges = <00000000 f0000000 00053000>;
reg = <f0000000 10000>;
cpm@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
cpm@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <00000000 00000000 20000>;
device_type = "cpm";
model = "CPM2";
ranges = <00000000 00000000 20000>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
device_type = "cpm-pic";
compatible = "CPM2";
};
device_type = "cpm-pic";
compatible = "CPM2";
};
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
soc8313@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8313@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
};
device_type = "ipic";
};
};
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
};
device_type = "ipic";
};
};
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
};
device_type = "ipic";
};
};
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
};
device_type = "ipic";
};
};
timebase-frequency = <3EF1480>;
bus-frequency = <FBC5200>;
clock-frequency = <1F78A400>;
timebase-frequency = <3EF1480>;
bus-frequency = <FBC5200>;
clock-frequency = <1F78A400>;
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
device_type = "pci";
i8259@19000 {
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1>;
interrupt-parent = <&pci1>;
};
interrupts = <1>;
interrupt-parent = <&pci1>;
};
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
soc8544@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8544@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
reg = <1 20 2
1 a0 2
1 4d0 2>;
reg = <1 20 2
1 a0 2
1 4d0 2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <00001000 e0001000 000ff000
80000000 80000000 10000000
device_type = "soc";
ranges = <00001000 e0001000 000ff000
80000000 80000000 10000000
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
device_type = "pci";
i8259@19000 {
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1>;
interrupt-parent = <&pci1>;
};
interrupts = <1>;
interrupt-parent = <&pci1>;
};
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
device_type = "open-pic";
};
cpm@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "open-pic";
};
cpm@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <0 0 c0000>;
device_type = "cpm";
model = "CPM2";
ranges = <0 0 c0000>;
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
device_type = "cpm-pic";
};
device_type = "cpm-pic";
};
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30
interrupt-parent = <&mpic>;
big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30
interrupt-parent = <&mpic>;
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
};
PowerPC,8641@1 {
device_type = "cpu";
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
soc8641@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
soc8641@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <00001000 f8001000 000ff000
80000000 80000000 20000000
device_type = "soc";
ranges = <00001000 f8001000 000ff000
80000000 80000000 20000000
reg = <1 20 2
1 a0 2
1 4d0 2>;
reg = <1 20 2
1 a0 2
1 4d0 2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent =
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent =
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
soc866@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
soc866@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
device_type = "mpc8xx-pic";
compatible = "CPM";
};
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
device_type = "cpm-pic";
compatible = "CPM";
};
device_type = "cpm-pic";
compatible = "CPM";
};
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
soc885@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
soc885@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
device_type = "mpc8xx-pic";
compatible = "CPM";
};
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
device_type = "cpm-pic";
compatible = "CPM";
};
device_type = "cpm-pic";
compatible = "CPM";
};
mv64x60@f1000000 { /* Marvell Discovery */
#address-cells = <1>;
#size-cells = <1>;
mv64x60@f1000000 { /* Marvell Discovery */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <1>;
model = "mv64360"; /* Default */
compatible = "marvell,mv64x60";
clock-frequency = <7f28155>; /* 133.333333 MHz */
model = "mv64360"; /* Default */
compatible = "marvell,mv64x60";
clock-frequency = <7f28155>; /* 133.333333 MHz */