ARM: perf: index PMU registers from zero
authorWill Deacon <will.deacon@arm.com>
Tue, 19 Jul 2011 21:43:28 +0000 (22:43 +0100)
committerWill Deacon <will.deacon@arm.com>
Wed, 31 Aug 2011 09:18:01 +0000 (10:18 +0100)
commitecf5a893211c26e02b9d4cfd6ba2183473ac0203
treeaccf48ac99027c2b3fcc81217569abae827ad80d
parentd2b41f7456223ba6abd3b38d7b54be97914f3aa5
ARM: perf: index PMU registers from zero

ARM PMU code used to use 1-based indices for PMU registers. This caused
several data structures (pmu_hw_events::{active_events, used_mask, events})
to have an unused element at index zero. ARMPMU_MAX_HWEVENTS still takes
this indexing into account, and currently equates to 33.

This patch updates the core ARM perf code to use the 0th index again.

Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm/kernel/perf_event.c