ARM: perf: index PMU registers from zero

ARM PMU code used to use 1-based indices for PMU registers. This caused
several data structures (pmu_hw_events::{active_events, used_mask, events})
to have an unused element at index zero. ARMPMU_MAX_HWEVENTS still takes
this indexing into account, and currently equates to 33.

This patch updates the core ARM perf code to use the 0th index again.

Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index d507fe1..c668c91 100644 (file)
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -35,7 +35,7 @@ static struct platform_device *pmu_device;
 static DEFINE_RAW_SPINLOCK(pmu_lock);
 
 /*
- * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
+ * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
  * another platform that supports more, we need to increase this to be the
  * largest of all platforms.
  *
@@ -43,13 +43,12 @@ static DEFINE_RAW_SPINLOCK(pmu_lock);
  *  cycle counter CCNT + 31 events counters CNT0..30.
  *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
  */
-#define ARMPMU_MAX_HWEVENTS            33
+#define ARMPMU_MAX_HWEVENTS            32
 
 /* The events for a given CPU. */
 struct cpu_hw_events {
        /*
-        * The events that are active on the CPU for the given index. Index 0
-        * is reserved.
+        * The events that are active on the CPU for the given index.
         */
        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
 
@@ -597,7 +596,7 @@ static void armpmu_enable(struct pmu *pmu)
        if (!armpmu)
                return;
 
-       for (idx = 0; idx <= armpmu->num_events; ++idx) {
+       for (idx = 0; idx < armpmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
 
                if (!event)