? "Failed" : "OK");
}
break;
-
+ default:
+ /* AMD Hudson needs the similar snoop, as it seems... */
+ if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
+ update_pci_byte(chip->pci,
+ ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
+ 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
+ break;
}
}
}
}
+ /* AMD chipsets often cause the communication stalls upon certain
+ * sequence like the pin-detection. It seems that forcing the synced
+ * access works around the stall. Grrr...
+ */
+ if (chip->pci->vendor == PCI_VENDOR_ID_AMD ||
+ chip->pci->vendor == PCI_VENDOR_ID_ATI) {
+ snd_printk(KERN_INFO SFX "Enable sync_write for AMD chipset\n");
+ chip->bus->sync_write = 1;
+ chip->bus->allow_bus_reset = 1;
+ }
+
/* Then create codec instances */
for (c = 0; c < max_slots; c++) {
if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
/* Check VIA/ATI HD Audio Controller exist */
switch (chip->driver_type) {
case AZX_DRIVER_VIA:
- case AZX_DRIVER_ATI:
/* Use link position directly, avoid any transfer problem. */
return POS_FIX_VIACOMBO;
+ case AZX_DRIVER_ATI:
+ /* ATI chipsets don't work well with position-buffer */
+ return POS_FIX_LPIB;
+ case AZX_DRIVER_GENERIC:
+ /* AMD chipsets also don't work with position-buffer */
+ if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
+ return POS_FIX_LPIB;
+ break;
}
return POS_FIX_AUTO;
gcap &= ~ICH6_GCAP_64OK;
pci_dev_put(p_smbus);
}
+ } else {
+ /* FIXME: not sure whether this is really needed, but
+ * Hudson isn't stable enough for allowing everything...
+ * let's check later again.
+ */
+ if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
+ gcap &= ~ICH6_GCAP_64OK;
}
/* disable 64bit DMA address for Teradici */