/* STATESTS int mask: SD2,SD1,SD0 */
#define STATESTS_INT_MASK 0x07
-#define AZX_MAX_CODECS 3
/* SD_CTL bits */
#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
* Codec initialization
*/
+static unsigned int azx_max_codecs[] __devinitdata = {
+ [AZX_DRIVER_ICH] = 3,
+ [AZX_DRIVER_ATI] = 4,
+ [AZX_DRIVER_ATIHDMI] = 4,
+ [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
+ [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
+ [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
+ [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
+};
+
static int __devinit azx_codec_create(struct azx *chip, const char *model)
{
struct hda_bus_template bus_temp;
return err;
codecs = 0;
- for (c = 0; c < AZX_MAX_CODECS; c++) {
+ for (c = 0; c < azx_max_codecs[chip->driver_type]; c++) {
if ((chip->codec_mask & (1 << c)) & probe_mask) {
err = snd_hda_codec_new(chip->bus, c, NULL);
if (err < 0)
runtime->hw.rates = hinfo->rates;
snd_pcm_limit_hw_rates(runtime);
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
+ 128);
+ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
+ 128);
if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
azx_release_device(azx_dev);
mutex_unlock(&chip->open_mutex);