/* board specific information */
u32 board_flags;
- const char *bus_id;
+ u32 bus_id;
+ u32 phy_id;
u8 mac_addr[6];
};
struct gianfar_mdio_data {
- /* device specific information */
- u32 paddr;
-
/* board specific information */
int irq[32];
};
#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
#define FSL_I2C_DEV_CLOCK_5200 0x00000002
+
+enum fsl_usb2_operating_modes {
+ FSL_USB2_MPH_HOST,
+ FSL_USB2_DR_HOST,
+ FSL_USB2_DR_DEVICE,
+ FSL_USB2_DR_OTG,
+};
+
+enum fsl_usb2_phy_modes {
+ FSL_USB2_PHY_NONE,
+ FSL_USB2_PHY_ULPI,
+ FSL_USB2_PHY_UTMI,
+ FSL_USB2_PHY_UTMI_WIDE,
+ FSL_USB2_PHY_SERIAL,
+};
+
+struct fsl_usb2_platform_data {
+ /* board specific information */
+ enum fsl_usb2_operating_modes operating_mode;
+ enum fsl_usb2_phy_modes phy_mode;
+ unsigned int port_enables;
+};
+
+/* Flags in fsl_usb2_mph_platform_data */
+#define FSL_USB2_PORT0_ENABLED 0x00000001
+#define FSL_USB2_PORT1_ENABLED 0x00000002
+
+struct fsl_spi_platform_data {
+ u32 initial_spmode; /* initial SPMODE value */
+ u16 bus_num;
+
+ /* board specific information */
+ u16 max_chipselect;
+ void (*activate_cs)(u8 cs, u8 polarity);
+ void (*deactivate_cs)(u8 cs, u8 polarity);
+ u32 sysclk;
+};
+
#endif /* _FSL_DEVICE_H_ */
#endif /* __KERNEL__ */