*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
/* misc settings */
* leaving the correct space for initial global data structure above that
* address while providing maximum stack area below.
*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* Defines for SPL */
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
+#define CFG_SYS_MASTER_CLOCK (198656000/2)
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x2060bf09
-#define CONFIG_SYS_MCKR 0x100
-#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB 0x10483f0e
+#define CFG_SYS_AT91_PLLA 0x2060bf09
+#define CFG_SYS_MCKR 0x100
+#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB 0x10483f0e
#endif /* __CONFIG_H */