#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* PAXK FPGA Definitions */
-#define CONFIG_SYS_CSPR3_EXT (0x00)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
+#define CFG_SYS_CSPR3_EXT (0x00)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
-#define CONFIG_SYS_CS3_FTIM3 0x04000000
+#define CFG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define KM_LIU_RST 0