#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifdef CONFIG_NAND_BOOT
#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10)
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT (0x0)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
- CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
+ CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/*
* NAND Flash Definitions
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_PWR_CTL2 0x21
#define QIXIS_PWR_CTL2_PCTL 0x2
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/*
* QIXIS Timing parameters for IFC GPCM
*/
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
FTIM0_GPCM_TEADC(0xe) | \
FTIM0_GPCM_TEAHC(0xe))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
FTIM2_GPCM_TCH(0xe) | \
FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_FPGA_FTIM3 0x0
#endif
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#endif
/*
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
git.openpandora.org / pandora-u-boot.git / blobdiff