#define PCI_IRQ_NONE 0xffffffff
+#define PCI_CACHE_LINE_BYTES 64
+
static inline void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
struct pci_dev;
struct pci_iommu_ops {
- void *(*alloc_consistent)(struct pci_dev *, size_t, dma_addr_t *);
+ void *(*alloc_consistent)(struct pci_dev *, size_t, dma_addr_t *, gfp_t);
void (*free_consistent)(struct pci_dev *, size_t, void *, dma_addr_t);
dma_addr_t (*map_single)(struct pci_dev *, void *, size_t, int);
void (*unmap_single)(struct pci_dev *, dma_addr_t, size_t, int);
void (*dma_sync_sg_for_cpu)(struct pci_dev *, struct scatterlist *, int, int);
};
-extern struct pci_iommu_ops *pci_iommu_ops;
+extern const struct pci_iommu_ops *pci_iommu_ops;
/* Allocate and map kernel buffer using consistent mode DMA for a device.
* hwdev should be valid struct pci_dev pointer for PCI devices.
*/
static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
{
- return pci_iommu_ops->alloc_consistent(hwdev, size, dma_handle);
+ return pci_iommu_ops->alloc_consistent(hwdev, size, dma_handle, GFP_ATOMIC);
}
/* Free and unmap a consistent DMA buffer.
enum pci_mmap_state mmap_state,
int write_combine);
-/* Platform specific MWI support. */
-#define HAVE_ARCH_PCI_MWI
-extern int pcibios_prep_mwi(struct pci_dev *dev);
-
extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res);
return PCI_IRQ_NONE;
}
+struct device_node;
+extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
+
#endif /* __KERNEL__ */
#endif /* __SPARC64_PCI_H */