Begin consolidation of of_device.h

[pandora-kernel.git] / include / asm-powerpc / reg.h

diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index a3631b1..281011e 100644 (file)
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -166,6 +166,7 @@
 #define SPRN_TBWU      0x11D   /* Time Base Upper Register (super, R/W) */
 #define SPRN_SPURR     0x134   /* Scaled PURR */
 #define SPRN_HIOR      0x137   /* 970 Hypervisor interrupt offset */
+#define SPRN_LPCR      0x13E   /* LPAR Control Register */
 #define SPRN_DBAT0L    0x219   /* Data BAT 0 Lower Register */
 #define SPRN_DBAT0U    0x218   /* Data BAT 0 Upper Register */
 #define SPRN_DBAT1L    0x21B   /* Data BAT 1 Lower Register */
@@ -391,6 +392,12 @@
 #define SPRN_HSRR0     0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1     0x13B   /* Save/Restore Register 1 */
 
+#define SPRN_TBCTL     0x35f   /* PA6T Timebase control register */
+#define   TBCTL_FREEZE         0x0000000000000000ull /* Freeze all tbs */
+#define   TBCTL_RESTART                0x0000000100000000ull /* Restart all tbs */
+#define   TBCTL_UPDATE_UPPER   0x0000000200000000ull /* Set upper 32 bits */
+#define   TBCTL_UPDATE_LOWER   0x0000000300000000ull /* Set lower 32 bits */
+
 #ifndef SPRN_SVR
 #define SPRN_SVR       0x11E   /* System Version Register */
 #endif
@@ -446,6 +453,8 @@
 #define SPRN_MMCRA     0x312
 #define   MMCRA_SIHV   0x10000000UL /* state of MSR HV when SIAR set */
 #define   MMCRA_SIPR   0x08000000UL /* state of MSR PR when SIAR set */
+#define   MMCRA_SLOT   0x07000000UL /* SLOT bits (37-39) */
+#define   MMCRA_SLOT_SHIFT     24
 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
@@ -462,6 +471,69 @@
 #define SPRN_SIAR      780
 #define SPRN_SDAR      781
 
+#define SPRN_PA6T_MMCR0 795
+#define   PA6T_MMCR0_EN0       0x0000000000000001UL
+#define   PA6T_MMCR0_EN1       0x0000000000000002UL
+#define   PA6T_MMCR0_EN2       0x0000000000000004UL
+#define   PA6T_MMCR0_EN3       0x0000000000000008UL
+#define   PA6T_MMCR0_EN4       0x0000000000000010UL
+#define   PA6T_MMCR0_EN5       0x0000000000000020UL
+#define   PA6T_MMCR0_SUPEN     0x0000000000000040UL
+#define   PA6T_MMCR0_PREN      0x0000000000000080UL
+#define   PA6T_MMCR0_HYPEN     0x0000000000000100UL
+#define   PA6T_MMCR0_FCM0      0x0000000000000200UL
+#define   PA6T_MMCR0_FCM1      0x0000000000000400UL
+#define   PA6T_MMCR0_INTGEN    0x0000000000000800UL
+#define   PA6T_MMCR0_INTEN0    0x0000000000001000UL
+#define   PA6T_MMCR0_INTEN1    0x0000000000002000UL
+#define   PA6T_MMCR0_INTEN2    0x0000000000004000UL
+#define   PA6T_MMCR0_INTEN3    0x0000000000008000UL
+#define   PA6T_MMCR0_INTEN4    0x0000000000010000UL
+#define   PA6T_MMCR0_INTEN5    0x0000000000020000UL
+#define   PA6T_MMCR0_DISCNT    0x0000000000040000UL
+#define   PA6T_MMCR0_UOP       0x0000000000080000UL
+#define   PA6T_MMCR0_TRG       0x0000000000100000UL
+#define   PA6T_MMCR0_TRGEN     0x0000000000200000UL
+#define   PA6T_MMCR0_TRGREG    0x0000000001600000UL
+#define   PA6T_MMCR0_SIARLOG   0x0000000002000000UL
+#define   PA6T_MMCR0_SDARLOG   0x0000000004000000UL
+#define   PA6T_MMCR0_PROEN     0x0000000008000000UL
+#define   PA6T_MMCR0_PROLOG    0x0000000010000000UL
+#define   PA6T_MMCR0_DAMEN2    0x0000000020000000UL
+#define   PA6T_MMCR0_DAMEN3    0x0000000040000000UL
+#define   PA6T_MMCR0_DAMEN4    0x0000000080000000UL
+#define   PA6T_MMCR0_DAMEN5    0x0000000100000000UL
+#define   PA6T_MMCR0_DAMSEL2   0x0000000200000000UL
+#define   PA6T_MMCR0_DAMSEL3   0x0000000400000000UL
+#define   PA6T_MMCR0_DAMSEL4   0x0000000800000000UL
+#define   PA6T_MMCR0_DAMSEL5   0x0000001000000000UL
+#define   PA6T_MMCR0_HANDDIS   0x0000002000000000UL
+#define   PA6T_MMCR0_PCTEN     0x0000004000000000UL
+#define   PA6T_MMCR0_SOCEN     0x0000008000000000UL
+#define   PA6T_MMCR0_SOCMOD    0x0000010000000000UL
+
+#define SPRN_PA6T_MMCR1 798
+#define   PA6T_MMCR1_ES2       0x00000000000000ffUL
+#define   PA6T_MMCR1_ES3       0x000000000000ff00UL
+#define   PA6T_MMCR1_ES4       0x0000000000ff0000UL
+#define   PA6T_MMCR1_ES5       0x00000000ff000000UL
+
+#define SPRN_PA6T_SIAR  780
+#define SPRN_PA6T_UPMC0 771
+#define SPRN_PA6T_UPMC1 772
+#define SPRN_PA6T_UPMC2 773
+#define SPRN_PA6T_UPMC3 774
+#define SPRN_PA6T_UPMC4 775
+#define SPRN_PA6T_UPMC5 776
+#define SPRN_PA6T_UMMCR0 779
+#define SPRN_PA6T_UMMCR1 782
+#define SPRN_PA6T_PMC0  787
+#define SPRN_PA6T_PMC1  788
+#define SPRN_PA6T_PMC2  789
+#define SPRN_PA6T_PMC3  790
+#define SPRN_PA6T_PMC4  791
+#define SPRN_PA6T_PMC5  792
+
 #else /* 32-bit */
 #define SPRN_MMCR0     952     /* Monitor Mode Control Register 0 */
 #define   MMCR0_FC     0x80000000UL /* freeze counters */