Merge commit 'v2.6.26-rc9' into sched/devel

[pandora-kernel.git] / include / asm-powerpc / qe.h

diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index bcf60be..c3be6e2 100644 (file)
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -84,6 +84,8 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
 
 /* QE internal API */
 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
+enum qe_clock qe_clock_source(const char *source);
+unsigned int qe_get_brg_clk(void);
 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
 int qe_get_snum(void);
 void qe_put_snum(u8 snum);
@@ -91,7 +93,68 @@ unsigned long qe_muram_alloc(int size, int align);
 int qe_muram_free(unsigned long offset);
 unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
 void qe_muram_dump(void);
-void *qe_muram_addr(unsigned long offset);
+
+static inline void __iomem *qe_muram_addr(unsigned long offset)
+{
+       return (void __iomem *)&qe_immr->muram[offset];
+}
+
+static inline unsigned long qe_muram_offset(void __iomem *addr)
+{
+       return addr - (void __iomem *)qe_immr->muram;
+}
+
+/* Structure that defines QE firmware binary files.
+ *
+ * See Documentation/powerpc/qe-firmware.txt for a description of these
+ * fields.
+ */
+struct qe_firmware {
+       struct qe_header {
+               __be32 length;  /* Length of the entire structure, in bytes */
+               u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
+               u8 version;     /* Version of this layout. First ver is '1' */
+       } header;
+       u8 id[62];      /* Null-terminated identifier string */
+       u8 split;       /* 0 = shared I-RAM, 1 = split I-RAM */
+       u8 count;       /* Number of microcode[] structures */
+       struct {
+               __be16 model;           /* The SOC model  */
+               u8 major;               /* The SOC revision major */
+               u8 minor;               /* The SOC revision minor */
+       } __attribute__ ((packed)) soc;
+       u8 padding[4];                  /* Reserved, for alignment */
+       __be64 extended_modes;          /* Extended modes */
+       __be32 vtraps[8];               /* Virtual trap addresses */
+       u8 reserved[4];                 /* Reserved, for future expansion */
+       struct qe_microcode {
+               u8 id[32];              /* Null-terminated identifier */
+               __be32 traps[16];       /* Trap addresses, 0 == ignore */
+               __be32 eccr;            /* The value for the ECCR register */
+               __be32 iram_offset;     /* Offset into I-RAM for the code */
+               __be32 count;           /* Number of 32-bit words of the code */
+               __be32 code_offset;     /* Offset of the actual microcode */
+               u8 major;               /* The microcode version major */
+               u8 minor;               /* The microcode version minor */
+               u8 revision;            /* The microcode version revision */
+               u8 padding;             /* Reserved, for alignment */
+               u8 reserved[4];         /* Reserved, for future expansion */
+       } __attribute__ ((packed)) microcode[1];
+       /* All microcode binaries should be located here */
+       /* CRC32 should be located here, after the microcode binaries */
+} __attribute__ ((packed));
+
+struct qe_firmware_info {
+       char id[64];            /* Firmware name */
+       u32 vtraps[8];          /* Virtual trap addresses */
+       u64 extended_modes;     /* Extended modes */
+};
+
+/* Upload a firmware to the QE */
+int qe_upload_firmware(const struct qe_firmware *firmware);
+
+/* Obtain information on the uploaded firmware */
+struct qe_firmware_info *qe_get_firmware_info(void);
 
 /* Buffer descriptors */
 struct qe_bd {
@@ -328,6 +391,15 @@ enum comm_dir {
 
 #define QE_SDEBCR_BA_MASK      0x01FFFFFF
 
+/* Communication Processor */
+#define QE_CP_CERCR_MEE                0x8000  /* Multi-user RAM ECC enable */
+#define QE_CP_CERCR_IEE                0x4000  /* Instruction RAM ECC enable */
+#define QE_CP_CERCR_CIR                0x0800  /* Common instruction RAM */
+
+/* I-RAM */
+#define QE_IRAM_IADD_AIE       0x80000000      /* Auto Increment Enable */
+#define QE_IRAM_IADD_BADDR     0x00080000      /* Base Address */
+
 /* UPC */
 #define UPGCR_PROTOCOL 0x80000000      /* protocol ul2 or pl2 */
 #define UPGCR_TMS      0x40000000      /* Transmit master/slave mode */