#include <linux/stringify.h>
#include <linux/config.h>
+#include <asm/asm-compat.h>
-#ifdef __ASSEMBLY__
+#ifndef __ASSEMBLY__
+#error __FILE__ should only be used in assembler files
+#else
+
+#define SZL (BITS_PER_LONG/8)
/*
* Macros for storing registers into and loading registers from
#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
-/* Macros to adjust thread priority for Iseries hardware multithreading */
-#define HMT_VERY_LOW or 31,31,31 # very low priority\n"
-#define HMT_LOW or 1,1,1
-#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority\n"
-#define HMT_MEDIUM or 2,2,2
-#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority\n"
-#define HMT_HIGH or 3,3,3
+/* Macros to adjust thread priority for hardware multithreading */
+#define HMT_VERY_LOW or 31,31,31 # very low priority
+#define HMT_LOW or 1,1,1
+#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
+#define HMT_MEDIUM or 2,2,2
+#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
+#define HMT_HIGH or 3,3,3
/* handle instructions that older assemblers may not know */
#define RFCI .long 0x4c000066 /* rfci instruction */
#define RFDI .long 0x4c00004e /* rfdi instruction */
#define RFMCI .long 0x4c00004c /* rfmci instruction */
+#ifdef __KERNEL__
#ifdef CONFIG_PPC64
#define XGLUE(a,b) a##b
* loads the address of 'name' into 'rn'
*
* LOADBASE( rn, name )
- * loads the address (less the low 16 bits) of 'name' into 'rn'
+ * loads the address (possibly without the low 16 bits) of 'name' into 'rn'
* suitable for base+disp addressing
*/
#ifdef __powerpc64__
ori rn,rn,name##@l
#define LOADBASE(rn,name) \
- .section .toc,"aw"; \
-1: .tc name[TC],name; \
- .previous; \
- ld rn,1b@toc(r2)
+ ld rn,name@got(r2)
#define OFF(name) 0
oris reg,reg,(label)@h; \
ori reg,reg,(label)@l;
-/* operations for longs and pointers */
-#define LDL ld
-#define STL std
-#define CMPI cmpdi
+/* offsets for stack frame layout */
+#define LRSAVE 16
#else /* 32-bit */
#define LOADADDR(rn,name) \
#define OFF(name) name@l
-/* operations for longs and pointers */
-#define LDL lwz
-#define STL stw
-#define CMPI cmpwi
+/* offsets for stack frame layout */
+#define LRSAVE 4
#endif
#endif
-#ifdef CONFIG_IBM405_ERR77
-#define PPC405_ERR77(ra,rb) dcbt ra, rb;
-#define PPC405_ERR77_SYNC sync;
-#else
-#define PPC405_ERR77(ra,rb)
-#define PPC405_ERR77_SYNC
-#endif
-
-
#ifdef CONFIG_IBM440EP_ERR42
#define PPC440EP_ERR42 isync
#else
#if defined(CONFIG_BOOKE)
+#define toreal(rd)
+#define fromreal(rd)
+
#define tophys(rd,rs) \
addis rd,rs,0
addis rd,rs,0
#elif defined(CONFIG_PPC64)
-/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
- * Then we can easily do this with one asm insn. -Peter
- */
+#define toreal(rd) /* we can access c000... in real mode */
+#define fromreal(rd)
+
#define tophys(rd,rs) \
- lis rd,((KERNELBASE>>48)&0xFFFF); \
- rldicr rd,rd,32,31; \
- sub rd,rs,rd
+ clrldi rd,rs,2
#define tovirt(rd,rs) \
- lis rd,((KERNELBASE>>48)&0xFFFF); \
- rldicr rd,rd,32,31; \
- add rd,rs,rd
+ rotldi rd,rs,16; \
+ ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
+ rotldi rd,rd,48
#else
/*
* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
* physical base address of RAM at compile time.
*/
+#define toreal(rd) tophys(rd,rd)
+#define fromreal(rd) tovirt(rd,rd)
+
#define tophys(rd,rs) \
0: addis rd,rs,-KERNELBASE@h; \
.section ".vtop_fixup","aw"; \
#define CLR_TOP32(r)
#endif
+#endif /* __KERNEL__ */
+
/* The boring bits... */
/* Condition Register Bit Fields */
#define N_SLINE 68
#define N_SO 100
-#define ASM_CONST(x) x
-#else
- #define __ASM_CONST(x) x##UL
- #define ASM_CONST(x) __ASM_CONST(x)
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PPC_ASM_H */