Pull asus into release branch

[pandora-kernel.git] / include / asm-i386 / msr.h

diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h
index 5679d49..2ad3f30 100644 (file)
--- a/include/asm-i386/msr.h
+++ b/include/asm-i386/msr.h
@@ -83,6 +83,20 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
                          : "c" (counter))
 #endif /* !CONFIG_PARAVIRT */
 
+#ifdef CONFIG_SMP
+void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
+void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+#else  /*  CONFIG_SMP  */
+static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+{
+       rdmsr(msr_no, *l, *h);
+}
+static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+{
+       wrmsr(msr_no, l, h);
+}
+#endif  /*  CONFIG_SMP  */
+
 /* symbolic names for some interesting MSRs */
 /* Intel defined MSRs. */
 #define MSR_IA32_P5_MC_ADDR            0
@@ -100,6 +114,8 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 
 #define MSR_P6_PERFCTR0                0xc1
 #define MSR_P6_PERFCTR1                0xc2
+#define MSR_FSB_FREQ           0xcd
+
 
 #define MSR_IA32_BBL_CR_CTL            0x119
 
@@ -130,6 +146,9 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 #define MSR_IA32_PERF_STATUS           0x198
 #define MSR_IA32_PERF_CTL              0x199
 
+#define MSR_IA32_MPERF                 0xE7
+#define MSR_IA32_APERF                 0xE8
+
 #define MSR_IA32_THERM_CONTROL         0x19a
 #define MSR_IA32_THERM_INTERRUPT       0x19b
 #define MSR_IA32_THERM_STATUS          0x19c
@@ -256,6 +275,8 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 #define MSR_K7_FID_VID_CTL             0xC0010041
 #define MSR_K7_FID_VID_STATUS          0xC0010042
 
+#define MSR_K8_ENABLE_C1E              0xC0010055
+
 /* extended feature register */
 #define MSR_EFER                       0xc0000080
 
@@ -302,4 +323,7 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 #define MSR_CORE_PERF_GLOBAL_CTRL      0x38f
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL  0x390
 
+/* Geode defined MSRs */
+#define MSR_GEODE_BUSCONT_CONF0         0x1900
+
 #endif /* __ASM_MSR_H */