Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

[pandora-kernel.git] / include / asm-arm / arch-pxa / regs-ssp.h

diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 991cb68..3c04cde 100644 (file)
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -20,6 +20,10 @@
 #define SSTSS          (0x38)  /* SSP Timeslot Status */
 #define SSACD          (0x3C)  /* SSP Audio Clock Divider */
 
+#if defined(CONFIG_PXA3xx)
+#define SSACDD         (0x40)  /* SSP Audio Clock Dither Divider */
+#endif
+
 /* Common PXA2xx bits first */
 #define SSCR0_DSS      (0x0000000f)    /* Data Size Select (mask) */
 #define SSCR0_DataSize(x)  ((x) - 1)   /* Data Size Select [4..16] */
@@ -29,10 +33,12 @@
 #define SSCR0_National (0x2 << 4)      /* National Microwire */
 #define SSCR0_ECS      (1 << 6)        /* External clock select */
 #define SSCR0_SSE      (1 << 7)        /* Synchronous Serial Port Enable */
+
 #if defined(CONFIG_PXA25x)
 #define SSCR0_SCR      (0x0000ff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
-#elif defined(CONFIG_PXA27x)
+
+#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define SSCR0_SCR      (0x000fff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
 #define SSCR0_EDSS     (1 << 20)       /* Extended data size select */
@@ -45,6 +51,10 @@
 #define SSCR0_MOD      (1 << 31)       /* Mode (normal or network) */
 #endif
 
+#if defined(CONFIG_PXA3xx)
+#define SSCR0_FPCKE    (1 << 29)       /* FIFO packing enable */
+#endif
+
 #define SSCR1_RIE      (1 << 0)        /* Receive FIFO Interrupt Enable */
 #define SSCR1_TIE      (1 << 1)        /* Transmit FIFO Interrupt Enable */
 #define SSCR1_LBM      (1 << 2)        /* Loop-Back Mode */
@@ -85,6 +95,7 @@
 #define SSCR1_RSRE             (1 << 20)       /* Receive Service Request Enable */
 #define SSCR1_TINTE            (1 << 19)       /* Receiver Time-out Interrupt enable */
 #define SSCR1_PINTE            (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
+#define SSCR1_IFS              (1 << 16)       /* Invert Frame Signal */
 #define SSCR1_STRF             (1 << 15)       /* Select FIFO or EFWR */
 #define SSCR1_EFWR             (1 << 14)       /* Enable FIFO Write/Read */
 
@@ -108,5 +119,9 @@
 #define SSACD_SCDB             (1 << 3)        /* SSPSYSCLK Divider Bypass */
 #define SSACD_ACPS(x)          ((x) << 4)      /* Audio clock PLL select */
 #define SSACD_ACDS(x)          ((x) << 0)      /* Audio clock divider select */
+#if defined(CONFIG_PXA3xx)
+#define SSACD_SCDX8            (1 << 7)        /* SYSCLK division ratio select */
+#endif
+
 
 #endif /* __ASM_ARCH_REGS_SSP_H */