int nvclk_khz;
char mem_page_miss;
char mem_latency;
- int memory_type;
+ u32 memory_type;
int memory_width;
char enable_video;
char gr_during_vid;
}
}
}
+
+ /* non-zero: M/N/P/clock values assigned. zero: error (not set) */
return (DeltaOld != 0xFFFFFFFF);
}
/*
int dotClock
)
{
- int pixelDepth, VClk, m, n, p;
+ int pixelDepth;
+ int uninitialized_var(VClk),uninitialized_var(m),
+ uninitialized_var(n), uninitialized_var(p);
+
/*
* Save mode parameters.
*/
)
{
struct pci_dev* dev;
- int amt;
+ u32 amt;
#ifdef __BIG_ENDIAN
/* turn on big endian register access */