}
#ifdef CONFIG_CPU_FREQ
- pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
- pxafb_display_dma_period(var),
- get_clk_frequency_khz(0));
+ pr_debug("pxafb: dma period = %d ps\n",
+ pxafb_display_dma_period(var));
#endif
return 0;
}
}
-static int pxafb_decode_mach_info(struct pxafb_info *fbi,
- struct pxafb_mach_info *inf)
+static void pxafb_decode_mach_info(struct pxafb_info *fbi,
+ struct pxafb_mach_info *inf)
{
unsigned int lcd_conn = inf->lcd_conn;
fbi->lccr0 = inf->lccr0;
fbi->lccr3 = inf->lccr3;
fbi->lccr4 = inf->lccr4;
- return -EINVAL;
+ goto decode_mode;
}
if (lcd_conn == LCD_MONO_STN_8BPP)
fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
+decode_mode:
pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
- return 0;
}
static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
struct pxafb_info *fbi;
void *addr;
struct pxafb_mach_info *inf = dev->platform_data;
- struct pxafb_mode_info *mode = inf->modes;
/* Alloc the pxafb_info and pseudo_palette in one step */
fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);