#include <linux/workqueue.h>
#include <linux/hardirq.h>
#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <plat/sram.h>
#include <plat/clock.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "dss.h"
#include "dss_features.h"
+#include "dispc.h"
/* DISPC */
#define DISPC_SZ_REGS SZ_4K
-struct dispc_reg { u16 idx; };
-
-#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
-
-/*
- * DISPC common registers and
- * DISPC channel registers , ch = 0 for LCD, ch = 1 for
- * DIGIT, and ch = 2 for LCD2
- */
-#define DISPC_REVISION DISPC_REG(0x0000)
-#define DISPC_SYSCONFIG DISPC_REG(0x0010)
-#define DISPC_SYSSTATUS DISPC_REG(0x0014)
-#define DISPC_IRQSTATUS DISPC_REG(0x0018)
-#define DISPC_IRQENABLE DISPC_REG(0x001C)
-#define DISPC_CONTROL DISPC_REG(0x0040)
-#define DISPC_CONTROL2 DISPC_REG(0x0238)
-#define DISPC_CONFIG DISPC_REG(0x0044)
-#define DISPC_CONFIG2 DISPC_REG(0x0620)
-#define DISPC_CAPABLE DISPC_REG(0x0048)
-#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
- (ch == 1 ? 0x0050 : 0x03AC))
-#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
- (ch == 1 ? 0x0058 : 0x03B0))
-#define DISPC_LINE_STATUS DISPC_REG(0x005C)
-#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
-#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
-#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
-#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
-#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
-#define DISPC_SIZE_DIG DISPC_REG(0x0078)
-#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
-
-/* DISPC GFX plane */
-#define DISPC_GFX_BA0 DISPC_REG(0x0080)
-#define DISPC_GFX_BA1 DISPC_REG(0x0084)
-#define DISPC_GFX_POSITION DISPC_REG(0x0088)
-#define DISPC_GFX_SIZE DISPC_REG(0x008C)
-#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
-#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
-#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
-#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
-#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
-#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
-#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
-
-#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
-#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
-#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
-#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
-#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
-#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
-
-#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
-
-/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
-#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
-
-#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
-#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
-#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
-#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
-#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
-#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
-#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
-#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
-#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
-#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
-#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
-#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
-#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
-
-/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
-/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
-/* coef index i = {0, 1, 2, 3, 4} */
-#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
-/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
-
-#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
-
-#define DISPC_DIVISOR DISPC_REG(0x0804)
-
#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
DISPC_IRQ_OCP_ERR | \
DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
s8 vc00;
};
+enum omap_burst_size {
+ BURST_SIZE_X2 = 0,
+ BURST_SIZE_X4 = 1,
+ BURST_SIZE_X8 = 2,
+};
+
#define REG_GET(idx, start, end) \
FLD_GET(dispc_read_reg(idx), start, end)
#define REG_FLD_MOD(idx, val, start, end) \
dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
-static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
- DISPC_VID_ATTRIBUTES(0),
- DISPC_VID_ATTRIBUTES(1) };
-
struct dispc_irq_stats {
unsigned long last_reset;
unsigned irq_count;
static struct {
struct platform_device *pdev;
void __iomem *base;
+
+ int ctx_loss_cnt;
+
int irq;
+ struct clk *dss_clk;
u32 fifo_size[3];
u32 error_irqs;
struct work_struct error_work;
+ bool ctx_valid;
u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
#endif
} dispc;
+enum omap_color_component {
+ /* used for all color formats for OMAP3 and earlier
+ * and for RGB and Y color component on OMAP4
+ */
+ DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
+ /* used for UV component for
+ * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
+ * color formats on OMAP4
+ */
+ DISPC_COLOR_COMPONENT_UV = 1 << 1,
+};
+
static void _omap_dispc_set_irqs(void);
-static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
+static inline void dispc_write_reg(const u16 idx, u32 val)
{
- __raw_writel(val, dispc.base + idx.idx);
+ __raw_writel(val, dispc.base + idx);
}
-static inline u32 dispc_read_reg(const struct dispc_reg idx)
+static inline u32 dispc_read_reg(const u16 idx)
{
- return __raw_readl(dispc.base + idx.idx);
+ return __raw_readl(dispc.base + idx);
+}
+
+static int dispc_get_ctx_loss_count(void)
+{
+ struct device *dev = &dispc.pdev->dev;
+ struct omap_display_platform_data *pdata = dev->platform_data;
+ struct omap_dss_board_info *board_data = pdata->board_data;
+ int cnt;
+
+ if (!board_data->get_context_loss_count)
+ return -ENOENT;
+
+ cnt = board_data->get_context_loss_count(dev);
+
+ WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
+
+ return cnt;
}
#define SR(reg) \
- dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
+ dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
#define RR(reg) \
- dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
+ dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
-void dispc_save_context(void)
+static void dispc_save_context(void)
{
- if (cpu_is_omap24xx())
- return;
+ int i;
+
+ DSSDBG("dispc_save_context\n");
- SR(SYSCONFIG);
SR(IRQENABLE);
SR(CONTROL);
SR(CONFIG);
- SR(DEFAULT_COLOR(0));
- SR(DEFAULT_COLOR(1));
- SR(TRANS_COLOR(0));
- SR(TRANS_COLOR(1));
+ SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
+ SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
+ SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
+ SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
SR(LINE_NUMBER);
- SR(TIMING_H(0));
- SR(TIMING_V(0));
- SR(POL_FREQ(0));
- SR(DIVISORo(0));
- SR(GLOBAL_ALPHA);
- SR(SIZE_DIG);
- SR(SIZE_LCD(0));
+ SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
+ SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
+ SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
+ SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
+ if (dss_has_feature(FEAT_GLOBAL_ALPHA))
+ SR(GLOBAL_ALPHA);
+ SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
+ SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
SR(CONTROL2);
- SR(DEFAULT_COLOR(2));
- SR(TRANS_COLOR(2));
- SR(SIZE_LCD(2));
- SR(TIMING_H(2));
- SR(TIMING_V(2));
- SR(POL_FREQ(2));
- SR(DIVISORo(2));
+ SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
+ SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
+ SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
+ SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
+ SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
SR(CONFIG2);
}
- SR(GFX_BA0);
- SR(GFX_BA1);
- SR(GFX_POSITION);
- SR(GFX_SIZE);
- SR(GFX_ATTRIBUTES);
- SR(GFX_FIFO_THRESHOLD);
- SR(GFX_ROW_INC);
- SR(GFX_PIXEL_INC);
- SR(GFX_WINDOW_SKIP);
- SR(GFX_TABLE_BA);
-
- SR(DATA_CYCLE1(0));
- SR(DATA_CYCLE2(0));
- SR(DATA_CYCLE3(0));
-
- SR(CPR_COEF_R(0));
- SR(CPR_COEF_G(0));
- SR(CPR_COEF_B(0));
+ SR(OVL_BA0(OMAP_DSS_GFX));
+ SR(OVL_BA1(OMAP_DSS_GFX));
+ SR(OVL_POSITION(OMAP_DSS_GFX));
+ SR(OVL_SIZE(OMAP_DSS_GFX));
+ SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
+ SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
+ SR(OVL_ROW_INC(OMAP_DSS_GFX));
+ SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
+ SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
+ SR(OVL_TABLE_BA(OMAP_DSS_GFX));
+
+ SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
+ SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
+ SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
+
+ if (dss_has_feature(FEAT_CPR)) {
+ SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
+ SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
+ SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
+ }
if (dss_has_feature(FEAT_MGR_LCD2)) {
- SR(CPR_COEF_B(2));
- SR(CPR_COEF_G(2));
- SR(CPR_COEF_R(2));
+ if (dss_has_feature(FEAT_CPR)) {
+ SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
+ SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
+ SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
+ }
- SR(DATA_CYCLE1(2));
- SR(DATA_CYCLE2(2));
- SR(DATA_CYCLE3(2));
+ SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
+ SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
+ SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
}
- SR(GFX_PRELOAD);
+ if (dss_has_feature(FEAT_PRELOAD))
+ SR(OVL_PRELOAD(OMAP_DSS_GFX));
/* VID1 */
- SR(VID_BA0(0));
- SR(VID_BA1(0));
- SR(VID_POSITION(0));
- SR(VID_SIZE(0));
- SR(VID_ATTRIBUTES(0));
- SR(VID_FIFO_THRESHOLD(0));
- SR(VID_ROW_INC(0));
- SR(VID_PIXEL_INC(0));
- SR(VID_FIR(0));
- SR(VID_PICTURE_SIZE(0));
- SR(VID_ACCU0(0));
- SR(VID_ACCU1(0));
-
- SR(VID_FIR_COEF_H(0, 0));
- SR(VID_FIR_COEF_H(0, 1));
- SR(VID_FIR_COEF_H(0, 2));
- SR(VID_FIR_COEF_H(0, 3));
- SR(VID_FIR_COEF_H(0, 4));
- SR(VID_FIR_COEF_H(0, 5));
- SR(VID_FIR_COEF_H(0, 6));
- SR(VID_FIR_COEF_H(0, 7));
-
- SR(VID_FIR_COEF_HV(0, 0));
- SR(VID_FIR_COEF_HV(0, 1));
- SR(VID_FIR_COEF_HV(0, 2));
- SR(VID_FIR_COEF_HV(0, 3));
- SR(VID_FIR_COEF_HV(0, 4));
- SR(VID_FIR_COEF_HV(0, 5));
- SR(VID_FIR_COEF_HV(0, 6));
- SR(VID_FIR_COEF_HV(0, 7));
-
- SR(VID_CONV_COEF(0, 0));
- SR(VID_CONV_COEF(0, 1));
- SR(VID_CONV_COEF(0, 2));
- SR(VID_CONV_COEF(0, 3));
- SR(VID_CONV_COEF(0, 4));
-
- SR(VID_FIR_COEF_V(0, 0));
- SR(VID_FIR_COEF_V(0, 1));
- SR(VID_FIR_COEF_V(0, 2));
- SR(VID_FIR_COEF_V(0, 3));
- SR(VID_FIR_COEF_V(0, 4));
- SR(VID_FIR_COEF_V(0, 5));
- SR(VID_FIR_COEF_V(0, 6));
- SR(VID_FIR_COEF_V(0, 7));
-
- SR(VID_PRELOAD(0));
+ SR(OVL_BA0(OMAP_DSS_VIDEO1));
+ SR(OVL_BA1(OMAP_DSS_VIDEO1));
+ SR(OVL_POSITION(OMAP_DSS_VIDEO1));
+ SR(OVL_SIZE(OMAP_DSS_VIDEO1));
+ SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
+ SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
+ SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
+ SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
+ SR(OVL_FIR(OMAP_DSS_VIDEO1));
+ SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 5; i++)
+ SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
+
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
+ }
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
+ SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
+ SR(OVL_FIR2(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
+ if (dss_has_feature(FEAT_PRELOAD))
+ SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
/* VID2 */
- SR(VID_BA0(1));
- SR(VID_BA1(1));
- SR(VID_POSITION(1));
- SR(VID_SIZE(1));
- SR(VID_ATTRIBUTES(1));
- SR(VID_FIFO_THRESHOLD(1));
- SR(VID_ROW_INC(1));
- SR(VID_PIXEL_INC(1));
- SR(VID_FIR(1));
- SR(VID_PICTURE_SIZE(1));
- SR(VID_ACCU0(1));
- SR(VID_ACCU1(1));
-
- SR(VID_FIR_COEF_H(1, 0));
- SR(VID_FIR_COEF_H(1, 1));
- SR(VID_FIR_COEF_H(1, 2));
- SR(VID_FIR_COEF_H(1, 3));
- SR(VID_FIR_COEF_H(1, 4));
- SR(VID_FIR_COEF_H(1, 5));
- SR(VID_FIR_COEF_H(1, 6));
- SR(VID_FIR_COEF_H(1, 7));
-
- SR(VID_FIR_COEF_HV(1, 0));
- SR(VID_FIR_COEF_HV(1, 1));
- SR(VID_FIR_COEF_HV(1, 2));
- SR(VID_FIR_COEF_HV(1, 3));
- SR(VID_FIR_COEF_HV(1, 4));
- SR(VID_FIR_COEF_HV(1, 5));
- SR(VID_FIR_COEF_HV(1, 6));
- SR(VID_FIR_COEF_HV(1, 7));
-
- SR(VID_CONV_COEF(1, 0));
- SR(VID_CONV_COEF(1, 1));
- SR(VID_CONV_COEF(1, 2));
- SR(VID_CONV_COEF(1, 3));
- SR(VID_CONV_COEF(1, 4));
-
- SR(VID_FIR_COEF_V(1, 0));
- SR(VID_FIR_COEF_V(1, 1));
- SR(VID_FIR_COEF_V(1, 2));
- SR(VID_FIR_COEF_V(1, 3));
- SR(VID_FIR_COEF_V(1, 4));
- SR(VID_FIR_COEF_V(1, 5));
- SR(VID_FIR_COEF_V(1, 6));
- SR(VID_FIR_COEF_V(1, 7));
-
- SR(VID_PRELOAD(1));
+ SR(OVL_BA0(OMAP_DSS_VIDEO2));
+ SR(OVL_BA1(OMAP_DSS_VIDEO2));
+ SR(OVL_POSITION(OMAP_DSS_VIDEO2));
+ SR(OVL_SIZE(OMAP_DSS_VIDEO2));
+ SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
+ SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
+ SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
+ SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
+ SR(OVL_FIR(OMAP_DSS_VIDEO2));
+ SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 5; i++)
+ SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
+
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
+ }
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
+ SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
+ SR(OVL_FIR2(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
+ if (dss_has_feature(FEAT_PRELOAD))
+ SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
if (dss_has_feature(FEAT_CORE_CLK_DIV))
SR(DIVISOR);
+
+ dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
+ dispc.ctx_valid = true;
+
+ DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
}
-void dispc_restore_context(void)
+static void dispc_restore_context(void)
{
- RR(SYSCONFIG);
+ int i, ctx;
+
+ DSSDBG("dispc_restore_context\n");
+
+ if (!dispc.ctx_valid)
+ return;
+
+ ctx = dispc_get_ctx_loss_count();
+
+ if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
+ return;
+
+ DSSDBG("ctx_loss_count: saved %d, current %d\n",
+ dispc.ctx_loss_cnt, ctx);
+
/*RR(IRQENABLE);*/
/*RR(CONTROL);*/
RR(CONFIG);
- RR(DEFAULT_COLOR(0));
- RR(DEFAULT_COLOR(1));
- RR(TRANS_COLOR(0));
- RR(TRANS_COLOR(1));
+ RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
+ RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
+ RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
+ RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
RR(LINE_NUMBER);
- RR(TIMING_H(0));
- RR(TIMING_V(0));
- RR(POL_FREQ(0));
- RR(DIVISORo(0));
- RR(GLOBAL_ALPHA);
- RR(SIZE_DIG);
- RR(SIZE_LCD(0));
+ RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
+ RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
+ RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
+ RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
+ if (dss_has_feature(FEAT_GLOBAL_ALPHA))
+ RR(GLOBAL_ALPHA);
+ RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
+ RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
- RR(DEFAULT_COLOR(2));
- RR(TRANS_COLOR(2));
- RR(SIZE_LCD(2));
- RR(TIMING_H(2));
- RR(TIMING_V(2));
- RR(POL_FREQ(2));
- RR(DIVISORo(2));
+ RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
+ RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
+ RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
+ RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
+ RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
RR(CONFIG2);
}
- RR(GFX_BA0);
- RR(GFX_BA1);
- RR(GFX_POSITION);
- RR(GFX_SIZE);
- RR(GFX_ATTRIBUTES);
- RR(GFX_FIFO_THRESHOLD);
- RR(GFX_ROW_INC);
- RR(GFX_PIXEL_INC);
- RR(GFX_WINDOW_SKIP);
- RR(GFX_TABLE_BA);
-
- RR(DATA_CYCLE1(0));
- RR(DATA_CYCLE2(0));
- RR(DATA_CYCLE3(0));
-
- RR(CPR_COEF_R(0));
- RR(CPR_COEF_G(0));
- RR(CPR_COEF_B(0));
- if (dss_has_feature(FEAT_MGR_LCD2)) {
- RR(DATA_CYCLE1(2));
- RR(DATA_CYCLE2(2));
- RR(DATA_CYCLE3(2));
+ RR(OVL_BA0(OMAP_DSS_GFX));
+ RR(OVL_BA1(OMAP_DSS_GFX));
+ RR(OVL_POSITION(OMAP_DSS_GFX));
+ RR(OVL_SIZE(OMAP_DSS_GFX));
+ RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
+ RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
+ RR(OVL_ROW_INC(OMAP_DSS_GFX));
+ RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
+ RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
+ RR(OVL_TABLE_BA(OMAP_DSS_GFX));
- RR(CPR_COEF_B(2));
- RR(CPR_COEF_G(2));
- RR(CPR_COEF_R(2));
+
+ RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
+ RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
+ RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
+
+ if (dss_has_feature(FEAT_CPR)) {
+ RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
+ RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
+ RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
+ }
+ if (dss_has_feature(FEAT_MGR_LCD2)) {
+ RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
+ RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
+ RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
+
+ if (dss_has_feature(FEAT_CPR)) {
+ RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
+ RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
+ RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
+ }
}
- RR(GFX_PRELOAD);
+ if (dss_has_feature(FEAT_PRELOAD))
+ RR(OVL_PRELOAD(OMAP_DSS_GFX));
/* VID1 */
- RR(VID_BA0(0));
- RR(VID_BA1(0));
- RR(VID_POSITION(0));
- RR(VID_SIZE(0));
- RR(VID_ATTRIBUTES(0));
- RR(VID_FIFO_THRESHOLD(0));
- RR(VID_ROW_INC(0));
- RR(VID_PIXEL_INC(0));
- RR(VID_FIR(0));
- RR(VID_PICTURE_SIZE(0));
- RR(VID_ACCU0(0));
- RR(VID_ACCU1(0));
-
- RR(VID_FIR_COEF_H(0, 0));
- RR(VID_FIR_COEF_H(0, 1));
- RR(VID_FIR_COEF_H(0, 2));
- RR(VID_FIR_COEF_H(0, 3));
- RR(VID_FIR_COEF_H(0, 4));
- RR(VID_FIR_COEF_H(0, 5));
- RR(VID_FIR_COEF_H(0, 6));
- RR(VID_FIR_COEF_H(0, 7));
-
- RR(VID_FIR_COEF_HV(0, 0));
- RR(VID_FIR_COEF_HV(0, 1));
- RR(VID_FIR_COEF_HV(0, 2));
- RR(VID_FIR_COEF_HV(0, 3));
- RR(VID_FIR_COEF_HV(0, 4));
- RR(VID_FIR_COEF_HV(0, 5));
- RR(VID_FIR_COEF_HV(0, 6));
- RR(VID_FIR_COEF_HV(0, 7));
-
- RR(VID_CONV_COEF(0, 0));
- RR(VID_CONV_COEF(0, 1));
- RR(VID_CONV_COEF(0, 2));
- RR(VID_CONV_COEF(0, 3));
- RR(VID_CONV_COEF(0, 4));
-
- RR(VID_FIR_COEF_V(0, 0));
- RR(VID_FIR_COEF_V(0, 1));
- RR(VID_FIR_COEF_V(0, 2));
- RR(VID_FIR_COEF_V(0, 3));
- RR(VID_FIR_COEF_V(0, 4));
- RR(VID_FIR_COEF_V(0, 5));
- RR(VID_FIR_COEF_V(0, 6));
- RR(VID_FIR_COEF_V(0, 7));
-
- RR(VID_PRELOAD(0));
+ RR(OVL_BA0(OMAP_DSS_VIDEO1));
+ RR(OVL_BA1(OMAP_DSS_VIDEO1));
+ RR(OVL_POSITION(OMAP_DSS_VIDEO1));
+ RR(OVL_SIZE(OMAP_DSS_VIDEO1));
+ RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
+ RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
+ RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
+ RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
+ RR(OVL_FIR(OMAP_DSS_VIDEO1));
+ RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 5; i++)
+ RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
+
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
+ }
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
+ RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
+ RR(OVL_FIR2(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
+ if (dss_has_feature(FEAT_PRELOAD))
+ RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
/* VID2 */
- RR(VID_BA0(1));
- RR(VID_BA1(1));
- RR(VID_POSITION(1));
- RR(VID_SIZE(1));
- RR(VID_ATTRIBUTES(1));
- RR(VID_FIFO_THRESHOLD(1));
- RR(VID_ROW_INC(1));
- RR(VID_PIXEL_INC(1));
- RR(VID_FIR(1));
- RR(VID_PICTURE_SIZE(1));
- RR(VID_ACCU0(1));
- RR(VID_ACCU1(1));
-
- RR(VID_FIR_COEF_H(1, 0));
- RR(VID_FIR_COEF_H(1, 1));
- RR(VID_FIR_COEF_H(1, 2));
- RR(VID_FIR_COEF_H(1, 3));
- RR(VID_FIR_COEF_H(1, 4));
- RR(VID_FIR_COEF_H(1, 5));
- RR(VID_FIR_COEF_H(1, 6));
- RR(VID_FIR_COEF_H(1, 7));
-
- RR(VID_FIR_COEF_HV(1, 0));
- RR(VID_FIR_COEF_HV(1, 1));
- RR(VID_FIR_COEF_HV(1, 2));
- RR(VID_FIR_COEF_HV(1, 3));
- RR(VID_FIR_COEF_HV(1, 4));
- RR(VID_FIR_COEF_HV(1, 5));
- RR(VID_FIR_COEF_HV(1, 6));
- RR(VID_FIR_COEF_HV(1, 7));
-
- RR(VID_CONV_COEF(1, 0));
- RR(VID_CONV_COEF(1, 1));
- RR(VID_CONV_COEF(1, 2));
- RR(VID_CONV_COEF(1, 3));
- RR(VID_CONV_COEF(1, 4));
-
- RR(VID_FIR_COEF_V(1, 0));
- RR(VID_FIR_COEF_V(1, 1));
- RR(VID_FIR_COEF_V(1, 2));
- RR(VID_FIR_COEF_V(1, 3));
- RR(VID_FIR_COEF_V(1, 4));
- RR(VID_FIR_COEF_V(1, 5));
- RR(VID_FIR_COEF_V(1, 6));
- RR(VID_FIR_COEF_V(1, 7));
-
- RR(VID_PRELOAD(1));
+ RR(OVL_BA0(OMAP_DSS_VIDEO2));
+ RR(OVL_BA1(OMAP_DSS_VIDEO2));
+ RR(OVL_POSITION(OMAP_DSS_VIDEO2));
+ RR(OVL_SIZE(OMAP_DSS_VIDEO2));
+ RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
+ RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
+ RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
+ RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
+ RR(OVL_FIR(OMAP_DSS_VIDEO2));
+ RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 5; i++)
+ RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
+
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
+ }
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
+ RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
+ RR(OVL_FIR2(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
+ if (dss_has_feature(FEAT_PRELOAD))
+ RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
if (dss_has_feature(FEAT_CORE_CLK_DIV))
RR(DIVISOR);
* the context is fully restored
*/
RR(IRQENABLE);
+
+ DSSDBG("context restored\n");
}
#undef SR
#undef RR
-static inline void enable_clocks(bool enable)
+int dispc_runtime_get(void)
{
- if (enable)
- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
- else
- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
+ int r;
+
+ DSSDBG("dispc_runtime_get\n");
+
+ r = pm_runtime_get_sync(&dispc.pdev->dev);
+ WARN_ON(r < 0);
+ return r < 0 ? r : 0;
+}
+
+void dispc_runtime_put(void)
+{
+ int r;
+
+ DSSDBG("dispc_runtime_put\n");
+
+ r = pm_runtime_put(&dispc.pdev->dev);
+ WARN_ON(r < 0);
}
+
bool dispc_go_busy(enum omap_channel channel)
{
int bit;
int bit;
bool enable_bit, go_bit;
- enable_clocks(1);
-
if (channel == OMAP_DSS_CHANNEL_LCD ||
channel == OMAP_DSS_CHANNEL_LCD2)
bit = 0; /* LCDENABLE */
enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
if (!enable_bit)
- goto end;
+ return;
if (channel == OMAP_DSS_CHANNEL_LCD ||
channel == OMAP_DSS_CHANNEL_LCD2)
if (go_bit) {
DSSERR("GO bit not down for channel %d\n", channel);
- goto end;
+ return;
}
DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
else
REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
-end:
- enable_clocks(0);
}
static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
+{
+ dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
+}
+
+static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
+{
+ dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
+}
+
+static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
+{
+ dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
+}
+
+static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);
- dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
+ dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
}
-static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
+static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);
- dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
+ dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
}
-static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
+static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);
- dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
+ dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
}
static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
- int vscaleup, int five_taps)
+ int vscaleup, int five_taps,
+ enum omap_color_component color_comp)
{
/* Coefficients for horizontal up-sampling */
static const struct dispc_h_coef coef_hup[8] = {
| FLD_VAL(v_coef[i].vc1, 23, 16)
| FLD_VAL(v_coef[i].vc2, 31, 24);
- _dispc_write_firh_reg(plane, i, h);
- _dispc_write_firhv_reg(plane, i, hv);
+ if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
+ _dispc_write_firh_reg(plane, i, h);
+ _dispc_write_firhv_reg(plane, i, hv);
+ } else {
+ _dispc_write_firh2_reg(plane, i, h);
+ _dispc_write_firhv2_reg(plane, i, hv);
+ }
+
}
if (five_taps) {
u32 v;
v = FLD_VAL(v_coef[i].vc00, 7, 0)
| FLD_VAL(v_coef[i].vc22, 15, 8);
- _dispc_write_firv_reg(plane, i, v);
+ if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
+ _dispc_write_firv_reg(plane, i, v);
+ else
+ _dispc_write_firv2_reg(plane, i, v);
}
}
}
ct = &ctbl_bt601_5;
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
-
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
+ CVAL(ct->rcr, ct->ry));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
+ CVAL(ct->gy, ct->rcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
+ CVAL(ct->gcb, ct->gcr));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
+ CVAL(ct->bcr, ct->by));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
+ CVAL(0, ct->bcb));
+
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
+ CVAL(ct->rcr, ct->ry));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
+ CVAL(ct->gy, ct->rcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
+ CVAL(ct->gcb, ct->gcr));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
+ CVAL(ct->bcr, ct->by));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
+ CVAL(0, ct->bcb));
#undef CVAL
- REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
- REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
+ ct->full_range, 11, 11);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
+ ct->full_range, 11, 11);
}
static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
{
- const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
- DISPC_VID_BA0(0),
- DISPC_VID_BA0(1) };
-
- dispc_write_reg(ba0_reg[plane], paddr);
+ dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
}
static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
{
- const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
- DISPC_VID_BA1(0),
- DISPC_VID_BA1(1) };
+ dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
+}
+
+static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
+{
+ dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
+}
- dispc_write_reg(ba1_reg[plane], paddr);
+static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
+{
+ dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
}
static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
{
- const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
- DISPC_VID_POSITION(0),
- DISPC_VID_POSITION(1) };
-
u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
- dispc_write_reg(pos_reg[plane], val);
+
+ dispc_write_reg(DISPC_OVL_POSITION(plane), val);
}
static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
{
- const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
- DISPC_VID_PICTURE_SIZE(0),
- DISPC_VID_PICTURE_SIZE(1) };
u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
- dispc_write_reg(siz_reg[plane], val);
+
+ if (plane == OMAP_DSS_GFX)
+ dispc_write_reg(DISPC_OVL_SIZE(plane), val);
+ else
+ dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
}
static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
{
u32 val;
- const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
- DISPC_VID_SIZE(1) };
BUG_ON(plane == OMAP_DSS_GFX);
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
- dispc_write_reg(vsi_reg[plane-1], val);
+
+ dispc_write_reg(DISPC_OVL_SIZE(plane), val);
}
static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
plane == OMAP_DSS_VIDEO1)
return;
- REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
}
static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
{
- const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
- DISPC_VID_PIXEL_INC(0),
- DISPC_VID_PIXEL_INC(1) };
-
- dispc_write_reg(ri_reg[plane], inc);
+ dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
}
static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
{
- const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
- DISPC_VID_ROW_INC(0),
- DISPC_VID_ROW_INC(1) };
-
- dispc_write_reg(ri_reg[plane], inc);
+ dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
}
static void _dispc_set_color_mode(enum omap_plane plane,
enum omap_color_mode color_mode)
{
u32 m = 0;
-
- switch (color_mode) {
- case OMAP_DSS_COLOR_CLUT1:
- m = 0x0; break;
- case OMAP_DSS_COLOR_CLUT2:
- m = 0x1; break;
- case OMAP_DSS_COLOR_CLUT4:
- m = 0x2; break;
- case OMAP_DSS_COLOR_CLUT8:
- m = 0x3; break;
- case OMAP_DSS_COLOR_RGB12U:
- m = 0x4; break;
- case OMAP_DSS_COLOR_ARGB16:
- m = 0x5; break;
- case OMAP_DSS_COLOR_RGB16:
- m = 0x6; break;
- case OMAP_DSS_COLOR_RGB24U:
- m = 0x8; break;
- case OMAP_DSS_COLOR_RGB24P:
- m = 0x9; break;
- case OMAP_DSS_COLOR_YUV2:
- m = 0xa; break;
- case OMAP_DSS_COLOR_UYVY:
- m = 0xb; break;
- case OMAP_DSS_COLOR_ARGB32:
- m = 0xc; break;
- case OMAP_DSS_COLOR_RGBA32:
- m = 0xd; break;
- case OMAP_DSS_COLOR_RGBX32:
- m = 0xe; break;
- default:
- BUG(); break;
+ if (plane != OMAP_DSS_GFX) {
+ switch (color_mode) {
+ case OMAP_DSS_COLOR_NV12:
+ m = 0x0; break;
+ case OMAP_DSS_COLOR_RGB12U:
+ m = 0x1; break;
+ case OMAP_DSS_COLOR_RGBA16:
+ m = 0x2; break;
+ case OMAP_DSS_COLOR_RGBX16:
+ m = 0x4; break;
+ case OMAP_DSS_COLOR_ARGB16:
+ m = 0x5; break;
+ case OMAP_DSS_COLOR_RGB16:
+ m = 0x6; break;
+ case OMAP_DSS_COLOR_ARGB16_1555:
+ m = 0x7; break;
+ case OMAP_DSS_COLOR_RGB24U:
+ m = 0x8; break;
+ case OMAP_DSS_COLOR_RGB24P:
+ m = 0x9; break;
+ case OMAP_DSS_COLOR_YUV2:
+ m = 0xa; break;
+ case OMAP_DSS_COLOR_UYVY:
+ m = 0xb; break;
+ case OMAP_DSS_COLOR_ARGB32:
+ m = 0xc; break;
+ case OMAP_DSS_COLOR_RGBA32:
+ m = 0xd; break;
+ case OMAP_DSS_COLOR_RGBX32:
+ m = 0xe; break;
+ case OMAP_DSS_COLOR_XRGB16_1555:
+ m = 0xf; break;
+ default:
+ BUG(); break;
+ }
+ } else {
+ switch (color_mode) {
+ case OMAP_DSS_COLOR_CLUT1:
+ m = 0x0; break;
+ case OMAP_DSS_COLOR_CLUT2:
+ m = 0x1; break;
+ case OMAP_DSS_COLOR_CLUT4:
+ m = 0x2; break;
+ case OMAP_DSS_COLOR_CLUT8:
+ m = 0x3; break;
+ case OMAP_DSS_COLOR_RGB12U:
+ m = 0x4; break;
+ case OMAP_DSS_COLOR_ARGB16:
+ m = 0x5; break;
+ case OMAP_DSS_COLOR_RGB16:
+ m = 0x6; break;
+ case OMAP_DSS_COLOR_ARGB16_1555:
+ m = 0x7; break;
+ case OMAP_DSS_COLOR_RGB24U:
+ m = 0x8; break;
+ case OMAP_DSS_COLOR_RGB24P:
+ m = 0x9; break;
+ case OMAP_DSS_COLOR_YUV2:
+ m = 0xa; break;
+ case OMAP_DSS_COLOR_UYVY:
+ m = 0xb; break;
+ case OMAP_DSS_COLOR_ARGB32:
+ m = 0xc; break;
+ case OMAP_DSS_COLOR_RGBA32:
+ m = 0xd; break;
+ case OMAP_DSS_COLOR_RGBX32:
+ m = 0xe; break;
+ case OMAP_DSS_COLOR_XRGB16_1555:
+ m = 0xf; break;
+ default:
+ BUG(); break;
+ }
}
- REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
}
-static void _dispc_set_channel_out(enum omap_plane plane,
+void dispc_set_channel_out(enum omap_plane plane,
enum omap_channel channel)
{
int shift;
return;
}
- val = dispc_read_reg(dispc_reg_att[plane]);
+ val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
if (dss_has_feature(FEAT_MGR_LCD2)) {
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
} else {
val = FLD_MOD(val, channel, shift, shift);
}
- dispc_write_reg(dispc_reg_att[plane], val);
+ dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
}
-void dispc_set_burst_size(enum omap_plane plane,
+static void dispc_set_burst_size(enum omap_plane plane,
enum omap_burst_size burst_size)
{
int shift;
- u32 val;
-
- enable_clocks(1);
switch (plane) {
case OMAP_DSS_GFX:
return;
}
- val = dispc_read_reg(dispc_reg_att[plane]);
- val = FLD_MOD(val, burst_size, shift+1, shift);
- dispc_write_reg(dispc_reg_att[plane], val);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
+}
- enable_clocks(0);
+static void dispc_configure_burst_sizes(void)
+{
+ int i;
+ const int burst_size = BURST_SIZE_X8;
+
+ /* Configure burst size always to maximum size */
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i)
+ dispc_set_burst_size(i, burst_size);
+}
+
+u32 dispc_get_burst_size(enum omap_plane plane)
+{
+ unsigned unit = dss_feat_get_burst_size_unit();
+ /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
+ return unit * 8;
}
void dispc_enable_gamma_table(bool enable)
REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
}
+void dispc_enable_cpr(enum omap_channel channel, bool enable)
+{
+ u16 reg;
+
+ if (channel == OMAP_DSS_CHANNEL_LCD)
+ reg = DISPC_CONFIG;
+ else if (channel == OMAP_DSS_CHANNEL_LCD2)
+ reg = DISPC_CONFIG2;
+ else
+ return;
+
+ REG_FLD_MOD(reg, enable, 15, 15);
+}
+
+void dispc_set_cpr_coef(enum omap_channel channel,
+ struct omap_dss_cpr_coefs *coefs)
+{
+ u32 coef_r, coef_g, coef_b;
+
+ if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
+ return;
+
+ coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
+ FLD_VAL(coefs->rb, 9, 0);
+ coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
+ FLD_VAL(coefs->gb, 9, 0);
+ coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
+ FLD_VAL(coefs->bb, 9, 0);
+
+ dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
+ dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
+ dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
+}
+
static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
{
u32 val;
BUG_ON(plane == OMAP_DSS_GFX);
- val = dispc_read_reg(dispc_reg_att[plane]);
+ val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
val = FLD_MOD(val, enable, 9, 9);
- dispc_write_reg(dispc_reg_att[plane], val);
+ dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
}
void dispc_enable_replication(enum omap_plane plane, bool enable)
else
bit = 10;
- enable_clocks(1);
- REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
- enable_clocks(0);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
}
void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
u32 val;
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
- enable_clocks(1);
- dispc_write_reg(DISPC_SIZE_LCD(channel), val);
- enable_clocks(0);
+ dispc_write_reg(DISPC_SIZE_MGR(channel), val);
}
void dispc_set_digit_size(u16 width, u16 height)
u32 val;
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
- enable_clocks(1);
- dispc_write_reg(DISPC_SIZE_DIG, val);
- enable_clocks(0);
+ dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
}
static void dispc_read_plane_fifo_sizes(void)
{
- const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
- DISPC_VID_FIFO_SIZE_STATUS(0),
- DISPC_VID_FIFO_SIZE_STATUS(1) };
u32 size;
int plane;
u8 start, end;
+ u32 unit;
- enable_clocks(1);
+ unit = dss_feat_get_buffer_size_unit();
dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
- size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
+ size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
+ size *= unit;
dispc.fifo_size[plane] = size;
}
-
- enable_clocks(0);
}
u32 dispc_get_plane_fifo_size(enum omap_plane plane)
return dispc.fifo_size[plane];
}
-void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
+void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
{
- const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
- DISPC_VID_FIFO_THRESHOLD(0),
- DISPC_VID_FIFO_THRESHOLD(1) };
u8 hi_start, hi_end, lo_start, lo_end;
+ u32 unit;
- enable_clocks(1);
+ unit = dss_feat_get_buffer_size_unit();
- DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
- plane,
- REG_GET(ftrs_reg[plane], 11, 0),
- REG_GET(ftrs_reg[plane], 27, 16),
- low, high);
+ WARN_ON(low % unit != 0);
+ WARN_ON(high % unit != 0);
+
+ low /= unit;
+ high /= unit;
dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
- dispc_write_reg(ftrs_reg[plane],
+ DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
+ plane,
+ REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
+ lo_start, lo_end),
+ REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
+ hi_start, hi_end),
+ low, high);
+
+ dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
FLD_VAL(high, hi_start, hi_end) |
FLD_VAL(low, lo_start, lo_end));
-
- enable_clocks(0);
}
void dispc_enable_fifomerge(bool enable)
{
- enable_clocks(1);
-
DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
-
- enable_clocks(0);
}
-static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
+static void _dispc_set_fir(enum omap_plane plane,
+ int hinc, int vinc,
+ enum omap_color_component color_comp)
{
u32 val;
- const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
- DISPC_VID_FIR(1) };
- u8 hinc_start, hinc_end, vinc_start, vinc_end;
- BUG_ON(plane == OMAP_DSS_GFX);
+ if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
+ u8 hinc_start, hinc_end, vinc_start, vinc_end;
- dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
- dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
+ dss_feat_get_reg_field(FEAT_REG_FIRHINC,
+ &hinc_start, &hinc_end);
+ dss_feat_get_reg_field(FEAT_REG_FIRVINC,
+ &vinc_start, &vinc_end);
+ val = FLD_VAL(vinc, vinc_start, vinc_end) |
+ FLD_VAL(hinc, hinc_start, hinc_end);
- val = FLD_VAL(vinc, vinc_start, vinc_end) |
- FLD_VAL(hinc, hinc_start, hinc_end);
-
- dispc_write_reg(fir_reg[plane-1], val);
+ dispc_write_reg(DISPC_OVL_FIR(plane), val);
+ } else {
+ val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
+ dispc_write_reg(DISPC_OVL_FIR2(plane), val);
+ }
}
static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;
- const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
- DISPC_VID_ACCU0(1) };
u8 hor_start, hor_end, vert_start, vert_end;
- BUG_ON(plane == OMAP_DSS_GFX);
-
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
- dispc_write_reg(ac0_reg[plane-1], val);
+ dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
}
static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;
- const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
- DISPC_VID_ACCU1(1) };
u8 hor_start, hor_end, vert_start, vert_end;
- BUG_ON(plane == OMAP_DSS_GFX);
-
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
- dispc_write_reg(ac1_reg[plane-1], val);
+ dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
}
+static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
+{
+ u32 val;
-static void _dispc_set_scaling(enum omap_plane plane,
+ val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+ dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
+}
+
+static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
+{
+ u32 val;
+
+ val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+ dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
+}
+
+static void _dispc_set_scale_param(enum omap_plane plane,
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
- bool ilace, bool five_taps,
- bool fieldmode)
+ bool five_taps, u8 rotation,
+ enum omap_color_component color_comp)
{
- int fir_hinc;
- int fir_vinc;
+ int fir_hinc, fir_vinc;
int hscaleup, vscaleup;
- int accu0 = 0;
- int accu1 = 0;
- u32 l;
-
- BUG_ON(plane == OMAP_DSS_GFX);
hscaleup = orig_width <= out_width;
vscaleup = orig_height <= out_height;
- _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
+ _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
- if (!orig_width || orig_width == out_width)
- fir_hinc = 0;
- else
- fir_hinc = 1024 * orig_width / out_width;
+ fir_hinc = 1024 * orig_width / out_width;
+ fir_vinc = 1024 * orig_height / out_height;
- if (!orig_height || orig_height == out_height)
- fir_vinc = 0;
- else
- fir_vinc = 1024 * orig_height / out_height;
+ _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
+}
- _dispc_set_fir(plane, fir_hinc, fir_vinc);
+static void _dispc_set_scaling_common(enum omap_plane plane,
+ u16 orig_width, u16 orig_height,
+ u16 out_width, u16 out_height,
+ bool ilace, bool five_taps,
+ bool fieldmode, enum omap_color_mode color_mode,
+ u8 rotation)
+{
+ int accu0 = 0;
+ int accu1 = 0;
+ u32 l;
- l = dispc_read_reg(dispc_reg_att[plane]);
+ _dispc_set_scale_param(plane, orig_width, orig_height,
+ out_width, out_height, five_taps,
+ rotation, DISPC_COLOR_COMPONENT_RGB_Y);
+ l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
/* RESIZEENABLE and VERTICALTAPS */
l &= ~((0x3 << 5) | (0x1 << 21));
- l |= fir_hinc ? (1 << 5) : 0;
- l |= fir_vinc ? (1 << 6) : 0;
+ l |= (orig_width != out_width) ? (1 << 5) : 0;
+ l |= (orig_height != out_height) ? (1 << 6) : 0;
l |= five_taps ? (1 << 21) : 0;
/* VRESIZECONF and HRESIZECONF */
if (dss_has_feature(FEAT_RESIZECONF)) {
l &= ~(0x3 << 7);
- l |= hscaleup ? 0 : (1 << 7);
- l |= vscaleup ? 0 : (1 << 8);
+ l |= (orig_width <= out_width) ? 0 : (1 << 7);
+ l |= (orig_height <= out_height) ? 0 : (1 << 8);
}
/* LINEBUFFERSPLIT */
l |= five_taps ? (1 << 22) : 0;
}
- dispc_write_reg(dispc_reg_att[plane], l);
+ dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
/*
* field 0 = even field = bottom field
*/
if (ilace && !fieldmode) {
accu1 = 0;
- accu0 = (fir_vinc / 2) & 0x3ff;
+ accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
if (accu0 >= 1024/2) {
accu1 = 1024/2;
accu0 -= accu1;
_dispc_set_vid_accu1(plane, 0, accu1);
}
+static void _dispc_set_scaling_uv(enum omap_plane plane,
+ u16 orig_width, u16 orig_height,
+ u16 out_width, u16 out_height,
+ bool ilace, bool five_taps,
+ bool fieldmode, enum omap_color_mode color_mode,
+ u8 rotation)
+{
+ int scale_x = out_width != orig_width;
+ int scale_y = out_height != orig_height;
+
+ if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
+ return;
+ if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
+ color_mode != OMAP_DSS_COLOR_UYVY &&
+ color_mode != OMAP_DSS_COLOR_NV12)) {
+ /* reset chroma resampling for RGB formats */
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
+ return;
+ }
+ switch (color_mode) {
+ case OMAP_DSS_COLOR_NV12:
+ /* UV is subsampled by 2 vertically*/
+ orig_height >>= 1;
+ /* UV is subsampled by 2 horz.*/
+ orig_width >>= 1;
+ break;
+ case OMAP_DSS_COLOR_YUV2:
+ case OMAP_DSS_COLOR_UYVY:
+ /*For YUV422 with 90/270 rotation,
+ *we don't upsample chroma
+ */
+ if (rotation == OMAP_DSS_ROT_0 ||
+ rotation == OMAP_DSS_ROT_180)
+ /* UV is subsampled by 2 hrz*/
+ orig_width >>= 1;
+ /* must use FIR for YUV422 if rotated */
+ if (rotation != OMAP_DSS_ROT_0)
+ scale_x = scale_y = true;
+ break;
+ default:
+ BUG();
+ }
+
+ if (out_width != orig_width)
+ scale_x = true;
+ if (out_height != orig_height)
+ scale_y = true;
+
+ _dispc_set_scale_param(plane, orig_width, orig_height,
+ out_width, out_height, five_taps,
+ rotation, DISPC_COLOR_COMPONENT_UV);
+
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
+ (scale_x || scale_y) ? 1 : 0, 8, 8);
+ /* set H scaling */
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
+ /* set V scaling */
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
+
+ _dispc_set_vid_accu2_0(plane, 0x80, 0);
+ _dispc_set_vid_accu2_1(plane, 0x80, 0);
+}
+
+static void _dispc_set_scaling(enum omap_plane plane,
+ u16 orig_width, u16 orig_height,
+ u16 out_width, u16 out_height,
+ bool ilace, bool five_taps,
+ bool fieldmode, enum omap_color_mode color_mode,
+ u8 rotation)
+{
+ BUG_ON(plane == OMAP_DSS_GFX);
+
+ _dispc_set_scaling_common(plane,
+ orig_width, orig_height,
+ out_width, out_height,
+ ilace, five_taps,
+ fieldmode, color_mode,
+ rotation);
+
+ _dispc_set_scaling_uv(plane,
+ orig_width, orig_height,
+ out_width, out_height,
+ ilace, five_taps,
+ fieldmode, color_mode,
+ rotation);
+}
+
static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
bool mirroring, enum omap_color_mode color_mode)
{
row_repeat = false;
}
- REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
if (dss_has_feature(FEAT_ROWREPEATENABLE))
- REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
+ row_repeat ? 1 : 0, 18, 18);
}
static int color_mode_to_bpp(enum omap_color_mode color_mode)
case OMAP_DSS_COLOR_CLUT4:
return 4;
case OMAP_DSS_COLOR_CLUT8:
+ case OMAP_DSS_COLOR_NV12:
return 8;
case OMAP_DSS_COLOR_RGB12U:
case OMAP_DSS_COLOR_RGB16:
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
+ case OMAP_DSS_COLOR_RGBA16:
+ case OMAP_DSS_COLOR_RGBX16:
+ case OMAP_DSS_COLOR_ARGB16_1555:
+ case OMAP_DSS_COLOR_XRGB16_1555:
return 16;
case OMAP_DSS_COLOR_RGB24P:
return 24;
return dispc_pclk_rate(channel) * vf * hf;
}
-void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
-{
- enable_clocks(1);
- _dispc_set_channel_out(plane, channel_out);
- enable_clocks(0);
-}
-
-static int _dispc_setup_plane(enum omap_plane plane,
+int dispc_setup_plane(enum omap_plane plane,
u32 paddr, u16 screen_width,
u16 pos_x, u16 pos_y,
u16 width, u16 height,
enum omap_color_mode color_mode,
bool ilace,
enum omap_dss_rotation_type rotation_type,
- u8 rotation, int mirror,
+ u8 rotation, bool mirror,
u8 global_alpha, u8 pre_mult_alpha,
- enum omap_channel channel)
+ enum omap_channel channel, u32 puv_addr)
{
const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
bool five_taps = 0;
u16 frame_height = height;
unsigned int field_offset = 0;
+ DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
+ "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
+ plane, paddr, screen_width, pos_x, pos_y,
+ width, height,
+ out_width, out_height,
+ ilace, color_mode,
+ rotation, mirror, channel);
+
if (paddr == 0)
return -EINVAL;
return -EINVAL;
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
- color_mode == OMAP_DSS_COLOR_UYVY)
+ color_mode == OMAP_DSS_COLOR_UYVY ||
+ color_mode == OMAP_DSS_COLOR_NV12)
cconv = 1;
/* Must use 5-tap filter? */
_dispc_set_plane_ba0(plane, paddr + offset0);
_dispc_set_plane_ba1(plane, paddr + offset1);
+ if (OMAP_DSS_COLOR_NV12 == color_mode) {
+ _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
+ _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
+ }
+
+
_dispc_set_row_inc(plane, row_inc);
_dispc_set_pix_inc(plane, pix_inc);
if (plane != OMAP_DSS_GFX) {
_dispc_set_scaling(plane, width, height,
out_width, out_height,
- ilace, five_taps, fieldmode);
+ ilace, five_taps, fieldmode,
+ color_mode, rotation);
_dispc_set_vid_size(plane, out_width, out_height);
_dispc_set_vid_color_conv(plane, cconv);
}
return 0;
}
-static void _dispc_enable_plane(enum omap_plane plane, bool enable)
+int dispc_enable_plane(enum omap_plane plane, bool enable)
{
- REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
+ DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
+
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
+
+ return 0;
}
static void dispc_disable_isr(void *data, u32 mask)
int r;
u32 irq;
- enable_clocks(1);
-
/* When we disable LCD output, we need to wait until frame is done.
* Otherwise the DSS is still working, and turning off the clocks
* prevents DSS from going to OFF mode */
if (r)
DSSERR("failed to unregister FRAMEDONE isr\n");
}
-
- enable_clocks(0);
}
static void _enable_digit_out(bool enable)
struct completion frame_done_completion;
int r;
- enable_clocks(1);
-
- if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
- enable_clocks(0);
+ if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
return;
- }
if (enable) {
unsigned long flags;
_omap_dispc_set_irqs();
spin_unlock_irqrestore(&dispc.irq_lock, flags);
}
-
- enable_clocks(0);
}
bool dispc_is_channel_enabled(enum omap_channel channel)
if (!dss_has_feature(FEAT_LCDENABLEPOL))
return;
- enable_clocks(1);
REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
- enable_clocks(0);
}
void dispc_lcd_enable_signal(bool enable)
if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
return;
- enable_clocks(1);
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
- enable_clocks(0);
}
void dispc_pck_free_enable(bool enable)
if (!dss_has_feature(FEAT_PCKFREEENABLE))
return;
- enable_clocks(1);
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
- enable_clocks(0);
}
void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
{
- enable_clocks(1);
if (channel == OMAP_DSS_CHANNEL_LCD2)
REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
else
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
- enable_clocks(0);
}
return;
}
- enable_clocks(1);
if (channel == OMAP_DSS_CHANNEL_LCD2)
REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
else
REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
- enable_clocks(0);
}
void dispc_set_loadmode(enum omap_dss_load_mode mode)
{
- enable_clocks(1);
REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
- enable_clocks(0);
}
void dispc_set_default_color(enum omap_channel channel, u32 color)
{
- enable_clocks(1);
dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
- enable_clocks(0);
}
u32 dispc_get_default_color(enum omap_channel channel)
channel != OMAP_DSS_CHANNEL_LCD &&
channel != OMAP_DSS_CHANNEL_LCD2);
- enable_clocks(1);
l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
- enable_clocks(0);
return l;
}
enum omap_dss_trans_key_type type,
u32 trans_key)
{
- enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
- enable_clocks(0);
}
void dispc_get_trans_key(enum omap_channel ch,
enum omap_dss_trans_key_type *type,
u32 *trans_key)
{
- enable_clocks(1);
if (type) {
if (ch == OMAP_DSS_CHANNEL_LCD)
*type = REG_GET(DISPC_CONFIG, 11, 11);
if (trans_key)
*trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
- enable_clocks(0);
}
void dispc_enable_trans_key(enum omap_channel ch, bool enable)
{
- enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
else /* OMAP_DSS_CHANNEL_LCD2 */
REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
- enable_clocks(0);
}
void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
{
if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
return;
- enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
else /* OMAP_DSS_CHANNEL_LCD2 */
REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
- enable_clocks(0);
}
bool dispc_alpha_blending_enabled(enum omap_channel ch)
{
if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
return false;
- enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
enabled = REG_GET(DISPC_CONFIG, 18, 18);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
enabled = REG_GET(DISPC_CONFIG2, 18, 18);
else
BUG();
- enable_clocks(0);
return enabled;
}
{
bool enabled;
- enable_clocks(1);
if (ch == OMAP_DSS_CHANNEL_LCD)
enabled = REG_GET(DISPC_CONFIG, 10, 10);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
enabled = REG_GET(DISPC_CONFIG2, 10, 10);
else
BUG();
- enable_clocks(0);
return enabled;
}
return;
}
- enable_clocks(1);
if (channel == OMAP_DSS_CHANNEL_LCD2)
REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
else
REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
- enable_clocks(0);
}
void dispc_set_parallel_interface_mode(enum omap_channel channel,
return;
}
- enable_clocks(1);
-
if (channel == OMAP_DSS_CHANNEL_LCD2) {
l = dispc_read_reg(DISPC_CONTROL2);
l = FLD_MOD(l, stallmode, 11, 11);
l = FLD_MOD(l, gpout1, 16, 16);
dispc_write_reg(DISPC_CONTROL, l);
}
-
- enable_clocks(0);
}
static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
FLD_VAL(vbp, 31, 20);
}
- enable_clocks(1);
dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
- enable_clocks(0);
}
/* change name to mode? */
BUG_ON(lck_div < 1);
BUG_ON(pck_div < 2);
- enable_clocks(1);
dispc_write_reg(DISPC_DIVISORo(channel),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
- enable_clocks(0);
}
static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
unsigned long dispc_fclk_rate(void)
{
+ struct platform_device *dsidev;
unsigned long r = 0;
switch (dss_get_dispc_clk_source()) {
- case DSS_CLK_SRC_FCK:
- r = dss_clk_get_rate(DSS_CLK_FCK);
+ case OMAP_DSS_CLK_SRC_FCK:
+ r = clk_get_rate(dispc.dss_clk);
+ break;
+ case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(0);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
break;
- case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
- r = dsi_get_pll_hsdiv_dispc_rate();
+ case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(1);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
break;
default:
BUG();
unsigned long dispc_lclk_rate(enum omap_channel channel)
{
+ struct platform_device *dsidev;
int lcd;
unsigned long r;
u32 l;
lcd = FLD_GET(l, 23, 16);
switch (dss_get_lcd_clk_source(channel)) {
- case DSS_CLK_SRC_FCK:
- r = dss_clk_get_rate(DSS_CLK_FCK);
+ case OMAP_DSS_CLK_SRC_FCK:
+ r = clk_get_rate(dispc.dss_clk);
+ break;
+ case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(0);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
break;
- case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
- r = dsi_get_pll_hsdiv_dispc_rate();
+ case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(1);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
break;
default:
BUG();
{
int lcd, pcd;
u32 l;
- enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
- enum dss_clk_source lcd_clk_src;
+ enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
+ enum omap_dss_clk_source lcd_clk_src;
- enable_clocks(1);
+ if (dispc_runtime_get())
+ return;
seq_printf(s, "- DISPC -\n");
seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
}
- enable_clocks(0);
+
+ dispc_runtime_put();
}
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
void dispc_dump_regs(struct seq_file *s)
{
-#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
+#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
+ if (dispc_runtime_get())
+ return;
DUMPREG(DISPC_REVISION);
DUMPREG(DISPC_SYSCONFIG);
DUMPREG(DISPC_CONTROL);
DUMPREG(DISPC_CONFIG);
DUMPREG(DISPC_CAPABLE);
- DUMPREG(DISPC_DEFAULT_COLOR(0));
- DUMPREG(DISPC_DEFAULT_COLOR(1));
- DUMPREG(DISPC_TRANS_COLOR(0));
- DUMPREG(DISPC_TRANS_COLOR(1));
+ DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
+ DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
DUMPREG(DISPC_LINE_STATUS);
DUMPREG(DISPC_LINE_NUMBER);
- DUMPREG(DISPC_TIMING_H(0));
- DUMPREG(DISPC_TIMING_V(0));
- DUMPREG(DISPC_POL_FREQ(0));
- DUMPREG(DISPC_DIVISORo(0));
- DUMPREG(DISPC_GLOBAL_ALPHA);
- DUMPREG(DISPC_SIZE_DIG);
- DUMPREG(DISPC_SIZE_LCD(0));
+ DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
+ if (dss_has_feature(FEAT_GLOBAL_ALPHA))
+ DUMPREG(DISPC_GLOBAL_ALPHA);
+ DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
+ DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
DUMPREG(DISPC_CONTROL2);
DUMPREG(DISPC_CONFIG2);
- DUMPREG(DISPC_DEFAULT_COLOR(2));
- DUMPREG(DISPC_TRANS_COLOR(2));
- DUMPREG(DISPC_TIMING_H(2));
- DUMPREG(DISPC_TIMING_V(2));
- DUMPREG(DISPC_POL_FREQ(2));
- DUMPREG(DISPC_DIVISORo(2));
- DUMPREG(DISPC_SIZE_LCD(2));
- }
-
- DUMPREG(DISPC_GFX_BA0);
- DUMPREG(DISPC_GFX_BA1);
- DUMPREG(DISPC_GFX_POSITION);
- DUMPREG(DISPC_GFX_SIZE);
- DUMPREG(DISPC_GFX_ATTRIBUTES);
- DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
- DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
- DUMPREG(DISPC_GFX_ROW_INC);
- DUMPREG(DISPC_GFX_PIXEL_INC);
- DUMPREG(DISPC_GFX_WINDOW_SKIP);
- DUMPREG(DISPC_GFX_TABLE_BA);
-
- DUMPREG(DISPC_DATA_CYCLE1(0));
- DUMPREG(DISPC_DATA_CYCLE2(0));
- DUMPREG(DISPC_DATA_CYCLE3(0));
-
- DUMPREG(DISPC_CPR_COEF_R(0));
- DUMPREG(DISPC_CPR_COEF_G(0));
- DUMPREG(DISPC_CPR_COEF_B(0));
+ DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
+ }
+
+ DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
+
+ DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
+
+ if (dss_has_feature(FEAT_CPR)) {
+ DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
+ }
if (dss_has_feature(FEAT_MGR_LCD2)) {
- DUMPREG(DISPC_DATA_CYCLE1(2));
- DUMPREG(DISPC_DATA_CYCLE2(2));
- DUMPREG(DISPC_DATA_CYCLE3(2));
-
- DUMPREG(DISPC_CPR_COEF_R(2));
- DUMPREG(DISPC_CPR_COEF_G(2));
- DUMPREG(DISPC_CPR_COEF_B(2));
- }
-
- DUMPREG(DISPC_GFX_PRELOAD);
-
- DUMPREG(DISPC_VID_BA0(0));
- DUMPREG(DISPC_VID_BA1(0));
- DUMPREG(DISPC_VID_POSITION(0));
- DUMPREG(DISPC_VID_SIZE(0));
- DUMPREG(DISPC_VID_ATTRIBUTES(0));
- DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
- DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
- DUMPREG(DISPC_VID_ROW_INC(0));
- DUMPREG(DISPC_VID_PIXEL_INC(0));
- DUMPREG(DISPC_VID_FIR(0));
- DUMPREG(DISPC_VID_PICTURE_SIZE(0));
- DUMPREG(DISPC_VID_ACCU0(0));
- DUMPREG(DISPC_VID_ACCU1(0));
-
- DUMPREG(DISPC_VID_BA0(1));
- DUMPREG(DISPC_VID_BA1(1));
- DUMPREG(DISPC_VID_POSITION(1));
- DUMPREG(DISPC_VID_SIZE(1));
- DUMPREG(DISPC_VID_ATTRIBUTES(1));
- DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
- DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
- DUMPREG(DISPC_VID_ROW_INC(1));
- DUMPREG(DISPC_VID_PIXEL_INC(1));
- DUMPREG(DISPC_VID_FIR(1));
- DUMPREG(DISPC_VID_PICTURE_SIZE(1));
- DUMPREG(DISPC_VID_ACCU0(1));
- DUMPREG(DISPC_VID_ACCU1(1));
-
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
- DUMPREG(DISPC_VID_CONV_COEF(0, 0));
- DUMPREG(DISPC_VID_CONV_COEF(0, 1));
- DUMPREG(DISPC_VID_CONV_COEF(0, 2));
- DUMPREG(DISPC_VID_CONV_COEF(0, 3));
- DUMPREG(DISPC_VID_CONV_COEF(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
-
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
- DUMPREG(DISPC_VID_CONV_COEF(1, 0));
- DUMPREG(DISPC_VID_CONV_COEF(1, 1));
- DUMPREG(DISPC_VID_CONV_COEF(1, 2));
- DUMPREG(DISPC_VID_CONV_COEF(1, 3));
- DUMPREG(DISPC_VID_CONV_COEF(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
-
- DUMPREG(DISPC_VID_PRELOAD(0));
- DUMPREG(DISPC_VID_PRELOAD(1));
-
- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
+ DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
+
+ if (dss_has_feature(FEAT_CPR)) {
+ DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
+ }
+ }
+
+ if (dss_has_feature(FEAT_PRELOAD))
+ DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
+
+ DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
+
+ DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
+ }
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
+
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
+
+ if (dss_has_feature(FEAT_FIR_COEF_V)) {
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
+ }
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
+ if (dss_has_feature(FEAT_PRELOAD)) {
+ DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
+ }
+
+ dispc_runtime_put();
#undef DUMPREG
}
l |= FLD_VAL(acbi, 11, 8);
l |= FLD_VAL(acb, 7, 0);
- enable_clocks(1);
dispc_write_reg(DISPC_POL_FREQ(channel), l);
- enable_clocks(0);
}
void dispc_set_pol_freq(enum omap_channel channel,
mask |= isr_data->mask;
}
- enable_clocks(1);
-
old_mask = dispc_read_reg(DISPC_IRQENABLE);
/* clear the irqstatus for newly enabled irqs */
dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
dispc_write_reg(DISPC_IRQENABLE, mask);
-
- enable_clocks(0);
}
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
{
u32 l;
- l = dispc_read_reg(DISPC_SYSCONFIG);
- l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
- l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
- l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
- l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
- dispc_write_reg(DISPC_SYSCONFIG, l);
-
/* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
l = dispc_read_reg(DISPC_DIVISOR);
dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
dispc_read_plane_fifo_sizes();
-}
-int dispc_enable_plane(enum omap_plane plane, bool enable)
-{
- DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
-
- enable_clocks(1);
- _dispc_enable_plane(plane, enable);
- enable_clocks(0);
-
- return 0;
-}
-
-int dispc_setup_plane(enum omap_plane plane,
- u32 paddr, u16 screen_width,
- u16 pos_x, u16 pos_y,
- u16 width, u16 height,
- u16 out_width, u16 out_height,
- enum omap_color_mode color_mode,
- bool ilace,
- enum omap_dss_rotation_type rotation_type,
- u8 rotation, bool mirror, u8 global_alpha,
- u8 pre_mult_alpha, enum omap_channel channel)
-{
- int r = 0;
-
- DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
- "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
- plane, paddr, screen_width, pos_x, pos_y,
- width, height,
- out_width, out_height,
- ilace, color_mode,
- rotation, mirror, channel);
-
- enable_clocks(1);
-
- r = _dispc_setup_plane(plane,
- paddr, screen_width,
- pos_x, pos_y,
- width, height,
- out_width, out_height,
- color_mode, ilace,
- rotation_type,
- rotation, mirror,
- global_alpha,
- pre_mult_alpha, channel);
-
- enable_clocks(0);
-
- return r;
+ dispc_configure_burst_sizes();
}
/* DISPC HW IP initialisation */
u32 rev;
int r = 0;
struct resource *dispc_mem;
+ struct clk *clk;
dispc.pdev = pdev;
+ clk = clk_get(&pdev->dev, "fck");
+ if (IS_ERR(clk)) {
+ DSSERR("can't get fck\n");
+ r = PTR_ERR(clk);
+ goto err_get_clk;
+ }
+
+ dispc.dss_clk = clk;
+
spin_lock_init(&dispc.irq_lock);
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
if (!dispc_mem) {
DSSERR("can't get IORESOURCE_MEM DISPC\n");
r = -EINVAL;
- goto fail0;
+ goto err_ioremap;
}
dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
if (!dispc.base) {
DSSERR("can't ioremap DISPC\n");
r = -ENOMEM;
- goto fail0;
+ goto err_ioremap;
}
dispc.irq = platform_get_irq(dispc.pdev, 0);
if (dispc.irq < 0) {
DSSERR("platform_get_irq failed\n");
r = -ENODEV;
- goto fail1;
+ goto err_irq;
}
r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
"OMAP DISPC", dispc.pdev);
if (r < 0) {
DSSERR("request_irq failed\n");
- goto fail1;
+ goto err_irq;
}
- enable_clocks(1);
+ pm_runtime_enable(&pdev->dev);
+
+ r = dispc_runtime_get();
+ if (r)
+ goto err_runtime_get;
_omap_dispc_initial_config();
_omap_dispc_initialize_irq();
- dispc_save_context();
-
rev = dispc_read_reg(DISPC_REVISION);
dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
- enable_clocks(0);
+ dispc_runtime_put();
return 0;
-fail1:
+
+err_runtime_get:
+ pm_runtime_disable(&pdev->dev);
+ free_irq(dispc.irq, dispc.pdev);
+err_irq:
iounmap(dispc.base);
-fail0:
+err_ioremap:
+ clk_put(dispc.dss_clk);
+err_get_clk:
return r;
}
static int omap_dispchw_remove(struct platform_device *pdev)
{
+ pm_runtime_disable(&pdev->dev);
+
+ clk_put(dispc.dss_clk);
+
free_irq(dispc.irq, dispc.pdev);
iounmap(dispc.base);
return 0;
}
+static int dispc_runtime_suspend(struct device *dev)
+{
+ dispc_save_context();
+ clk_disable(dispc.dss_clk);
+ dss_runtime_put();
+
+ return 0;
+}
+
+static int dispc_runtime_resume(struct device *dev)
+{
+ int r;
+
+ r = dss_runtime_get();
+ if (r < 0)
+ return r;
+
+ clk_enable(dispc.dss_clk);
+ dispc_restore_context();
+
+ return 0;
+}
+
+static const struct dev_pm_ops dispc_pm_ops = {
+ .runtime_suspend = dispc_runtime_suspend,
+ .runtime_resume = dispc_runtime_resume,
+};
+
static struct platform_driver omap_dispchw_driver = {
.probe = omap_dispchw_probe,
.remove = omap_dispchw_remove,
.driver = {
.name = "omapdss_dispc",
.owner = THIS_MODULE,
+ .pm = &dispc_pm_ops,
},
};
git.openpandora.org / pandora-kernel.git / blobdiff