Merge branch 'kvm-updates/2.6.36' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[pandora-kernel.git] / drivers / staging / tidspbridge / core / tiomap3430_pwr.c

diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
index 2b3ce64..b789f8f 100644 (file)
--- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
@@ -50,7 +50,7 @@
  *     Sets new DSP constraint
  */
 int handle_constraints_set(struct bridge_dev_context *dev_context,
-                                 IN void *pargs)
+                                 void *pargs)
 {
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
        u32 *constraint_val;
@@ -112,7 +112,7 @@ int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context)
                /* Disable wdt on hibernation. */
                dsp_wdt_enable(false);
 
-               if (DSP_SUCCEEDED(status)) {
+               if (!status) {
                        /* Update the Bridger Driver state */
                        dev_context->dw_brd_state = BRD_DSP_HIBERNATION;
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
@@ -142,8 +142,8 @@ int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context)
  *  ======== sleep_dsp ========
  *     Put DSP in low power consuming state.
  */
-int sleep_dsp(struct bridge_dev_context *dev_context, IN u32 dw_cmd,
-                    IN void *pargs)
+int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd,
+                    void *pargs)
 {
        int status = 0;
 #ifdef CONFIG_PM
@@ -228,7 +228,7 @@ int sleep_dsp(struct bridge_dev_context *dev_context, IN u32 dw_cmd,
 
                /* Turn off DSP Peripheral clocks */
                status = dsp_clock_disable_all(dev_context->dsp_per_clks);
-               if (DSP_FAILED(status))
+               if (status)
                        return status;
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
                else if (target_pwr_state == PWRDM_POWER_OFF) {
@@ -248,7 +248,7 @@ int sleep_dsp(struct bridge_dev_context *dev_context, IN u32 dw_cmd,
  *  ======== wake_dsp ========
  *     Wake up DSP from sleep.
  */
-int wake_dsp(struct bridge_dev_context *dev_context, IN void *pargs)
+int wake_dsp(struct bridge_dev_context *dev_context, void *pargs)
 {
        int status = 0;
 #ifdef CONFIG_PM
@@ -275,7 +275,7 @@ int wake_dsp(struct bridge_dev_context *dev_context, IN void *pargs)
  *     Enable/Disable the DSP peripheral clocks as needed..
  */
 int dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context,
-                                  IN void *pargs)
+                                  void *pargs)
 {
        u32 ext_clk = 0;
        u32 ext_clk_id = 0;
@@ -310,7 +310,7 @@ int dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context,
                status = dsp_clk_disable(bpwr_clks[clk_id_index].clk);
                dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id,
                                          false);
-               if (DSP_SUCCEEDED(status)) {
+               if (!status) {
                        (dev_context->dsp_per_clks) &=
                                (~((u32) (1 << bpwr_clks[clk_id_index].clk)));
                }
@@ -318,7 +318,7 @@ int dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context,
        case BPWR_ENABLE_CLOCK:
                status = dsp_clk_enable(bpwr_clks[clk_id_index].clk);
                dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id, true);
-               if (DSP_SUCCEEDED(status))
+               if (!status)
                        (dev_context->dsp_per_clks) |=
                                (1 << bpwr_clks[clk_id_index].clk);
                break;
@@ -336,7 +336,7 @@ int dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context,
  *  Sends prescale notification to DSP
  *
  */
-int pre_scale_dsp(struct bridge_dev_context *dev_context, IN void *pargs)
+int pre_scale_dsp(struct bridge_dev_context *dev_context, void *pargs)
 {
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
        u32 level;
@@ -370,7 +370,7 @@ int pre_scale_dsp(struct bridge_dev_context *dev_context, IN void *pargs)
  *
  */
 int post_scale_dsp(struct bridge_dev_context *dev_context,
-                                                       IN void *pargs)
+                                                       void *pargs)
 {
        int status = 0;
 #ifdef CONFIG_TIDSPBRIDGE_DVFS
@@ -430,12 +430,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
 
        switch (clock_id) {
        case BPWR_GP_TIMER5:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_per_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_per_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
@@ -443,18 +439,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        case BPWR_GP_TIMER6:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_per_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_per_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
@@ -462,18 +452,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        case BPWR_GP_TIMER7:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_per_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_per_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
@@ -481,18 +465,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        case BPWR_GP_TIMER8:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_per_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_per_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
@@ -500,18 +478,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        case BPWR_MCBSP1:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_core_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_core_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
@@ -519,18 +491,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4);
                break;
        case BPWR_MCBSP2:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_per_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_per_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
@@ -538,18 +504,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        case BPWR_MCBSP3:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_per_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_per_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
@@ -557,18 +517,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        case BPWR_MCBSP4:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_per_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_per_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
@@ -576,18 +530,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        case BPWR_MCBSP5:
-               iva2_grpsel = (u32) *((reg_uword32 *)
-                                      ((u32) (resources->dw_core_pm_base) +
-                                       0xA8));
-               mpu_grpsel = (u32) *((reg_uword32 *)
-                                     ((u32) (resources->dw_core_pm_base) +
-                                      0xA4));
+               iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+               mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
                if (enable) {
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
@@ -595,10 +543,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
                }
-               *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8))
-                   = iva2_grpsel;
-               *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4))
-                   = mpu_grpsel;
+               writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+               writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
                break;
        }
 }