Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u...

[pandora-u-boot.git] / drivers / spi / zynq_spi.c

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 2a02942..cb911c3 100644 (file)
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -8,9 +8,15 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/device_compat.h>
+#include <log.h>
 #include <malloc.h>
 #include <spi.h>
+#include <time.h>
+#include <clk.h>
 #include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -32,9 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_SPI_CR_SS_SHIFT           10      /* Slave select shift */
 
 #define ZYNQ_SPI_FIFO_DEPTH            128
-#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
-#define CONFIG_SYS_ZYNQ_SPI_WAIT       (CONFIG_SYS_HZ/100)     /* 10 ms */
-#endif
+#define ZYNQ_SPI_WAIT                  (CONFIG_SYS_HZ / 100)   /* 10 ms */
 
 /* zynq spi register set */
 struct zynq_spi_regs {
@@ -75,19 +79,12 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
        const void *blob = gd->fdt_blob;
        int node = dev_of_offset(bus);
 
-       plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus);
+       plat->regs = dev_read_addr_ptr(bus);
 
-       /* FIXME: Use 250MHz as a suitable default */
-       plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
-                                       250000000);
        plat->deactivate_delay_us = fdtdec_get_int(blob, node,
                                        "spi-deactivate-delay", 0);
        plat->activate_delay_us = fdtdec_get_int(blob, node,
                                                 "spi-activate-delay", 0);
-       plat->speed_hz = plat->frequency / 2;
-
-       debug("%s: regs=%p max-frequency=%d\n", __func__,
-             plat->regs, plat->frequency);
 
        return 0;
 }
@@ -126,13 +123,39 @@ static int zynq_spi_probe(struct udevice *bus)
 {
        struct zynq_spi_platdata *plat = dev_get_platdata(bus);
        struct zynq_spi_priv *priv = dev_get_priv(bus);
+       struct clk clk;
+       unsigned long clock;
+       int ret;
 
        priv->regs = plat->regs;
        priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
 
+       ret = clk_get_by_name(bus, "ref_clk", &clk);
+       if (ret < 0) {
+               dev_err(bus, "failed to get clock\n");
+               return ret;
+       }
+
+       clock = clk_get_rate(&clk);
+       if (IS_ERR_VALUE(clock)) {
+               dev_err(bus, "failed to get rate\n");
+               return clock;
+       }
+
+       ret = clk_enable(&clk);
+       if (ret && ret != -ENOSYS) {
+               dev_err(bus, "failed to enable clock\n");
+               return ret;
+       }
+
        /* init the zynq spi hw */
        zynq_spi_init_hw(priv);
 
+       plat->frequency = clock;
+       plat->speed_hz = plat->frequency / 2;
+
+       debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
+
        return 0;
 }
 
@@ -247,7 +270,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
                ts = get_timer(0);
                status = readl(&regs->isr);
                while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
-                       if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
+                       if (get_timer(ts) > ZYNQ_SPI_WAIT) {
                                printf("spi_xfer: Timeout! TX FIFO not full\n");
                                return -1;
                        }