#include <dm.h>
#include <dm/device_compat.h>
#include <malloc.h>
+#include <spi.h>
#include <spi-mem.h>
#include <wait_bit.h>
#include <asm/io.h>
};
static void sifive_spi_prep_device(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat)
+ struct dm_spi_slave_plat *slave_plat)
{
/* Update the chip select polarity */
if (slave_plat->mode & SPI_CS_HIGH)
}
static int sifive_spi_set_cs(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat)
+ struct dm_spi_slave_plat *slave_plat)
{
u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
}
static void sifive_spi_prep_transfer(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat,
+ struct dm_spi_slave_plat *slave_plat,
u8 *rx_ptr)
{
u32 cr;
{
struct udevice *bus = dev->parent;
struct sifive_spi *spi = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
const u8 *tx_ptr = dout;
u8 *rx_ptr = din;
u32 remaining_len;
.id = UCLASS_SPI,
.of_match = sifive_spi_ids,
.ops = &sifive_spi_ops,
- .priv_auto_alloc_size = sizeof(struct sifive_spi),
+ .priv_auto = sizeof(struct sifive_spi),
.probe = sifive_spi_probe,
};