+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
+#include <log.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
+/* MX35 and older is CSPI */
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#define MXC_CSPI
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+ u32 test;
+};
+
+#define MXC_CSPICTRL_EN BIT(0)
+#define MXC_CSPICTRL_MODE BIT(1)
+#define MXC_CSPICTRL_XCH BIT(2)
+#define MXC_CSPICTRL_SMC BIT(3)
+#define MXC_CSPICTRL_POL BIT(4)
+#define MXC_CSPICTRL_PHA BIT(5)
+#define MXC_CSPICTRL_SSCTL BIT(6)
+#define MXC_CSPICTRL_SSPOL BIT(7)
+#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_RXOVF BIT(6)
+#define MXC_CSPIPERIOD_32KHZ BIT(15)
+#define MAX_SPI_BYTES 4
+#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_TC BIT(7)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#else /* MX31 */
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_TC BIT(8)
+#define MXC_CSPICTRL_MAXBITS 0x1f
+#endif
+
+#else /* MX51 and newer is ECSPI */
+#define MXC_ECSPI
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 cfg;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+};
+
+#define MXC_CSPICTRL_EN BIT(0)
+#define MXC_CSPICTRL_MODE BIT(1)
+#define MXC_CSPICTRL_XCH BIT(2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC BIT(7)
+#define MXC_CSPICTRL_RXOVF BIT(6)
+#define MXC_CSPIPERIOD_32KHZ BIT(15)
+#define MAX_SPI_BYTES 32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+#endif
+
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
* datasheet, the correct one is in the Freescale's Linux driver */
#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
#endif
+#define MAX_CS_COUNT 4
+
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
unsigned int max_hz;
unsigned int mode;
struct gpio_desc ss;
+ struct gpio_desc cs_gpios[MAX_CS_COUNT];
+ struct udevice *dev;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
- if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(&mxcs->ss, mxcs->ss_pol);
- } else {
- if (mxcs->gpio > 0)
- gpio_set_value(mxcs->gpio, mxcs->ss_pol);
- }
+#if CONFIG_IS_ENABLED(DM_SPI)
+ struct udevice *dev = mxcs->dev;
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+ u32 cs = slave_plat->cs;
+
+ if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
+ return;
+
+ dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
+#else
+ if (mxcs->gpio > 0)
+ gpio_set_value(mxcs->gpio, mxcs->ss_pol);
+#endif
}
static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
- if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(&mxcs->ss, !(mxcs->ss_pol));
- } else {
- if (mxcs->gpio > 0)
- gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
- }
+#if CONFIG_IS_ENABLED(DM_SPI)
+ struct udevice *dev = mxcs->dev;
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+ u32 cs = slave_plat->cs;
+
+ if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
+ return;
+
+ dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
+#else
+ if (mxcs->gpio > 0)
+ gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
+#endif
}
u32 get_cspi_div(u32 div)
u32 ts;
int status;
- debug("%s: bitlen %d dout 0x%x din 0x%x\n",
- __func__, bitlen, (u32)dout, (u32)din);
+ debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
+ __func__, bitlen, (ulong)dout, (ulong)din);
mxcs->ctrl_reg = (mxcs->ctrl_reg &
~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
return 0;
}
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}
-void spi_init(void)
-{
-}
-
/*
* Some SPI devices require active chip-select over multiple
* transactions, we achieve this using a GPIO. Still, the SPI
static int mxc_spi_probe(struct udevice *bus)
{
- struct mxc_spi_slave *plat = bus->platdata;
- struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
+ struct mxc_spi_slave *mxcs = dev_get_plat(bus);
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;
int ret;
+ int i;
- if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
- GPIOD_IS_OUT)) {
- dev_err(bus, "No cs-gpios property\n");
- return -EINVAL;
+ ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
+ ARRAY_SIZE(mxcs->cs_gpios), 0);
+ if (ret < 0) {
+ pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
+ if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
+ continue;
+
+ ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
+ GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+ if (ret) {
+ dev_err(bus, "Setting cs %d error\n", i);
+ return ret;
+ }
}
- plat->base = dev_get_addr(bus);
- if (plat->base == FDT_ADDR_T_NONE)
+ mxcs->base = dev_read_addr(bus);
+ if (mxcs->base == FDT_ADDR_T_NONE)
return -ENODEV;
- ret = dm_gpio_set_value(&plat->ss, !(mxcs->ss_pol));
- if (ret) {
- dev_err(bus, "Setting cs error\n");
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret)
return ret;
- }
+ clk_enable(&clk);
+
+ mxcs->max_hz = clk_get_rate(&clk);
+#else
mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
20000000);
+#endif
return 0;
}
static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
- struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
+ struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
static int mxc_spi_claim_bus(struct udevice *dev)
{
- struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+ mxcs->dev = dev;
return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}
static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
- /* Nothing to do */
+ struct mxc_spi_slave *mxcs = dev_get_plat(bus);
+
+ mxcs->max_hz = speed;
+
return 0;
}
static int mxc_spi_set_mode(struct udevice *bus, uint mode)
{
- struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
+ struct mxc_spi_slave *mxcs = dev_get_plat(bus);
mxcs->mode = mode;
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
.id = UCLASS_SPI,
.of_match = mxc_spi_ids,
.ops = &mxc_spi_ops,
- .platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
+ .plat_auto = sizeof(struct mxc_spi_slave),
.probe = mxc_spi_probe,
};
#endif
git.openpandora.org / pandora-u-boot.git / blobdiff