* Haikun Wang (B53464@freescale.com)
*/
+#include <linux/math64.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+/* linux/include/time.h */
+#define NSEC_PER_SEC 1000000000L
+
DECLARE_GLOBAL_DATA_PTR;
-/* fsl_dspi_platdata flags */
+/* fsl_dspi_plat flags */
#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* idle data value */
DSPI_CTAR_DT(15))
/**
- * struct fsl_dspi_platdata - platform data for Freescale DSPI
+ * struct fsl_dspi_plat - platform data for Freescale DSPI
*
* @flags: Flags for DSPI DSPI_FLAG_...
* @speed_hz: Default SCK frequency
* @num_chipselect: Number of DSPI chipselect signals
* @regs_addr: Base address of DSPI registers
*/
-struct fsl_dspi_platdata {
+struct fsl_dspi_plat {
uint flags;
uint speed_hz;
uint num_chipselect;
return -EINVAL;
}
+static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
+ unsigned long clkrate)
+{
+ int scale_needed, scale, minscale = INT_MAX;
+ int pscale_tbl[4] = {1, 3, 5, 7};
+ u32 remainder;
+ int i, j;
+
+ scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
+ &remainder);
+ if (remainder)
+ scale_needed++;
+
+ for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
+ for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
+ scale = pscale_tbl[i] * (2 << j);
+ if (scale >= scale_needed) {
+ if (scale < minscale) {
+ minscale = scale;
+ *psc = i;
+ *sc = j;
+ }
+ break;
+ }
+ }
+
+ if (minscale == INT_MAX) {
+ pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
+ delay_ns, clkrate);
+ *psc = ARRAY_SIZE(pscale_tbl) - 1;
+ *sc = DSPI_CTAR_SCALE_BITS;
+ }
+}
+
static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
{
int ret;
static int fsl_dspi_child_pre_probe(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
+ u32 cs_sck_delay = 0, sck_cs_delay = 0;
+ unsigned char pcssck = 0, cssck = 0;
+ unsigned char pasc = 0, asc = 0;
if (slave_plat->cs >= priv->num_chipselect) {
debug("DSPI invalid chipselect number %d(max %d)!\n",
return -EINVAL;
}
- priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
+ ofnode_read_u32(dev->node, "fsl,spi-cs-sck-delay", &cs_sck_delay);
+ ofnode_read_u32(dev->node, "fsl,spi-sck-cs-delay", &sck_cs_delay);
+
+ /* Set PCS to SCK delay scale values */
+ ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
+
+ /* Set After SCK delay scale values */
+ ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
+
+ priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
+ DSPI_CTAR_PCSSCK(pcssck) |
+ DSPI_CTAR_PASC(pasc);
debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
static int fsl_dspi_probe(struct udevice *bus)
{
- struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
+ struct fsl_dspi_plat *plat = dev_get_plat(bus);
struct fsl_dspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
uint mcr_cfg_val;
uint sr_val;
struct fsl_dspi_priv *priv;
struct udevice *bus = dev->parent;
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
priv = dev_get_priv(bus);
{
struct udevice *bus = dev->parent;
struct fsl_dspi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
/* halt module */
dspi_halt(priv, 1);
return 0;
}
-static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
+static int fsl_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct fsl_dspi_platdata *plat = bus->platdata;
+ struct fsl_dspi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
- addr = devfdt_get_addr(bus);
+ addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE) {
debug("DSPI: Can't get base address or size\n");
return -ENOMEM;
const void *dout, void *din, unsigned long flags)
{
struct fsl_dspi_priv *priv;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct udevice *bus;
bus = dev->parent;
.id = UCLASS_SPI,
.of_match = fsl_dspi_ids,
.ops = &fsl_dspi_ops,
- .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
- .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
+ .of_to_plat = fsl_dspi_of_to_plat,
+ .plat_auto = sizeof(struct fsl_dspi_plat),
+ .priv_auto = sizeof(struct fsl_dspi_priv),
.probe = fsl_dspi_probe,
.child_pre_probe = fsl_dspi_child_pre_probe,
.bind = fsl_dspi_bind,